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author | Gabor Juhos <juhosg@openwrt.org> | 2010-08-31 20:13:47 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2010-08-31 20:13:47 +0000 |
commit | 47f8fd1dde5d2778cad79313f444a03934d5d0b4 (patch) | |
tree | 87d1372d917c4e5903da0a42ecdfed9676f96280 /target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx | |
parent | 4ca54a5b3995b80dc814165c244a1d597bfacca1 (diff) | |
download | upstream-47f8fd1dde5d2778cad79313f444a03934d5d0b4.tar.gz upstream-47f8fd1dde5d2778cad79313f444a03934d5d0b4.tar.bz2 upstream-47f8fd1dde5d2778cad79313f444a03934d5d0b4.zip |
ar71xx: rewrite SPI drivers for the RB4xx boards
* add a new SPI controller driver
* add SPI driver for the CPLD chip
* convert the NAND driver
* enable the mikroSD slot
* enable more LEDs
SVN-Revision: 22863
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx')
-rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h new file mode 100644 index 0000000000..5b17e94b64 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h @@ -0,0 +1,48 @@ +/* + * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define CPLD_GPIO_nLED1 0 +#define CPLD_GPIO_nLED2 1 +#define CPLD_GPIO_nLED3 2 +#define CPLD_GPIO_nLED4 3 +#define CPLD_GPIO_FAN 4 +#define CPLD_GPIO_ALE 5 +#define CPLD_GPIO_CLE 6 +#define CPLD_GPIO_nCE 7 +#define CPLD_GPIO_nLED5 8 + +#define CPLD_NUM_GPIOS 9 + +#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) +#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) +#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) +#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) +#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) +#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) +#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) +#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) +#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) + +struct rb4xx_cpld_platform_data { + unsigned gpio_base; +}; + +extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); +extern int rb4xx_cpld_read(unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_read_from(unsigned addr, + unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); |