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| author | John Crispin <john@openwrt.org> | 2016-03-23 12:52:17 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2016-03-23 12:52:17 +0000 |
| commit | b269a3520d4e9e7855e383d0c0ad750d446d42e5 (patch) | |
| tree | 78a69964c14af724a1e5e4c422d506c6faf9413a /target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | |
| parent | 26d18d4e072201f7620c3daf8fabfb33400630b5 (diff) | |
| download | upstream-b269a3520d4e9e7855e383d0c0ad750d446d42e5.tar.gz upstream-b269a3520d4e9e7855e383d0c0ad750d446d42e5.tar.bz2 upstream-b269a3520d4e9e7855e383d0c0ad750d446d42e5.zip | |
Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x"
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some
boards. These boards depend on the preset values of u-boot which may
differ.
This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49071
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 6445023ec4..2f2825f945 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -830,9 +830,7 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, iounmap(base); } -void __init ath79_setup_qca955x_eth_cfg(u32 mask, - unsigned int rxd, unsigned int rxdv, - unsigned int txd, unsigned int txe) +void __init ath79_setup_qca955x_eth_cfg(u32 mask) { void __iomem *base; u32 t, m; @@ -847,10 +845,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask, QCA955X_ETH_CFG_RMII_GE0 | QCA955X_ETH_CFG_MII_CNTL_SPEED | QCA955X_ETH_CFG_RMII_GE0_MASTER; - m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; - m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; - m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; - m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); @@ -858,10 +852,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask, t &= ~m; t |= mask; - t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; - t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; - t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; - t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); |