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authorGabor Juhos <juhosg@openwrt.org>2007-12-10 14:05:01 +0000
committerGabor Juhos <juhosg@openwrt.org>2007-12-10 14:05:01 +0000
commit9b9b83976c64fd220fde833262f6a0c385677d3b (patch)
tree945cd92a0d936c8a1ccd36da03e64e898b33bc9c /target/linux/adm5120/files/include/asm-mips
parentcf1c2554e70cdabf10eff9a55360366e7f7a06d6 (diff)
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add support for GPIO IRQs
SVN-Revision: 9700
Diffstat (limited to 'target/linux/adm5120/files/include/asm-mips')
-rw-r--r--target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_info.h5
-rw-r--r--target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h5
2 files changed, 10 insertions, 0 deletions
diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_info.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_info.h
index ac452ef30f..7d92a510bd 100644
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_info.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_info.h
@@ -68,6 +68,11 @@ extern void adm5120_halt(void);
extern void (*adm5120_board_reset)(void);
+extern void adm5120_gpio_init(void) __init;
+extern void adm5120_gpio_csx0_enable(void) __init;
+extern void adm5120_gpio_csx1_enable(void) __init;
+extern void adm5120_gpio_ew_enable(void) __init;
+
static inline int adm5120_package_pqfp(void)
{
return (adm5120_package == ADM5120_PACKAGE_PQFP);
diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
index a40175b03b..f96c7d50c7 100644
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
@@ -247,6 +247,11 @@
#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
+/* GPIO_CONF2 register bits */
+#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */
+#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */
+#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */
+
/* INT_STATUS/INT_MASK register bits */
#define SWITCH_INT_SHD BIT(0) /* Send High Done */
#define SWITCH_INT_SLD BIT(1) /* Send Low Done */