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| author | Paul Fertser <fercerpav@gmail.com> | 2020-10-27 14:02:53 +0300 |
|---|---|---|
| committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2020-11-16 14:05:24 +0100 |
| commit | 4d36569b9cab6422d31bda5501718177f2f9c990 (patch) | |
| tree | a09cc47a2b4df367c4a6110fdc6fe291dcf94727 /scripts/dl_github_archive.py | |
| parent | 03d178727aa0f60cd620f58d7df2578969e3c212 (diff) | |
| download | upstream-4d36569b9cab6422d31bda5501718177f2f9c990.tar.gz upstream-4d36569b9cab6422d31bda5501718177f2f9c990.tar.bz2 upstream-4d36569b9cab6422d31bda5501718177f2f9c990.zip | |
ath79: fix ath10k caldata extraction on some D-Link DIR-842 C3 devices
According to forum threads [0][1] and a report on IRC by Doc-Saintly
some of those boards have calibration data in a different place. Only
one alternative location is known.
Without proper board calibration data (board.bin having all 0xff bytes)
ath10k firmware still tries to load but crashes on startup with a
confusing error message.
If you're applying this patch manually on your device do not forget to
remove /lib/firmware/ath10k/pre-cal-pci-0000:00:00.0.bin and reboot to
force caldata re-extraction.
[0] https://forum.openwrt.org/t/support-for-d-link-dir842-rev-c3/41654
[1] https://forum.openwrt.org/t/d-link-dir-842-cant-access-firmware-upload-form/65454
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'scripts/dl_github_archive.py')
0 files changed, 0 insertions, 0 deletions