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authorHauke Mehrtens <hauke@hauke-m.de>2011-08-04 20:07:58 +0000
committerHauke Mehrtens <hauke@hauke-m.de>2011-08-04 20:07:58 +0000
commitb220442c75934dbd2143ea9869dc39e913e1a57f (patch)
treee5a754e6d1b06220b59609e4742c30ed89c6e5c8 /package
parent695cef4f456ac64fefb1eaf16447a23ad07914c1 (diff)
downloadupstream-b220442c75934dbd2143ea9869dc39e913e1a57f.tar.gz
upstream-b220442c75934dbd2143ea9869dc39e913e1a57f.tar.bz2
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switch: update for brcm47xx target
* remove suport for 2.4 kernel * add support for bcma bus SVN-Revision: 27904
Diffstat (limited to 'package')
-rw-r--r--package/switch/Makefile4
-rw-r--r--package/switch/src/gpio-bcm947xx.h92
-rw-r--r--package/switch/src/gpio.h2
-rw-r--r--package/switch/src/switch-adm.c58
-rw-r--r--package/switch/src/switch-core.c1
-rw-r--r--package/switch/src/switch-core.h4
-rw-r--r--package/switch/src/switch-robo.c24
7 files changed, 83 insertions, 102 deletions
diff --git a/package/switch/Makefile b/package/switch/Makefile
index 17158dac8bc..364416de793 100644
--- a/package/switch/Makefile
+++ b/package/switch/Makefile
@@ -33,10 +33,6 @@ define Build/Prepare
$(CP) ./src/* $(PKG_BUILD_DIR)/
endef
-ifeq ($(BOARD),brcm47xx)
- BUILDFLAGS := -DBROADCOM
-endif
-
define Build/Compile
$(MAKE) -C "$(LINUX_DIR)" \
CROSS_COMPILE="$(TARGET_CROSS)" \
diff --git a/package/switch/src/gpio-bcm947xx.h b/package/switch/src/gpio-bcm947xx.h
index 9135f916a76..23c221da879 100644
--- a/package/switch/src/gpio-bcm947xx.h
+++ b/package/switch/src/gpio-bcm947xx.h
@@ -1,75 +1,55 @@
#ifndef __SWITCH_GPIO_H
#define __SWITCH_GPIO_H
-#include <linux/interrupt.h>
-#ifndef BCMDRIVER
#include <linux/ssb/ssb_embedded.h>
-
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
-#define ssb ssb_bcm47xx
-#endif
-
-extern struct ssb_bus ssb;
-
+#include <linux/bcma/bcma_driver_chipcommon.h>
+#include <bcm47xx.h>
static inline u32 gpio_in(void)
{
- return ssb_gpio_in(&ssb, ~0);
+ switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ return ssb_gpio_in(&bcm47xx_bus.ssb, ~0);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+ case BCM47XX_BUS_TYPE_BCMA:
+ return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, ~0);
+#endif
+ }
+ return -EINVAL;
}
static inline u32 gpio_out(u32 mask, u32 value)
{
- return ssb_gpio_out(&ssb, mask, value);
+ switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
+#endif
+#ifdef CONFIG_BCM47XX_BCMA
+ case BCM47XX_BUS_TYPE_BCMA:
+ return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+#endif
+ }
+ return -EINVAL;
}
static inline u32 gpio_outen(u32 mask, u32 value)
{
- return ssb_gpio_outen(&ssb, mask, value);
-}
-
-static inline u32 gpio_control(u32 mask, u32 value)
-{
- return ssb_gpio_control(&ssb, mask, value);
-}
-
-static inline u32 gpio_intmask(u32 mask, u32 value)
-{
- return ssb_gpio_intmask(&ssb, mask, value);
-}
-
-static inline u32 gpio_intpolarity(u32 mask, u32 value)
-{
- return ssb_gpio_polarity(&ssb, mask, value);
-}
-
-#else
-
-#include <typedefs.h>
-#include <osl.h>
-#include <bcmdevs.h>
-#include <sbutils.h>
-#include <sbconfig.h>
-#include <sbchipc.h>
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
-#include <sbmips.h>
-#else
-#include <hndcpu.h>
+ switch (bcm47xx_bus_type) {
+#ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
+ return 0;
#endif
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-#define sbh bcm947xx_sbh
-#define sbh_lock bcm947xx_sbh_lock
+#ifdef CONFIG_BCM47XX_BCMA
+ case BCM47XX_BUS_TYPE_BCMA:
+ bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, mask, value);
+ return 0;
#endif
+ }
+ return -EINVAL;
+}
-extern void *sbh;
-extern spinlock_t sbh_lock;
-
-#define gpio_in() sb_gpioin(sbh)
-#define gpio_out(mask, value) sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
-#define gpio_outen(mask, value) sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_control(mask, value) sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_intmask(mask, value) sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
-#define gpio_intpolarity(mask, value) sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
-
-#endif /* BCMDRIVER */
#endif /* __SWITCH_GPIO_H */
diff --git a/package/switch/src/gpio.h b/package/switch/src/gpio.h
index e541cdac55c..90bafd39ed8 100644
--- a/package/switch/src/gpio.h
+++ b/package/switch/src/gpio.h
@@ -8,7 +8,7 @@
#ifndef __GPIO_H
#define __GPIO_H
-#ifdef BROADCOM
+#ifdef CONFIG_BCM47XX
#include "gpio-bcm947xx.h"
#else
#warning "Unsupported configuration."
diff --git a/package/switch/src/switch-adm.c b/package/switch/src/switch-adm.c
index fa59c3fb8d2..2aff14207b3 100644
--- a/package/switch/src/switch-adm.c
+++ b/package/switch/src/switch-adm.c
@@ -37,6 +37,10 @@
#include "switch-core.h"
#include "gpio.h"
+#ifdef CONFIG_BCM47XX
+#include <nvram.h>
+#endif
+
#define DRIVER_NAME "adm6996"
#define DRIVER_VERSION "0.01"
@@ -48,19 +52,11 @@ static int force = 0;
MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
MODULE_LICENSE("GPL");
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
module_param(eecs, int, 0);
module_param(eesk, int, 0);
module_param(eedi, int, 0);
module_param(eerc, int, 0);
module_param(force, int, 0);
-#else
-MODULE_PARM(eecs, "i");
-MODULE_PARM(eesk, "i");
-MODULE_PARM(eedi, "i");
-MODULE_PARM(eerc, "i");
-MODULE_PARM(force, "i");
-#endif
/* Minimum timing constants */
#define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */
@@ -74,8 +70,7 @@ MODULE_PARM(force, "i");
#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
-#ifdef BROADCOM
-extern char *nvram_get(char *name);
+#ifdef CONFIG_BCM47XX
/* Return gpio pin number assigned to the named pin */
/*
@@ -88,15 +83,16 @@ extern char *nvram_get(char *name);
static unsigned int get_gpiopin(char *pin_name, unsigned int def_pin)
{
char name[] = "gpioXXXX";
- char *val;
+ char val[10];
unsigned int pin;
/* Go thru all possibilities till a match in pin name */
for (pin = 0; pin < 16; pin ++) {
sprintf(name, "gpio%d", pin);
- val = nvram_get(name);
- if (val && !strcmp(val, pin_name))
- return pin;
+ if (nvram_getenv(name, val, sizeof(val)) >= 0) {
+ if (!strcmp(val, pin_name))
+ return pin;
+ }
}
return def_pin;
}
@@ -495,9 +491,16 @@ static int detect_adm(void)
{
int ret = 0;
-#ifdef BROADCOM
- int boardflags = atoi(nvram_get("boardflags"));
- int boardnum = atoi(nvram_get("boardnum"));
+#ifdef CONFIG_BCM47XX
+ char buf[20];
+ int boardflags = 0;
+ int boardnum = 0;
+
+ if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0)
+ boardflags = simple_strtoul(buf, NULL, 0);
+
+ if (nvram_getenv("boardnum", buf, sizeof(buf)) >= 0)
+ boardnum = simple_strtoul(buf, NULL, 0);
if ((boardnum == 44) && (boardflags == 0x0388)) { /* Trendware TEW-411BRP+ */
ret = 1;
@@ -515,14 +518,19 @@ static int detect_adm(void)
eedi = get_gpiopin("adm_eedi", 4);
eerc = get_gpiopin("adm_rc", 0);
- } else if ((strcmp(nvram_get("boardtype") ?: "", "bcm94710dev") == 0) &&
- (strncmp(nvram_get("boardnum") ?: "", "42", 2) == 0)) {
- /* WRT54G v1.1 hack */
- eecs = 2;
- eesk = 3;
- eedi = 5;
-
- ret = 1;
+ } else if (nvram_getenv("boardtype", buf, sizeof(buf)) >= 0) {
+ if (strcmp(buf, "bcm94710dev") == 0) {
+ if (nvram_getenv("boardnum", buf, sizeof(buf)) >= 0) {
+ if (strncmp(buf, "42", 2) == 0) {
+ /* WRT54G v1.1 hack */
+ eecs = 2;
+ eesk = 3;
+ eedi = 5;
+
+ ret = 1;
+ }
+ }
+ }
}
if (eecs)
diff --git a/package/switch/src/switch-core.c b/package/switch/src/switch-core.c
index 2e5395950e7..f5b248aadbb 100644
--- a/package/switch/src/switch-core.c
+++ b/package/switch/src/switch-core.c
@@ -394,7 +394,6 @@ switch_vlan_config *switch_parse_vlan(switch_driver *driver, char *buf)
int switch_device_registered (char* device) {
struct list_head *pos;
- switch_driver *new;
list_for_each(pos, &drivers.list) {
if (strcmp(list_entry(pos, switch_driver, list)->interface, device) == 0) {
diff --git a/package/switch/src/switch-core.h b/package/switch/src/switch-core.h
index c9ab90dde81..a2114cf92d9 100644
--- a/package/switch/src/switch-core.h
+++ b/package/switch/src/switch-core.h
@@ -9,10 +9,6 @@
#define SWITCH_MEDIA_100 2
#define SWITCH_MEDIA_FD 4
-#ifndef KERNEL_VERSION
-#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
-#endif
-
typedef int (*switch_handler)(void *driver, char *buf, int nr);
typedef struct {
diff --git a/package/switch/src/switch-robo.c b/package/switch/src/switch-robo.c
index 817fba3f48f..ec9e3373375 100644
--- a/package/switch/src/switch-robo.c
+++ b/package/switch/src/switch-robo.c
@@ -34,6 +34,10 @@
#include "switch-core.h"
#include "etc53xx.h"
+#ifdef CONFIG_BCM47XX
+#include <nvram.h>
+#endif
+
#define DRIVER_NAME "bcm53xx"
#define DRIVER_VERSION "0.02"
#define PFX "roboswitch: "
@@ -63,14 +67,6 @@
#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
-/* Only available on brcm47xx */
-#ifdef BROADCOM
-extern char *nvram_get(const char *name);
-#define getvar(str) (nvram_get(str)?:"")
-#else
-#define getvar(str) ""
-#endif
-
/* Data structure for a Roboswitch device. */
struct robo_switch {
char *device; /* The device name string (ethX) */
@@ -258,6 +254,9 @@ static int robo_switch_enable(void)
{
unsigned int i, last_port;
u16 val;
+#ifdef CONFIG_BCM47XX
+ char buf[20];
+#endif
val = robo_read16(ROBO_CTRL_PAGE, ROBO_SWITCH_MODE);
if (!(val & (1 << 1))) {
@@ -278,10 +277,13 @@ static int robo_switch_enable(void)
robo_write16(ROBO_CTRL_PAGE, i, 0);
}
+#ifdef CONFIG_BCM47XX
/* WAN port LED, except for Netgear WGT634U */
- if (strcmp(getvar("nvram_type"), "cfe") != 0)
- robo_write16(ROBO_CTRL_PAGE, 0x16, 0x1F);
-
+ if (nvram_getenv("nvram_type", buf, sizeof(buf)) >= 0) {
+ if (strcmp(buf, "cfe") != 0)
+ robo_write16(ROBO_CTRL_PAGE, 0x16, 0x1F);
+ }
+#endif
return 0;
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-23 12:35:46 +0000
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/*
 * I/O SAPIC support.
 *
 * Copyright (C) 1999 Intel Corp.
 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 * Copyright (C) 1999 VA Linux Systems
 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
 *
 * 00/04/19	D. Mosberger	Rewritten to mirror more closely the x86 I/O APIC code.
 *				In particular, we now have separate handlers for edge
 *				and level triggered interrupts.
 * 00/10/27	Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
 *				PCI to vector mapping, shared PCI interrupts.
 * 00/10/27	D. Mosberger	Document things a bit more to make them more understandable.
 *				Clean up much of the old IOSAPIC cruft.
 * 01/07/27	J.I. Lee	PCI irq routing, Platform/Legacy interrupts and fixes for
 *				ACPI S5(SoftOff) support.
 * 02/01/23	J.I. Lee	iosapic pgm fixes for PCI irq routing from _PRT
 * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt vectors in
 *                              iosapic_set_affinity(), initializations for
 *                              /proc/irq/#/smp_affinity
 * 02/04/02	P. Diefenbaugh	Cleaned up ACPI PCI IRQ routing.
 * 02/04/18	J.I. Lee	bug fix in iosapic_init_pci_irq
 * 02/04/30	J.I. Lee	bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
 *				error
 * 02/07/29	T. Kochi	Allocate interrupt vectors dynamically
 * 02/08/04	T. Kochi	Cleaned up terminology (irq, global system interrupt, vector, etc.)
 * 02/09/20	D. Mosberger	Simplified by taking advantage of ACPI's pci_irq code.
 * 03/02/19	B. Helgaas	Make pcat_compat system-wide, not per-IOSAPIC.
 *				Remove iosapic_address & gsi_base from external interfaces.
 *				Rationalize __init/__devinit attributes.
 * 04/12/04 Ashok Raj	<ashok.raj@intel.com> Intel Corporation 2004
 *				Updated to work with irq migration necessary for CPU Hotplug
 */
/*
 * Here is what the interrupt logic between a PCI device and the kernel looks like:
 *
 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD).  The
 *     device is uniquely identified by its bus--, and slot-number (the function
 *     number does not matter here because all functions share the same interrupt
 *     lines).
 *
 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
 *     Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
 *     triggered and use the same polarity).  Each interrupt line has a unique Global
 *     System Interrupt (GSI) number which can be calculated as the sum of the controller's
 *     base GSI number and the IOSAPIC pin number to which the line connects.
 *
 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
 *     into the IA-64 interrupt vector.  This interrupt vector is then sent to the CPU.
 *
 * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is used as
 *     architecture-independent interrupt handling mechanism in Linux.  As an
 *     IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
 *     mapping.  On smaller systems, we use one-to-one mapping between IA-64 vector and
 *     IRQ.  A platform can implement platform_irq_to_vector(irq) and
 *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
 *     Please see also include/asm-ia64/hw_irq.h for those APIs.
 *
 * To sum up, there are three levels of mappings involved:
 *
 *	PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
 *
 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
 * Now we use "IRQ" only for Linux IRQ's.  ISA IRQ (isa_irq) is the only exception in this
 * source code.
 */
#include <linux/config.h>

#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/pci.h>
#ifdef XEN
#include <xen/errno.h>
#endif
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/string.h>
#include <linux/bootmem.h>

#include <asm/delay.h>
#include <asm/hw_irq.h>
#include <asm/io.h>
#include <asm/iosapic.h>
#include <asm/machvec.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/system.h>


#undef DEBUG_INTERRUPT_ROUTING

#ifdef DEBUG_INTERRUPT_ROUTING
#define DBG(fmt...)	printk(fmt)
#else
#define DBG(fmt...)
#endif

#define NR_PREALLOCATE_RTE_ENTRIES	(PAGE_SIZE / sizeof(struct iosapic_rte_info))
#define RTE_PREALLOCATED	(1)

static DEFINE_SPINLOCK(iosapic_lock);

/* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */

struct iosapic_rte_info {
	struct list_head rte_list;	/* node in list of RTEs sharing the same vector */
	char __iomem	*addr;		/* base address of IOSAPIC */
	unsigned int	gsi_base;	/* first GSI assigned to this IOSAPIC */
	char		rte_index;	/* IOSAPIC RTE index */
	int		refcnt;		/* reference counter */
	unsigned int	flags;		/* flags */
} ____cacheline_aligned;

static struct iosapic_intr_info {
	struct list_head rtes;		/* RTEs using this vector (empty => not an IOSAPIC interrupt) */
	int		count;		/* # of RTEs that shares this vector */
	u32		low32;		/* current value of low word of Redirection table entry */
	unsigned int	dest;		/* destination CPU physical ID */
	unsigned char	dmode	: 3;	/* delivery mode (see iosapic.h) */
	unsigned char 	polarity: 1;	/* interrupt polarity (see iosapic.h) */
	unsigned char	trigger	: 1;	/* trigger mode (see iosapic.h) */
} iosapic_intr_info[IA64_NUM_VECTORS];

static struct iosapic {
	char __iomem	*addr;		/* base address of IOSAPIC */
	unsigned int 	gsi_base;	/* first GSI assigned to this IOSAPIC */
	unsigned short 	num_rte;	/* number of RTE in this IOSAPIC */
	int		rtes_inuse;	/* # of RTEs in use on this IOSAPIC */
#ifdef CONFIG_NUMA
	unsigned short	node;		/* numa node association via pxm */
#endif
} iosapic_lists[NR_IOSAPICS];

static unsigned char pcat_compat __devinitdata;	/* 8259 compatibility flag */

static int iosapic_kmalloc_ok;
static LIST_HEAD(free_rte_list);

/*
 * Find an IOSAPIC associated with a GSI
 */
static inline int
find_iosapic (unsigned int gsi)
{
	int i;

	for (i = 0; i < NR_IOSAPICS; i++) {
		if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
			return i;
	}

	return -1;
}

static inline int
_gsi_to_vector (unsigned int gsi)
{
	struct iosapic_intr_info *info;
	struct iosapic_rte_info *rte;

	for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
		list_for_each_entry(rte, &info->rtes, rte_list)
			if (rte->gsi_base + rte->rte_index == gsi)
				return info - iosapic_intr_info;
	return -1;
}

/*
 * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 * entry exists, return -1.
 */
inline int
gsi_to_vector (unsigned int gsi)
{
	return _gsi_to_vector(gsi);
}

int
gsi_to_irq (unsigned int gsi)
{
	unsigned long flags;
	int irq;
	/*
	 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
	 * numbers...
	 */
	spin_lock_irqsave(&iosapic_lock, flags);
	{
		irq = _gsi_to_vector(gsi);
	}
	spin_unlock_irqrestore(&iosapic_lock, flags);

	return irq;
}

static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, unsigned int vec)
{
	struct iosapic_rte_info *rte;

	list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
		if (rte->gsi_base + rte->rte_index == gsi)
			return rte;
	return NULL;
}

static void
set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
{
	unsigned long pol, trigger, dmode;
	u32 low32, high32;
	char __iomem *addr;
	int rte_index;
	char redir;
	struct iosapic_rte_info *rte;

	DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);

	rte = gsi_vector_to_rte(gsi, vector);
	if (!rte)
		return;		/* not an IOSAPIC interrupt */

	rte_index = rte->rte_index;
	addr	= rte->addr;
	pol     = iosapic_intr_info[vector].polarity;
	trigger = iosapic_intr_info[vector].trigger;
	dmode   = iosapic_intr_info[vector].dmode;

	redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;

#ifdef CONFIG_SMP
	{
		unsigned int irq;

		for (irq = 0; irq < NR_IRQS; ++irq)
			if (irq_to_vector(irq) == vector) {
				set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
				break;
			}
	}
#endif

	low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
		 (trigger << IOSAPIC_TRIGGER_SHIFT) |
		 (dmode << IOSAPIC_DELIVERY_SHIFT) |
		 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
		 vector);

	/* dest contains both id and eid */
	high32 = (dest << IOSAPIC_DEST_SHIFT);

	iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
	iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
	iosapic_intr_info[vector].low32 = low32;
	iosapic_intr_info[vector].dest = dest;
}

static void
nop (unsigned int vector)
{
	/* do nothing... */
}

void
kexec_disable_iosapic(void)
{
        struct iosapic_intr_info *info;
        struct iosapic_rte_info *rte;
        u8 vec = 0;
        for (info = iosapic_intr_info; info <
                        iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) {
                list_for_each_entry(rte, &info->rtes,
                                rte_list) {
                        iosapic_write(rte->addr,
                                        IOSAPIC_RTE_LOW(rte->rte_index),
                                        IOSAPIC_MASK|vec);
                        iosapic_eoi(rte->addr, vec);
                }
        }
}

static void
mask_irq (unsigned int irq)
{
	unsigned long flags;
	char __iomem *addr;
	u32 low32;
	int rte_index;
	ia64_vector vec = irq_to_vector(irq);
	struct iosapic_rte_info *rte;

	if (list_empty(&iosapic_intr_info[vec].rtes))
		return;			/* not an IOSAPIC interrupt! */

	spin_lock_irqsave(&iosapic_lock, flags);
	{
		/* set only the mask bit */
		low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
		list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
			addr = rte->addr;
			rte_index = rte->rte_index;
			iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
		}
	}
	spin_unlock_irqrestore(&iosapic_lock, flags);
}

static void
unmask_irq (unsigned int irq)
{
	unsigned long flags;
	char __iomem *addr;
	u32 low32;
	int rte_index;
	ia64_vector vec = irq_to_vector(irq);
	struct iosapic_rte_info *rte;

	if (list_empty(&iosapic_intr_info[vec].rtes))
		return;			/* not an IOSAPIC interrupt! */

	spin_lock_irqsave(&iosapic_lock, flags);
	{
		low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
		list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
			addr = rte->addr;
			rte_index = rte->rte_index;
			iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);