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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-15 21:16:38 +0000 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-15 21:16:38 +0000 |
| commit | dfcd340721e76af49cef4291fd24db41c13da21b (patch) | |
| tree | a5c086eb1d3fbe2d9990a4bfcf9191e8ff701cf6 /package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch | |
| parent | cd3bd6e13e5c023d62546444ef2c03d4eddf2d45 (diff) | |
| download | upstream-dfcd340721e76af49cef4291fd24db41c13da21b.tar.gz upstream-dfcd340721e76af49cef4291fd24db41c13da21b.tar.bz2 upstream-dfcd340721e76af49cef4291fd24db41c13da21b.zip | |
package/mac80211: Add linux 3.0 compatibility
Add patches from Hauke adding linux 3.0 compatibility.
Signed-off-by: Jonas Gorski <jonas.gorski+openwrt@gmail.com>
SVN-Revision: 27187
Diffstat (limited to 'package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch')
| -rw-r--r-- | package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch b/package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch index e6f08959d1..ea64014c4c 100644 --- a/package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch +++ b/package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch @@ -1,8 +1,6 @@ -diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c -index ade8655..826ed5d 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c -@@ -733,6 +733,39 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, +@@ -742,6 +742,39 @@ static void ath9k_hw_init_pll(struct ath REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_BB_DPLL2_PLL_PWD, 0x0); udelay(1000); @@ -42,7 +40,7 @@ index ade8655..826ed5d 100644 } else if (AR_SREV_9340(ah)) { u32 regval, pll2_divint, pll2_divfrac, refdiv; -@@ -774,7 +807,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, +@@ -783,7 +816,7 @@ static void ath9k_hw_init_pll(struct ath REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); @@ -51,4 +49,3 @@ index ade8655..826ed5d 100644 udelay(1000); /* Switch the core clock for ar9271 to 117Mhz */ - |