uboot-sunxi: various fixes

 - update A10-Lime support
 - fix MMC on sun5i with initializing PLL6 correctly

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>



git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39470 3c298f89-4303-0410-b956-a3cf2f4a3e73

3 files changed, 166 insertions, 0 deletions

diff --git a/package/boot/uboot-sunxi/patches/002-sun5i-give-pll6-a-sane-value.patch b/package/boot/uboot-sunxi/patches/002-sun5i-give-pll6-a-sane-value.patch
new file mode 100644
index 0000000000..b4e0ee1847
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/002-sun5i-give-pll6-a-sane-value.patch
@@ -0,0 +1,39 @@
+From 75ec90fda763b491e5169dcb6dce8abe3856d946 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Sat, 14 Dec 2013 20:58:57 +0100
+Subject: [PATCH] sun5i: Give PLL6 a sane initial value
+
+The upstream kernel does not override PLL values as set by power-on-reset
+and/or the bootloader if it can avoid doing so.
+
+The power-on-reset value for PLL6 is 2400MHz, which does not actually work,
+the kernel does not know this and 2400 / 48 is 50 MHz, so the kernel happily
+tries to use it as is for mmc.
+
+Set PLL6 to a working frequency so that the kernel can use it. This fixes
+mmc in the upstream kernel not working on sun5i.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ arch/arm/cpu/armv7/sunxi/clock.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
+index 57b136d..b9dd608 100644
+--- a/arch/arm/cpu/armv7/sunxi/clock.c
++++ b/arch/arm/cpu/armv7/sunxi/clock.c
+@@ -43,6 +43,11 @@ static void clock_init_safe(void)
+ 	sdelay(200);
+ 	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
+ 	       CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
++#ifdef CONFIG_SUN5I
++	/* Power on reset default for PLL6 is 2400 MHz, which is faster then
++	 * it can reliable do :|  Set it to a 600 MHz instead. */
++	writel(0x21009900, &ccm->pll6_cfg);
++#endif
+ #ifdef CONFIG_SUN7I
+ 	writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
+ 	writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
+-- 
+1.8.5.1
+
diff --git a/package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch b/package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch
new file mode 100644
index 0000000000..3300f42bf9
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch
@@ -0,0 +1,33 @@
+From 8f70a049daa30be894158411439a36f920f0d11c Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Wed, 15 Jan 2014 20:13:04 +0100
+Subject: [PATCH] sun5i: Tweak pll6 init value
+
+There are multiple ways to get 600 MHz from PLL6, the sun5i ccmu is very
+similar to the sun4i and sun7i ccmu.
+
+This commit changes the PLL6 initialization we do for sun5i to make the PLL6
+reg value match that of sun4i and sun7i. This also makes it closer to the
+sun5i power on default, as we are now only changing the K-factor from 3 to 1.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ arch/arm/cpu/armv7/sunxi/clock.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
+index b9dd608..54b8753 100644
+--- a/arch/arm/cpu/armv7/sunxi/clock.c
++++ b/arch/arm/cpu/armv7/sunxi/clock.c
+@@ -46,7 +46,7 @@ static void clock_init_safe(void)
+ #ifdef CONFIG_SUN5I
+ 	/* Power on reset default for PLL6 is 2400 MHz, which is faster then
+ 	 * it can reliable do :|  Set it to a 600 MHz instead. */
+-	writel(0x21009900, &ccm->pll6_cfg);
++	writel(0x21009911, &ccm->pll6_cfg);
+ #endif
+ #ifdef CONFIG_SUN7I
+ 	writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
+-- 
+1.8.5.1
+
diff --git a/package/boot/uboot-sunxi/patches/004-a10-lime-fixup.patch b/package/boot/uboot-sunxi/patches/004-a10-lime-fixup.patch
new file mode 100644
index 0000000000..32edb9c0b0
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/004-a10-lime-fixup.patch
@@ -0,0 +1,94 @@
+From eccc92de2d133957fe2c126f18a5a5faef0bb93b Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Thu, 9 Jan 2014 23:26:05 +0100
+Subject: [PATCH] sunxi: A10-OLinuXino-Lime support fixup
+
+Fix:
+-code indentation
+-dram timings, the used cas and tpr0 - tpr2 were typical sun5i / sun7i
+ settings, while they should be sun4i settings
+-Properly sort boards.cfg entry
+-Add status led support
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ board/sunxi/dram_a10_olinuxino_l.c | 40 +++++++++++++++++++-------------------
+ boards.cfg                         |  2 +-
+ 2 files changed, 21 insertions(+), 21 deletions(-)
+
+diff --git a/board/sunxi/dram_a10_olinuxino_l.c b/board/sunxi/dram_a10_olinuxino_l.c
+index 31b6542..24a1bd9 100644
+--- a/board/sunxi/dram_a10_olinuxino_l.c
++++ b/board/sunxi/dram_a10_olinuxino_l.c
+@@ -4,28 +4,28 @@
+ #include <asm/arch/dram.h>
+ 
+ static struct dram_para dram_para = {
+-       .clock = 480,
+-       .type = 3,
+-       .rank_num = 1,
+-       .density = 4096,
+-       .io_width = 16,
+-       .bus_width = 16,
+-       .cas = 9,
+-       .zq = 123,
+-       .odt_en = 0,
+-       .size = 512,
+-       .tpr0 = 0x42d899b7,
+-       .tpr1 = 0xa090,
+-       .tpr2 = 0x22a00,
+-       .tpr3 = 0,
+-       .tpr4 = 0,
+-       .tpr5 = 0,
+-       .emr1 = 0x4,
+-       .emr2 = 0x10,
+-       .emr3 = 0,
++	.clock = 480,
++	.type = 3,
++	.rank_num = 1,
++	.density = 4096,
++	.io_width = 16,
++	.bus_width = 16,
++	.cas = 6,
++	.zq = 123,
++	.odt_en = 0,
++	.size = 512,
++	.tpr0 = 0x30926692,
++	.tpr1 = 0x1090,
++	.tpr2 = 0x1a0c8,
++	.tpr3 = 0,
++	.tpr4 = 0,
++	.tpr5 = 0,
++	.emr1 = 0x4,
++	.emr2 = 0,
++	.emr3 = 0,
+ };
+ 
+ unsigned long sunxi_dram_init(void)
+ {
+-       return dramc_init(&dram_para);
++	return dramc_init(&dram_para);
+ }
+diff --git a/boards.cfg b/boards.cfg
+index eda05de..dfeb07a 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -345,6 +345,7 @@ Active  arm         armv7          s5pc1xx     samsung         goni
+ Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
+ Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
+ Active  arm         armv7          sunxi       -               sunxi               A10_MID_1GB                          sun4i:A10_MID_1GB,SPL                                                                                                             -
++Active  arm         armv7          sunxi       -               sunxi               A10-OLinuXino-Lime                   sun4i:A10_OLINUXINO_L,STATUSLED=226,SPL,SUNXI_EMAC                                                                                -
+ Active  arm         armv7          sunxi       -               sunxi               A10s-OLinuXino-M                     sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL,SUNXI_EMAC                                                     -
+ Active  arm         armv7          sunxi       -               sunxi               A10s-OLinuXino-M_FEL                 sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL_FEL,SUNXI_EMAC                                                 -
+ Active  arm         armv7          sunxi       -               sunxi               A13-OLinuXino                        sun5i:A13_OLINUXINO,SPL,STATUSLED=201,CONS_INDEX=2                                                                                -
+@@ -415,7 +416,6 @@ Active  arm         armv7          sunxi       -               sunxi
+ Active  arm         armv7          sunxi       -               sunxi               uhost_u1a                            sun4i:UHOST_U1A,SPL,STATUSLED=34                                                                                                  -
+ Active  arm         armv7          sunxi       -               sunxi               wobo-i5                              sun5i:WOBO_I5,SPL,STATUSLED=34                                                                                                    -
+ Active  arm         armv7          sunxi       -               sunxi               xzpad700                             sun5i:XZPAD700,SPL                                                                                                                -
+-Active  arm         armv7          sunxi       -               sunxi               A10-OLinuXino-Lime			 sun4i:A10_OLINUXINO_L,SPL,SUNXI_EMAC                                                                                             -
+ Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
+ Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
+ Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
+-- 
+1.8.5.1
+