aboutsummaryrefslogtreecommitdiffstats
path: root/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch
diff options
context:
space:
mode:
authorZoltan Herpai <wigyori@uid0.hu>2016-01-08 20:37:43 +0000
committerZoltan Herpai <wigyori@uid0.hu>2016-01-08 20:37:43 +0000
commitf15fc140f1e93ea2fbe1769782968a248bb4f5df (patch)
treeb478a4a1d55f4bec4fbd8d0cf849ec2798435609 /package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch
parentf6340da7df61334b28d85c9fbc7775ec8305f61f (diff)
downloadupstream-f15fc140f1e93ea2fbe1769782968a248bb4f5df.tar.gz
upstream-f15fc140f1e93ea2fbe1769782968a248bb4f5df.tar.bz2
upstream-f15fc140f1e93ea2fbe1769782968a248bb4f5df.zip
packages: bump uboot-sunxi to 2016.01-rc3, along with H3 PSCI/SMP patches
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 48154
Diffstat (limited to 'package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch')
-rw-r--r--package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch22
1 files changed, 22 insertions, 0 deletions
diff --git a/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch b/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch
new file mode 100644
index 0000000000..78d784f94e
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch
@@ -0,0 +1,22 @@
+diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+index 4ff46e4..90b5bfd 100644
+--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
++++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+@@ -106,7 +106,7 @@ psci_fiq_enter:
+ str r10, [r8, #0x100]
+ timer_wait r10, ONE_MS
+
+-#ifdef CONFIG_MACH_SUN6I
++#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+ @ Activate power clamp
+ lsl r12, r9, #2 @ x4
+ add r12, r12, r8
+@@ -170,7 +170,7 @@ psci_cpu_on:
+ movw r0, #(SUNXI_PRCM_BASE & 0xffff)
+ movt r0, #(SUNXI_PRCM_BASE >> 16)
+
+-#ifdef CONFIG_MACH_SUN6I
++#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+ @ Release power clamp
+ lsl r5, r1, #2 @ 1 register per CPU
+ add r5, r5, r0 @ PRCM