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| author | Daniel Golle <daniel@makrotopia.org> | 2021-02-20 13:04:38 +0000 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2021-03-11 16:24:53 +0000 |
| commit | 9dfc2b3ca4dff28259576e21bc3ade910ff52a05 (patch) | |
| tree | bc7a3bbea0fa638ece89027d3f04fcd0d09a9359 /package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch | |
| parent | e2cffbb80528b1c13bbaba6e53835de378ef3923 (diff) | |
| download | upstream-9dfc2b3ca4dff28259576e21bc3ade910ff52a05.tar.gz upstream-9dfc2b3ca4dff28259576e21bc3ade910ff52a05.tar.bz2 upstream-9dfc2b3ca4dff28259576e21bc3ade910ff52a05.zip | |
uboot-mediatek: update to 2021.04-rc3 with MediaTek's patches
MediaTek published their current U-Boot patchset on github:
https://github.com/mtk-openwrt/u-boot/commits/mtksoc
Import the platform patches from there (`00-mtk-*.patch`), arrange,
them nicely, drop no longer needed local patches and rebase on top of
U-Boot 2021.04-rc3.
Tested and works well on Linksys E8450 (snand-1ddr) as well as
Bananapi BPi-R64 (sdmmc-2ddr, emmc-2ddr).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch')
| -rw-r--r-- | package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch b/package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch new file mode 100644 index 0000000000..658cbc1232 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch @@ -0,0 +1,38 @@ +From ed880b7572e1135e3bd8382d4670a375f7d9c91b Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 2 Mar 2021 15:56:17 +0800 +Subject: [PATCH 10/21] mmc: mtk-sd: increase the minimum bus frequency + +With a 48MHz input clock, the lowest bus frequency can be as low as +48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause +the mmc framework take seconds to finish the initialization. + +Limiting the minimum bus frequency to a slightly higher value can solve the +issue without any side effects. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mmc/mtk-sd.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/mmc/mtk-sd.c ++++ b/drivers/mmc/mtk-sd.c +@@ -232,6 +232,8 @@ + + #define SCLK_CYCLES_SHIFT 20 + ++#define MIN_BUS_CLK 260000 ++ + #define CMD_INTS_MASK \ + (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) + +@@ -1639,6 +1641,9 @@ static int msdc_drv_probe(struct udevice + else + cfg->f_min = host->src_clk_freq / (4 * 4095); + ++ if (cfg->f_min < MIN_BUS_CLK) ++ cfg->f_min = MIN_BUS_CLK; ++ + cfg->f_max = host->src_clk_freq; + + cfg->b_max = 1024; |