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authorGabor Juhos <juhosg@openwrt.org>2009-06-06 13:48:36 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-06-06 13:48:36 +0000
commit9668bbeea98d82bdf1b9c4e38d0127cc42009615 (patch)
tree51a8504d5fd15752ae30748857251f3e71d19f57
parentbb698428f0efac94c48dd1b79c825cb19315cf0c (diff)
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handle PCI_CORE interrupt as well
SVN-Revision: 16358
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/irq.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
index 0d5af43d7c..c3ba7ec437 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
@@ -1,7 +1,7 @@
/*
* Atheros AR71xx SoC specific interrupt handling
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
@@ -27,7 +27,7 @@ static void ar71xx_pci_irq_dispatch(void)
u32 pending;
pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
- ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
+ ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
if (pending & PCI_INT_DEV0)
do_IRQ(AR71XX_PCI_IRQ_DEV0);
@@ -38,6 +38,9 @@ static void ar71xx_pci_irq_dispatch(void)
else if (pending & PCI_INT_DEV2)
do_IRQ(AR71XX_PCI_IRQ_DEV2);
+ else if (pending & PCI_INT_CORE)
+ do_IRQ(AR71XX_PCI_IRQ_CORE);
+
else
spurious_interrupt();
}