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authorJohn Crispin <john@openwrt.org>2014-09-12 06:53:15 +0000
committerJohn Crispin <john@openwrt.org>2014-09-12 06:53:15 +0000
commit94efeaa51f4e4f00160559c53ca6f601f2864560 (patch)
tree0f4346991d800c0a7caa3281db6b9714993f16be
parent78c914ffe52e84b05c6d6ad33d9232fb980f1725 (diff)
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atheros: ar2315-pci: update host bridge resources
It seems that the PCI controller does not support I/O ports, so remove the ports range. Also correct the beginning of the memory range and its size. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 42503
-rw-r--r--target/linux/atheros/patches-3.14/100-board.patch3
-rw-r--r--target/linux/atheros/patches-3.14/105-ar2315_pci.patch25
2 files changed, 8 insertions, 20 deletions
diff --git a/target/linux/atheros/patches-3.14/100-board.patch b/target/linux/atheros/patches-3.14/100-board.patch
index c87734b69d..4512d55ed4 100644
--- a/target/linux/atheros/patches-3.14/100-board.patch
+++ b/target/linux/atheros/patches-3.14/100-board.patch
@@ -674,7 +674,7 @@
+#endif /* __ASM_MACH_AR231X_WAR_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
-@@ -0,0 +1,624 @@
+@@ -0,0 +1,625 @@
+/*
+ * Register definitions for AR2315+
+ *
@@ -738,6 +738,7 @@
+#define AR2315_UART0 0x11100000 /* UART MMR */
+#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
+#define AR2315_PCIEXT 0x80000000 /* pci external */
++#define AR2315_PCIEXT_SZ 0x40000000
+
+/* MII registers offset inside Ethernet MMR region */
+#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
diff --git a/target/linux/atheros/patches-3.14/105-ar2315_pci.patch b/target/linux/atheros/patches-3.14/105-ar2315_pci.patch
index 6623dabf32..1460299a75 100644
--- a/target/linux/atheros/patches-3.14/105-ar2315_pci.patch
+++ b/target/linux/atheros/patches-3.14/105-ar2315_pci.patch
@@ -7,7 +7,7 @@
+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
--- /dev/null
+++ b/arch/mips/ar231x/pci.c
-@@ -0,0 +1,350 @@
+@@ -0,0 +1,337 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
@@ -61,10 +61,6 @@
+#include <ar2315_regs.h>
+#include "devices.h"
+
-+#define AR2315_MEM_BASE 0x80800000UL
-+#define AR2315_MEM_SIZE 0x00ffffffUL
-+#define AR2315_IO_SIZE 0x00007fffUL
-+
+/* Arbitrary size of memory region to access the configuration space */
+#define AR2315_PCI_CFG_SIZE 0x00100000
+
@@ -160,16 +156,16 @@
+
+static struct resource ar2315_mem_resource = {
+ .name = "ar2315-pci-mem",
-+ .start = AR2315_MEM_BASE,
-+ .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
-+ 0x4000000,
++ .start = AR2315_PCIEXT,
++ .end = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
+ .flags = IORESOURCE_MEM,
+};
+
++/* PCI controller does not support I/O ports */
+static struct resource ar2315_io_resource = {
+ .name = "ar2315-pci-io",
-+ .start = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
-+ .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
++ .start = 0,
++ .end = 0,
+ .flags = IORESOURCE_IO,
+};
+
@@ -298,11 +294,6 @@
+ return -ENOMEM;
+ }
+
-+ ar2315_pci_controller.io_map_base =
-+ (unsigned long)ioremap_nocache(AR2315_MEM_BASE +
-+ AR2315_MEM_SIZE, AR2315_IO_SIZE);
-+ set_io_port_base(ar2315_pci_controller.io_map_base); /* PCI I/O space*/
-+
+ /* Reset PCI DMA logic */
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
+ msleep(20);
@@ -338,10 +329,6 @@
+
+ msleep(500);
+
-+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
-+ ioport_resource.start = 0x10000000;
-+ ioport_resource.end = 0xffffffff;
-+
+ res = ar2315_pci_host_setup();
+ if (res)
+ goto error;