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authorPetr Štetiar <ynezz@true.cz>2020-02-11 11:17:41 +0100
committerDaniel Golle <daniel@makrotopia.org>2020-05-26 10:07:05 +0100
commit498f1f4f5df2d077ba524f5735906bb52c12d580 (patch)
tree538df6bfdd2176622af1e654091c9b7393d4d7d5
parentd8d1956a8087da2fd4465c4381d9e28b91cdc1e8 (diff)
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ramips: gsw_mt7621: disable PORT 5 MAC RX/TX flow control by default
Looking at the current upstream driver implementation, it seems like the TX/RX flow control is enabled only if the flow control pause option is resolved from the device/link partner advertisements (or otherwise set). On the other hand, our current in-tree driver force enables TX/RX flow control by default, thus possibly leading to TX timeouts if the other end sends pause frames (which are not properly handled?): WARNING: CPU: 3 PID: 0 at net/sched/sch_generic.c:320 dev_watchdog+0x1ac/0x324 NETDEV WATCHDOG: eth0 (mtk_soc_eth): transmit queue 0 timed out Disabling the flow control on PORT 5 MAC seems to fix this issues as the pause frames are then filtered out. While at it, I'm removing the if condition completely as suggested, since this code is run only on mt7621 SoC, so there is no need to check for the silicon revisions. Ref: https://lists.openwrt.org/pipermail/openwrt-devel/2017-November/009882.html Ref: https://forum.openwrt.org/t/mtk-soc-eth-watchdog-timeout-after-r11573/50000/12 Suggested-by: Felix Fietkau <nbd@nbd.name> Reported-by: Rosen Penev <rosenp@gmail.com> Signed-off-by: Petr Štetiar <ynezz@true.cz> (cherry picked from commit c8f8e59816eca49d776562d2d302bf990a87faf0)
-rw-r--r--target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c
index 89be239007..232bcd8cf4 100644
--- a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c
+++ b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7621.c
@@ -98,15 +98,9 @@ static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
mt7530_mdio_w32(gsw, 0x7000, 0x3);
usleep_range(10, 20);
- if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
- /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
- mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
- mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
- } else {
- /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
- mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
- mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
- }
+ /* (GE1, Force 1000M/FD, FC OFF, MAX_RX_LENGTH 1536) */
+ mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
+ mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
/* (GE2, Link down) */
mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);