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| author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-04-02 23:45:20 +0200 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2021-07-19 14:51:22 +0200 |
| commit | 2ca8e424b93cbf359a8028acbbe9acabdb9365a9 (patch) | |
| tree | b4ae276f03794fce73004d879eba68a990127e81 | |
| parent | 939c0030dba2742e17e18b68999e23317796ace8 (diff) | |
| download | upstream-2ca8e424b93cbf359a8028acbbe9acabdb9365a9.tar.gz upstream-2ca8e424b93cbf359a8028acbbe9acabdb9365a9.tar.bz2 upstream-2ca8e424b93cbf359a8028acbbe9acabdb9365a9.zip | |
mvebu: convert mtd-mac-address to nvmem implementation
Define nvmem-cells and convert mtd-mac-address to nvmem implementation.
The conversion is done with an automated script.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
| -rw-r--r-- | target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 80b078cfaa..cdc91880ee 100644 --- a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -169,7 +169,8 @@ label = "lan0"; phy-handle = <&switch0phy1>; - mtd-mac-address = <&factory 0x6>; + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; }; port@3 { @@ -177,7 +178,8 @@ label = "lan1"; phy-handle = <&switch0phy2>; - mtd-mac-address = <&factory 0x6>; + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; }; }; @@ -199,7 +201,8 @@ }; ð0 { - mtd-mac-address = <&factory 0x0>; + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; phy-mode = "rgmii-id"; status = "okay"; @@ -208,3 +211,17 @@ full-duplex; }; }; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; |