aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJohn Crispin <john@phrozen.org>2019-08-06 06:19:33 +0200
committerJohn Crispin <john@phrozen.org>2019-08-06 06:20:14 +0200
commit19cfbb1b34de5a6f7234c8615edaf3a497ba4d55 (patch)
tree93d1c02d5e23a5d662cb11c132cb2b1b8afe4e93
parent79596f782e2c8daa1ebb8e480b6373c8142714c6 (diff)
downloadupstream-19cfbb1b34de5a6f7234c8615edaf3a497ba4d55.tar.gz
upstream-19cfbb1b34de5a6f7234c8615edaf3a497ba4d55.tar.bz2
upstream-19cfbb1b34de5a6f7234c8615edaf3a497ba4d55.zip
mediatek: update the mt7531 switch driver
Signed-off-by: John Crispin <john@phrozen.org>
Diffstat
-rw-r--r--target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch305
1 files changed, 94 insertions, 211 deletions
diff --git a/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch b/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch
index 6eba4017d7..7ade515a7f 100644
--- a/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch
+++ b/target/linux/mediatek/patches-4.19/0003-mt7531-gsw-internal_phy_calibration.patch
@@ -10,25 +10,22 @@
--- a/drivers/net/phy/mtk/mt753x/mt7531.c
+++ b/drivers/net/phy/mtk/mt753x/mt7531.c
-@@ -454,6 +454,21 @@ static void mt7531_core_pll_setup(struct gsw_mt753x *gsw)
+@@ -454,6 +454,18 @@ static void mt7531_core_pll_setup(struct gsw_mt753x *gsw)
static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)
{
-+ u32 i;
++ u32 i, val;
+ int ret;
-+
-+ dev_info(gsw->dev,">>>>>>>>>>>>>>>>>>>>>>>>>>>>> START CALIBRATION:\n");
++ val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
++ val |= GBE_EFUSE_SETTING;
++ gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
+ for (i = 0; i < 5; i++) {
-+ dev_info(gsw->dev, "-------- gephy-calbration (port:%d) --------\n",
-+ i);
+ ret = mt753x_phy_calibration(gsw, i);
-+
+ /* set Auto-negotiation with giga extension. */
+ gsw->mii_write(gsw, i, 0, 0x1340);
+ if (ret)
+ return ret;
+ }
-+
return 0;
}
@@ -45,7 +42,7 @@
#define MMD_CMD_S 14
--- /dev/null
+++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
-@@ -0,0 +1,1061 @@
+@@ -0,0 +1,947 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common part for MediaTek MT753x gigabit switch
@@ -66,9 +63,6 @@
+{
+ u32 phy_val;
+ phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
-+
-+ //printk("switch phy cl45 r %d 0x%x 0x%x = %x\n",port_num, dev_addr, reg_addr, phy_val);
-+ //switch_phy_read_cl45(port_num, dev_addr, reg_addr, &phy_val);
+ return phy_val;
+}
+
@@ -77,8 +71,6 @@
+ u32 phy_val;
+ gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data);
+ phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
-+ //printk("switch phy cl45 w %d 0x%x 0x%x 0x%x --> read back 0x%x\n",port_num, dev_addr, reg_addr, write_data, phy_val);
-+ //switch_phy_write_cl45(port_num, dev_addr, reg_addr, write_data);
+}
+
+void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){
@@ -117,10 +109,7 @@
+{
+ u8 all_ana_cal_status;
+ u32 cnt, tmp_1e_17c;
-+ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017c, 0x0001); // da_calin_flag pull high
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
-+ //printk("delay = %d\n", delay);
-+
+ cnt = 10000;
+ do {
+ udelay(delay);
@@ -134,45 +123,10 @@
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
+ return all_ana_cal_status;
+ } else {
-+ tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c);
-+ if ((tmp_1e_17c & 0x1) != 1) {
-+ pr_info("FIRST MDC/MDIO write error\n");
-+ pr_info("FIRST 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c));
-+
-+ }
-+ printk("re-K again\n");
-+
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
-+ cnt = 10000;
-+ do {
-+ udelay(delay);
-+ cnt--;
-+ tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c);
-+ if ((tmp_1e_17c & 0x1) != 1) {
-+ pr_info("SECOND MDC/MDIO write error\n");
-+ pr_info("SECOND 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c));
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
-+ }
-+ } while ((cnt != 0) && (tmp_1e_17c == 0));
-+
-+ cnt = 10000;
-+ do {
-+ udelay(delay);
-+ cnt--;
-+ all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
-+
-+ } while ((all_ana_cal_status == 0) && (cnt != 0));
-+
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
++ pr_info("MDC/MDIO error\n");
++ return 0;
+ }
+
-+ if(all_ana_cal_status == 0){
-+ pr_info("!!!!!!!!!!!! dev1Eh_reg17b ERROR\n");
-+ }
-+
+ return all_ana_cal_status;
+}
+
@@ -188,12 +142,6 @@
+ u8 cnt = 0;
+ u16 dev1e_17a_tmp, dev1e_e0_tmp;
+
-+ /* *** Iext/Rext Cal start ************ */
-+ all_ana_cal_status = ANACAL_INIT;
-+ /* analog calibration enable, Rext calibration enable */
-+ /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
-+ /* 1e_dc[0]:rg_txvos_calen */
-+ /* 1e_e1[4]:rg_cal_refsel(0:1.2V) */
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110)
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110);
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000);
@@ -201,18 +149,15 @@
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000);
+ //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
+
-+ rg_zcal_ctrl = 0x20;/* start with 0 dB */
-+ dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); // get default value
-+ /* 1e_e0[5:0]:rg_zcal_ctrl */
++ rg_zcal_ctrl = 0x20;
++ dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl);
+ all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */
-+
+ if (all_ana_cal_status == 0) {
+ all_ana_cal_status = ANACAL_ERROR;
+ printk(" GE Rext AnaCal ERROR init! \r\n");
+ return -1;
+ }
-+ /* 1e_17a[8]:ad_cal_comp_out */
+ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1;
+ if (ad_cal_comp_out_init == 1)
+ calibration_polarity = -1;
@@ -236,7 +181,7 @@
+ dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
+ dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
+ if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
-+ all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
++ all_ana_cal_status = ANACAL_SATURATION;
+ printk(" GE Rext AnaCal Saturation! \r\n");
+ rg_zcal_ctrl = 0x20; /* 0 dB */
+ }
@@ -244,13 +189,12 @@
+ }
+
+ if (all_ana_cal_status == ANACAL_ERROR) {
-+ rg_zcal_ctrl = 0x20; /* 0 dB */
++ rg_zcal_ctrl = 0x20;
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
+ } else if(all_ana_cal_status == ANACAL_FINISH){
+ //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl));
+ printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0));
-+ /* **** 1f_115[2:0] = rg_zcal_ctrl[5:3] // Mog review */
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3));
+ printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115));
+ printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
@@ -272,38 +216,38 @@
+ u16 dev1e_e0_ana_cal_r5;
+ int calibration_polarity;
+ u8 cnt = 0;
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // 1e_dc[0]:rg_txvos_calen
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100);
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
+
+ for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
-+ rg_zcal_ctrl = 0x20; // start with 0 dB
-+ dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00e0) & (~0x003f));
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); // 1e_e0[5:0]:rg_zcal_ctrl
++ rg_zcal_ctrl = 0x20;
++ dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0) & (~0x003f));
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
+ if(calibration_pair == ANACAL_PAIR_A)
+ {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
+ //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
+
+ }
+ else if(calibration_pair == ANACAL_PAIR_B)
+ {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000); // 1e_dc[12]:rg_zcalen_b
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000);
+ //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
+
+ }
+ else if(calibration_pair == ANACAL_PAIR_C)
+ {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100); // 1e_dc[8]:rg_zcalen_c
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100);
+ //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
+
+ }
+ else // if(calibration_pair == ANACAL_PAIR_D)
+ {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010); // 1e_dc[4]:rg_zcalen_d
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010);
+ //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
+
+ }
@@ -316,7 +260,7 @@
+ return -1;
+ }
+
-+ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
++ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1;
+ if(ad_cal_comp_out_init == 1)
+ calibration_polarity = -1;
+ else
@@ -350,11 +294,11 @@
+ }
+
+ if(all_ana_cal_status == ANACAL_ERROR) {
-+ rg_zcal_ctrl = 0x20; // 0 dB
++ rg_zcal_ctrl = 0x20;
+ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
+ }
+ else {
-+ rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9]; // wait Mog zcal/r50 mapping table
++ rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9];
+ printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80));
+ }
+
@@ -362,7 +306,7 @@
+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00);
+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
+ //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_174[15:8]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000)));
+ //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
+ }
+ else if(calibration_pair == ANACAL_PAIR_B) {
@@ -370,18 +314,18 @@
+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
+ //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
+
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_174[7:0]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080)));
+ //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
+ }
+ else if(calibration_pair == ANACAL_PAIR_C) {
+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00);
+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_175[15:8]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000)));
+ //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
+ } else {// if(calibration_pair == ANACAL_PAIR_D)
+ ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f);
+ //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_175[7:0]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080)));
+ //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
+ }
+ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl));
@@ -402,11 +346,10 @@
+ u8 tx_offset_reg_shift, tabl_idx, i;
+ u8 cnt = 0;
+ u16 tx_offset_reg, reg_temp, cal_temp;
-+ //switch_phy_write(phyaddr, R0, 0x2100);//harry tmp
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000); // 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100);
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808);
+ for(i = 0; i <= 4; i++)
+ tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
+ for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++)
@@ -416,45 +359,45 @@
+
+ if(calibration_pair == ANACAL_PAIR_A) {
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010);
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:rg_txg_calen_a
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V)); // 1e_17d:dac_in0_a
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V)); // 1e_181:dac_in1_a
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V));
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V));
+ //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00));
-+ tx_offset_reg_shift = 8; // 1e_172[13:8]
++ tx_offset_reg_shift = 8;
+ tx_offset_reg = 0x0172;
+
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
+ } else if(calibration_pair == ANACAL_PAIR_B) {
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5018);
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:rg_txg_calen_b
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V)); // 1e_17e:dac_in0_b
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V)); // 1e_182:dac_in1_b
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V));
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V));
+ //printk("tx offset pairB 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x003f));
-+ tx_offset_reg_shift = 0; // 1e_172[5:0]
++ tx_offset_reg_shift = 0;
+ tx_offset_reg = 0x0172;
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
+ } else if(calibration_pair == ANACAL_PAIR_C) {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:rg_txg_calen_c
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V)); // 1e_17f:dac_in0_c
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V)); // 1e_183:dac_in1_c
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V));
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V));
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x3f00));
+ //printk("tx offset pairC 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
-+ tx_offset_reg_shift = 8; // 1e_173[13:8]
++ tx_offset_reg_shift = 8;
+ tx_offset_reg = 0x0173;
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
+ } else {// if(calibration_pair == ANACAL_PAIR_D)
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:rg_txg_calen_d
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V)); // 1e_180:dac_in0_d
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V)); // 1e_184:dac_in1_d
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V));
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V));
+ //printk("tx offset pairD 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x003f));
-+ tx_offset_reg_shift = 0; // 1e_173[5:0]
++ tx_offset_reg_shift = 0;
+ tx_offset_reg = 0x0173;
+ //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
+ }
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); // 1e_172, 1e_173
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
+ all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
+ if(all_ana_cal_status == 0) {
+ all_ana_cal_status = ANACAL_ERROR;
@@ -462,7 +405,7 @@
+ return -1;
+ }
+
-+ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
++ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1;
+ if(ad_cal_comp_out_init == 1)
+ calibration_polarity = 1;
+ else
@@ -489,7 +432,7 @@
+ all_ana_cal_status = ANACAL_FINISH;
+ } else {
+ if((tabl_idx == 0)||(tabl_idx == 0x3f)) {
-+ all_ana_cal_status = ANACAL_SATURATION; // need to FT
++ all_ana_cal_status = ANACAL_SATURATION;
+ printk( " GE Tx offset AnaCal Saturation! \r\n");
+ }
+ }
@@ -512,12 +455,12 @@
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
+
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000);
+}
+
+int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
@@ -528,11 +471,11 @@
+ u32 tx_amp_reg_shift;
+ u16 reg_temp;
+ u32 tx_amp_temp, tx_amp_reg, cnt=0, tx_amp_reg_100;
-+ u32 debug_tmp, reg_backup, reg_tmp;
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010); // 1e_e1[4]:select 1V
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e:enable Tx VLD
++ u32 reg_backup, reg_tmp;
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100);
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001);
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808);
+
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, 0xff00);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27a, 0x33);
@@ -541,36 +484,36 @@
+ for(i = 0; i <= 4; i++)
+ tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
+ for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
-+ tx_amp_temp = 0x20; // start with 0 dB
++ tx_amp_temp = 0x20;
+
+ if(calibration_pair == ANACAL_PAIR_A) {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:tx_a amp calibration enable
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d:dac_in0_a
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181:dac_in1_a
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x012) & (~0xfc00));
+ tx_amp_reg_shift = 10; // 1e_12[15:10]
+ tx_amp_reg = 0x12;
+ tx_amp_reg_100 = 0x16;
+ } else if(calibration_pair == ANACAL_PAIR_B) {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:tx_b amp calibration enable
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e:dac_in0_b
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182:dac_in1_b
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x017) & (~0x3f00));
+ tx_amp_reg_shift = 8; // 1e_17[13:8]
+ tx_amp_reg = 0x17;
+ tx_amp_reg_100 = 0x18;
+ } else if(calibration_pair == ANACAL_PAIR_C) {
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:tx_c amp calibration enable
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f:dac_in0_c
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183:dac_in1_c
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x019) & (~0x3f00));
+ tx_amp_reg_shift = 8; // 1e_19[13:8]
+ tx_amp_reg = 0x19;
+ tx_amp_reg_100 = 0x20;
+ } else { //if(calibration_pair == ANACAL_PAIR_D)
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:tx_d amp calibration enable
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180:dac_in0_d
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184:dac_in1_d
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184
+ reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x021) & (~0x3f00));
+ tx_amp_reg_shift = 8; // 1e_21[13:8]
+ tx_amp_reg = 0x21;
@@ -585,7 +528,7 @@
+ return -1;
+ }
+
-+ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out
++ ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]
+ if(ad_cal_comp_out_init == 1)
+ calibration_polarity = -1;
+ else
@@ -739,11 +682,10 @@
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
+ reg_tmp = ((reg_backup & 0xfc00) >> 10);
+ reg_tmp -= 8;
-+ reg_backup = (reg_backup & (~0xfc00));
-+ reg_backup |= (reg_tmp << 10);
++ reg_backup = 0x0000;
++ reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
-+ //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+ reg_tmp -= 8;
@@ -751,17 +693,15 @@
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
-+ //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_B){
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
+ reg_tmp = ((reg_backup & 0x3f00) >> 8);
+ reg_tmp -= 8;
-+ reg_backup = (reg_backup & (~0x3f00));
-+ reg_backup |= (reg_tmp << 8);
++ reg_backup = 0x0000;
++ reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
-+ //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+ reg_tmp -= 8;
@@ -769,7 +709,6 @@
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
-+ //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_C){
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
@@ -779,7 +718,6 @@
+ reg_backup |= (reg_tmp << 8);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
-+ //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+ reg_tmp -= 8;
@@ -787,7 +725,6 @@
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
-+ //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_D){
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
@@ -797,7 +734,6 @@
+ reg_backup |= (reg_tmp << 8);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
-+ //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+ reg_tmp -= 8;
@@ -805,45 +741,12 @@
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
-+ //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
-+ }
-+
-+ if (calibration_pair == ANACAL_PAIR_A){
-+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
-+ //printk("1e.012 = 0x%x\n", debug_tmp);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
-+ //printk("1e.016 = 0x%x\n", debug_tmp);
-+ }
-+
-+ else if(calibration_pair == ANACAL_PAIR_B){
-+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
-+ //printk("1e.017 = 0x%x\n", debug_tmp);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
-+ //printk("1e.018 = 0x%x\n", debug_tmp);
-+ }
-+ else if(calibration_pair == ANACAL_PAIR_C){
-+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
-+ //printk("1e.019 = 0x%x\n", debug_tmp);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
-+ //printk("1e.020 = 0x%x\n", debug_tmp);
+ }
-+ else if(calibration_pair == ANACAL_PAIR_D){
-+ //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
-+ //printk("1e.021 = 0x%x\n", debug_tmp);
-+ debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
-+ //printk("1e.022 = 0x%x\n", debug_tmp);
-+ }
-+
-+
+ printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
+
+ } else {
+ if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) {
-+ all_ana_cal_status = ANACAL_SATURATION; // need to FT
++ all_ana_cal_status = ANACAL_SATURATION;
+ printk( " GE Tx amp AnaCal Saturation! \r\n");
+ }
+ }
@@ -865,11 +768,11 @@
+
+ /* disable analog calibration circuit */
+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
-+ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit
++ tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000);
+
+
+
@@ -886,28 +789,18 @@
+ u32 reg_tmp,reg_tmp0, reg_tmp1, i;
+ u32 CALDLY = 40;
+ int ret;
-+ /* set [12]AN disable, [8]full duplex, [13/6]1000Mbps */
-+ //tc_phy_write_dev_reg(phyaddr, 0x0, 0x0140);
+ switch_phy_write(gsw, phyaddr, R0, 0x140);
+
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);/* fix mdi */
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);/* disable tx slew control */
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);/* BG voltage output */
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099); //bypass efuse
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);
++ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);
++ //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099);
+
+#if (1)
-+ // 1f_27c[12:8] cr_da_tx_i2mpb_10m Trimming TX bias setup(@10M)
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1f1f);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x3300);
+
+ reg_tmp1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x27c);
-+ //dev1Fh_reg273h TXVLD DA register - Adjust voltage mode TX amplitude.
-+ //tc_phy_write_dev_reg(phyaddr, 0x1f, 0x273, 0);
-+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x1000);
-+ //reg_tmp1 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x273);
-+ //printk("reg_tmp1273 = %x\n", reg_tmp1);
-+ /*1e_11 TX overshoot Enable (PAIR A/B/C/D) in gbe mode*/
-+
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11);
+ reg_tmp = reg_tmp | (0xf << 12);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, reg_tmp);
@@ -964,13 +857,11 @@
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18e, 0x0001);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18f, 0x0001);
+
-+ /*da_tx_bias1_b_tx_standby = 5'b10 (dev1eh_reg3aah[12:8])*/
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3aa);
+ reg_tmp = reg_tmp & ~(0x1f00);
+ reg_tmp = reg_tmp | 0x2 << 8;
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, reg_tmp);
+
-+ /*da_tx_bias1_a_tx_standby = 5'b10 (dev1eh_reg3a9h[4:0])*/
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3a9);
+ reg_tmp = reg_tmp & ~(0x1f);
+ reg_tmp = reg_tmp | 0x2;
@@ -982,7 +873,7 @@
+{
+ u32 reg_tmp1;
+
-+ pr_info("PORT %d RX_DC_OFFSET\n", phyaddr);
++ //pr_info("PORT %d RX_DC_OFFSET\n", phyaddr);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x96, 0x8000);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x37, 0x3);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x107, 0x4000);
@@ -1002,13 +893,11 @@
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x114f);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("before pairA output = %x\n", reg_tmp);
+ udelay(40);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1142);
+ udelay(40);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("after pairA output = %x\n", reg_tmp);
+ if ((reg_tmp & 0x80) != 0)
+ reg_tmp = (~reg_tmp) + 1;
+ if ((reg_tmp & 0xff) >4)
@@ -1023,13 +912,11 @@
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("before pairB output = %x\n", reg_tmp);
+ udelay(40);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143);
+ udelay(40);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("after pairB output = %x\n", reg_tmp);
+ if ((reg_tmp & 0x80) != 0)
+ reg_tmp = (~reg_tmp) + 1;
+ if ((reg_tmp & 0xff) >4)
@@ -1044,13 +931,11 @@
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("before pairC output = %x\n", reg_tmp);
+ udelay(40);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144);
+ udelay(40);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("after pairC output = %x\n", reg_tmp);
+ if ((reg_tmp & 0x80) != 0)
+ reg_tmp = (~reg_tmp) + 1;
+ if ((reg_tmp & 0xff) >4)
@@ -1065,13 +950,11 @@
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("before pairD output = %x\n", reg_tmp);
+ udelay(40);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145);
+ udelay(40);
+ reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
+ reg_tmp = reg_tmp & 0xff;
-+ pr_info("after pairD output = %x\n", reg_tmp);
+ if ((reg_tmp & 0x80) != 0)
+ reg_tmp = (~reg_tmp) + 1;
+ if ((reg_tmp & 0xff) >4)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 05:53:14 +0000