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| author | Rui Salvaterra <rsalvaterra@gmail.com> | 2021-03-30 23:59:50 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2021-03-31 00:58:49 +0100 |
| commit | 070ead4d4aaf30f5c6017054b822c3c6d649b071 (patch) | |
| tree | bce58e2d900e40e11d86a8e6a333d35e064193bf | |
| parent | 9c3b2d7ff755216a93d0ffa7d0375007cb7d3294 (diff) | |
| download | upstream-070ead4d4aaf30f5c6017054b822c3c6d649b071.tar.gz upstream-070ead4d4aaf30f5c6017054b822c3c6d649b071.tar.bz2 upstream-070ead4d4aaf30f5c6017054b822c3c6d649b071.zip | |
ramips/mt7621: enable support for cpuidle
MIPS Coherent Processor Systems (CPS), which include the MT7621 SoC, support
deep sleep idle states and have a specific cpuidle driver for them.
Enable support for it, while also switching from constant timer ticks to the
idle dynticks model, with the TEO governor.
Run-tested on a Redmi AC2100.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
| -rw-r--r-- | target/linux/ramips/mt7621/config-5.10 | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target/linux/ramips/mt7621/config-5.10 b/target/linux/ramips/mt7621/config-5.10 index 430ea9513c..adbd0c8c6c 100644 --- a/target/linux/ramips/mt7621/config-5.10 +++ b/target/linux/ramips/mt7621/config-5.10 @@ -2,6 +2,7 @@ CONFIG_ARCH_32BIT_OFF_T=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_AT803X_PHY=y CONFIG_BLK_MQ_PCI=y @@ -23,6 +24,9 @@ CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y @@ -30,6 +34,7 @@ CONFIG_CPU_MIPSR2=y CONFIG_CPU_MIPSR2_IRQ_EI=y CONFIG_CPU_MIPSR2_IRQ_VI=y CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_PM=y CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_CPU_RMAP=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y @@ -97,7 +102,6 @@ CONFIG_HAS_IOPORT_MAP=y CONFIG_HIGHMEM=y CONFIG_HZ=250 CONFIG_HZ_250=y -CONFIG_HZ_PERIODIC=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_MT7621=y @@ -134,7 +138,9 @@ CONFIG_MIPS_CM=y CONFIG_MIPS_CMDLINE_FROM_DTB=y CONFIG_MIPS_CPC=y CONFIG_MIPS_CPS=y +CONFIG_MIPS_CPS_CPUIDLE=y # CONFIG_MIPS_CPS_NS16550_BOOL is not set +CONFIG_MIPS_CPS_PM=y CONFIG_MIPS_CPU_SCACHE=y # CONFIG_MIPS_ELF_APPENDED_DTB is not set CONFIG_MIPS_GIC=y @@ -182,6 +188,8 @@ CONFIG_NET_MEDIATEK_SOC=y CONFIG_NET_SWITCHDEV=y CONFIG_NET_VENDOR_MEDIATEK=y # CONFIG_NET_VENDOR_RALINK is not set +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y CONFIG_NR_CPUS=4 CONFIG_OF=y CONFIG_OF_ADDRESS=y |