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/*
* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "plxtech,nas7820", "plxtech,nas782x";
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
/* alias to determine bank index */
gpio0 = &GPIOA;
gpio1 = &GPIOB;
ethernet0 = &gmac;
};
cpus {
cpu@0 {
compatible = "arm,arm11mpcore";
};
cpu@1 {
compatible = "arm,arm11mpcore";
};
};
gic: gic@47001000 {
compatible = "arm,arm11mp-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x47001000 0x1000>,
<0x47000100 0x0100>;
};
rst: reset-controller@44E00034 {
compatible = "plxtech,nas782x-reset";
#reset-cells = <1>;
reg = <0x44E00034 0x8>; /* currently not used */
};
rps: rps@44400000 {
compatible = "plxtech,nas782x-rps";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x44400000 0x14>;
interrupts = <0 5 0x304>;
};
/* external oscillator */
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
sysclk: sysclk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clocks = <&osc>;
};
plla: plla@44e001f0 {
compatible = "plxtech,nas782x-plla";
#clock-cells = <0>;
clocks = <&osc>;
reg = <0x44e001f0 0x10>;
};
pllb: pllb@44f001f0 {
compatible = "plxtech,nas782x-pllb";
#clock-cells = <0>;
clocks = <&osc>;
reg = <0x44f001f0 0x10>;
resets = <&rst 31>;
};
stdclk: stdclk {
compatible = "plxtech,nas782x-stdclk";
#clock-cells = <1>;
clocks = <&osc>;
};
twdclk: twdclk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clocks = <&plla>;
};
gmacclk: gmacclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
pinctrl {
/* act as a simple bus, so children will be probed automatically */
#address-cells = <1>;
#size-cells = <1>;
compatible = "plxtech,nas782x-pinctrl", "simple-bus";
ranges;
plxtech,mux-mask = <
0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0
0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3
>;
GPIOA: gpio@44000000 {
compatible = "plxtech,nas782x-gpio";
reg = <0x44000000 0x100>, <0x44E00000 0x200>;
interrupts = <0 21 0x304>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-lines = <32>; /* real gpio pin count */
};
GPIOB: gpio@44100000 {
compatible = "plxtech,nas782x-gpio";
reg = <0x44100000 0x100>, <0x44F00000 0x200>;
interrupts = <0 22 0x304>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-lines = <18>; /* real gpio pin count */
};
uart0 {
pinctrl_uart0: uart0-0 {
plxtech,pins =
<0 30 5 0 /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */
0 31 5 0>; /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */
};
};
gmac0 {
pinctrl_gmac0: gmac0-0 {
plxtech,pins =
<0 3 1 0 /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */
0 4 1 0>; /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */
};
};
nand0 {
pinctrl_nand0: nand0-0 {
plxtech,pins =
<0 12 1 0 /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */
0 13 1 0 /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */
0 14 1 0 /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */
0 15 1 0 /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */
0 16 1 0 /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */
0 17 1 0 /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */
0 18 1 0 /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */
0 19 1 0 /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */
0 20 1 0 /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */
0 21 1 0 /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */
0 22 1 0 /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */
0 23 1 0 /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */
0 24 1 0>; /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */
};
};
};
pcie-controller@47C00000 {
compatible = "plxtech,nas782x-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
/* flag & space bus address host address size */
ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
bus-range = <0x00 0x7f>;
/* cfg inbound translator phy*/
reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>;
#interrupt-cells = <1>;
/* wild card mask, match all bus address & interrupt specifier */
/* format: bus address mask, interrupt specifier mask */
/* each bit 1 means need match, 0 means ignored when match */
interrupt-map-mask = <0 0 0 0>;
/* format: a list of: bus address, interrupt specifier,
* parent interrupt controller & specifier */
interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
gpios = <&GPIOB 12 0>;
clocks = <&stdclk 8>, <&pllb>;
clock-names = "pcie", "busclk";
resets = <&rst 7>, <&rst 14>;
reset-names = "pcie", "phy";
plxtech,pcie-hcsl-bit = <2>;
plxtech,pcie-ctrl-offset = <0x120>;
plxtech,pcie-outbound-offset = <0x138>;
status = "disabled";
};
pcie-controller@47E00000 {
compatible = "plxtech,nas782x-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
/* flag & space bus address host address size */
ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
bus-range = <0x80 0xff>;
/* cfg inbound translator phy*/
reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>;
#interrupt-cells = <1>;
/* wild card mask, match all bus address & interrupt specifier */
/* format: bus address mask, interrupt specifier mask */
/* each bit 1 means need match, 0 means ignored when match */
interrupt-map-mask = <0 0 0 0>;
/* format: a list of: bus address, interrupt specifier,
* parent interrupt controller & specifier */
interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
/* gpios = <&GPIOB 12 0>; */
clocks = <&stdclk 11>, <&pllb>;
clock-names = "pcie", "busclk";
resets = <&rst 23>, <&rst 14>;
reset-names = "pcie", "phy";
plxtech,pcie-hcsl-bit = <3>;
plxtech,pcie-ctrl-offset = <0x124>;
plxtech,pcie-outbound-offset = <0x174>;
status = "disabled";
};
local-timer@47000600 {
compatible = "arm,arm11mp-twd-timer";
reg = <0x47000600 0x20>;
interrupts = <1 13 0x304>; /* percpu, irq 29, cpu mask 3, level high */
clocks = <&twdclk>;
};
watchdog@47000620 {
compatible = "mpcore_wdt";
reg = <0x47000620 0x20>;
interrupts = <1 14 0x304>; /* percpu, irq 30, cpu mask 3, level high */
clocks = <&twdclk>;
};
timer@44400200 {
compatible = "plxtech,nas782x-rps-timer";
reg = <0x44400200 0x40>;
clocks = <&sysclk>;
};
uart0: uart@44200000 {
compatible = "ns16550a";
reg = <0x44200000 0x100>;
clock-frequency = <6250000>;
interrupts = <0 23 0x304>;
reg-shift = <0>;
fifo-size = <16>;
reg-io-width = <1>;
current-speed = <115200>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
sata@45900000 {
compatible = "plxtech,nas782x-sata";
/* ports dmactl sgdma */
reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
/* core phy descriptors (optional) */
<0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
interrupts = <0 18 0x304>;
clocks = <&stdclk 4>;
resets = <&rst 11>, <&rst 12>, <&rst 13>;
reset-names = "sata", "link", "phy";
nr-ports = <1>;
status = "disabled";
};
nand@41000000 {
compatible = "plxtech,nand-nas782x", "gen_nand";
reg = <0x41000000 0x100000>, <0x41C00000 0x20>;
nand-ecc-mode = "soft";
clocks = <&stdclk 9>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand0>;
resets = <&rst 15>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
gmac: ethernet@40400000 {
compatible = "plxtech,nas782x-gmac", "snps,dwmac";
reg = <0x40400000 0x2000>;
interrupts = <0 8 0x304>, <0 17 0x304>;
interrupt-names = "macirq", "eth_wake_irq";
mac-address = [000000000000]; /* Filled in by U-Boot */
phy-mode = "rgmii";
clocks = <&stdclk 7>, <&gmacclk>;
clock-names = "gmac", "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0>;
resets = <&rst 6>;
status = "disabled";
};
ehci@40200100 {
compatible = "plxtech,nas782x-ehci";
reg = <0x40200100 0xf00>;
interrupts = <0 7 0x304>;
clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>;
clock-names = "usb", "refsrc", "phyref";
resets = <&rst 4>, <&rst 5>, <&rst 26>;
reset-names = "host", "phya", "phyb";
/* Otherwise ref300 is used, which is derived from sata phy
* in that case, usb depends on sata initialization */
/* FIXME: how to make this dependency explicit ? */
plxtech,ehci_use_pllb;
status = "disabled";
};
};
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