diff options
Diffstat (limited to 'package/boot/uboot-oxnas/files')
28 files changed, 4026 insertions, 0 deletions
diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile new file mode 100644 index 0000000..4c32f5c --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += timer.o +obj-y += clock.o +obj-y += pinmux.o diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c new file mode 100644 index 0000000..8974ca0 --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c @@ -0,0 +1,97 @@ +#include <common.h> +#include <asm/arch/sysctl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> + +typedef struct { + unsigned short mhz; + unsigned char refdiv; + unsigned char outdiv; + unsigned int fbdiv; + unsigned short bwadj; + unsigned short sfreq; + unsigned int sslope; +} PLL_CONFIG; + +const PLL_CONFIG C_PLL_CONFIG[] = { + { 500, 1, 2, 3932160, 119, 208, 189 }, // 500 MHz + { 525, 2, 1, 4128768, 125, 139, 297 }, // 525 MHz + { 550, 2, 1, 4325376, 131, 139, 311 }, // 550 MHz + { 575, 2, 1, 4521984, 137, 139, 326 }, // 575 MHz + { 600, 2, 1, 4718592, 143, 138, 339 }, // 600 MHz + { 625, 1, 1, 3276800, 99, 208, 157 }, // 625 MHz + { 650, 1, 1, 3407872, 103, 208, 164 }, // 650 MHz + { 675, 1, 1, 3538944, 107, 208, 170 }, // 675 MHz + { 700, 0, 0, 917504, 27, 416, 22 }, // 700 MHz + { 725, 1, 1, 3801088, 115, 208, 182 }, // 725 MHz + { 750, 0, 0, 983040, 29, 416, 23 }, // 750 MHz + { 775, 3, 0, 4063232, 123, 104, 390 }, // 775 MHz + { 800, 3, 0, 4194304, 127, 104, 403 }, // 800 MHz + { 825, 3, 0, 4325376, 131, 104, 415 }, // 825 MHz + { 850, 2, 0, 3342336, 101, 139, 241 }, // 850 MHz + { 875, 2, 0, 3440640, 104, 139, 248 }, // 875 MHz + { 900, 2, 0, 3538944, 107, 139, 255 }, // 900 MHz + { 925, 2, 0, 3637248, 110, 139, 262 }, // 925 MHz + { 950, 2, 0, 3735552, 113, 139, 269 }, // 950 MHz + { 975, 2, 0, 3833856, 116, 139, 276 }, // 975 MHz + { 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz +}; + +#define PLL_BYPASS (1<<1) +#define SAT_ENABLE (1<<3) + +#define PLL_OUTDIV_SHIFT 4 +#define PLL_REFDIV_SHIFT 8 +#define PLL_BWADJ_SHIFT 16 + +#define PLL_LOW_FREQ 500 +#define PLL_FREQ_STEP 25 +static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj, + int sfreq, int sslope) +{ + setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); + udelay(10); + reset_block(SYS_CTRL_RST_PLLA, 1); + udelay(10); + + writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) | + SAT_ENABLE | PLL_BYPASS, + SYS_CTRL_PLLA_CTRL0); + + writel(fbdiv, SYS_CTRL_PLLA_CTRL1); + writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2); + writel(sslope, SYS_CTRL_PLLA_CTRL3); + + udelay(10); // 5us delay required (from TCI datasheet), use 10us + + reset_block(SYS_CTRL_RST_PLLA, 0); + + udelay(100); // Delay for PLL to lock + + printf(" plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0)); + printf(" plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1)); + printf(" plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2)); + printf(" plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3)); + + clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass + puts("\nPLLA Set\n"); +} + +int plla_set_config(int mhz) +{ + int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP; + const PLL_CONFIG *cfg; + + if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) { + debug("Freq %d MHz out of range, default to lowest\n", mhz); + index = 0; + } + cfg = &C_PLL_CONFIG[index]; + + printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz); + plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj, + cfg->sfreq, cfg->sslope); + + return cfg->mhz; +} + diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c new file mode 100644 index 0000000..a6f5e9a --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c @@ -0,0 +1,43 @@ +#include <common.h> +#include <asm/arch/pinmux.h> + +void pinmux_set(int bank, int pin, int func) +{ + u32 reg; + u32 base; + /* TODO: check parameters */ + + if (bank == PINMUX_BANK_MFA) + base = SYS_CONTROL_BASE; + else + base = SEC_CONTROL_BASE; + + clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin)); + clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin)); + clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin)); + clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin)); + clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin)); + + switch (func) { + case PINMUX_GPIO: + default: + return; + break; + case PINMUX_2: + reg = base + PINMUX_SECONDARY_SEL; + break; + case PINMUX_3: + reg = base + PINMUX_TERTIARY_SEL; + break; + case PINMUX_4: + reg = base + PINMUX_QUATERNARY_SEL; + break; + case PINMUX_DEBUG: + reg = base + PINMUX_DEBUG_SEL; + break; + case PINMUX_ALT: + reg = base + PINMUX_ALTERNATIVE_SEL; + break; + } + setbits_le32(reg, BIT(pin)); +} diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c new file mode 100644 index 0000000..276c912 --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c @@ -0,0 +1,91 @@ +#include <common.h> +#include <asm/arch/sysctl.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> + +void reset_cpu(ulong addr) +{ + u32 value; + + // Assert reset to cores as per power on defaults + // Don't touch the DDR interface as things will come to an impromptu stop + // NB Possibly should be asserting reset for PLLB, but there are timing + // concerns here according to the docs + + value = + BIT(SYS_CTRL_RST_COPRO ) | + BIT(SYS_CTRL_RST_USBHS ) | + BIT(SYS_CTRL_RST_USBHSPHYA ) | + BIT(SYS_CTRL_RST_MACA ) | + BIT(SYS_CTRL_RST_PCIEA ) | + BIT(SYS_CTRL_RST_SGDMA ) | + BIT(SYS_CTRL_RST_CIPHER ) | + BIT(SYS_CTRL_RST_SATA ) | + BIT(SYS_CTRL_RST_SATA_LINK ) | + BIT(SYS_CTRL_RST_SATA_PHY ) | + BIT(SYS_CTRL_RST_PCIEPHY ) | + BIT(SYS_CTRL_RST_STATIC ) | + BIT(SYS_CTRL_RST_UART1 ) | + BIT(SYS_CTRL_RST_UART2 ) | + BIT(SYS_CTRL_RST_MISC ) | + BIT(SYS_CTRL_RST_I2S ) | + BIT(SYS_CTRL_RST_SD ) | + BIT(SYS_CTRL_RST_MACB ) | + BIT(SYS_CTRL_RST_PCIEB ) | + BIT(SYS_CTRL_RST_VIDEO ) | + BIT(SYS_CTRL_RST_USBHSPHYB ) | + BIT(SYS_CTRL_RST_USBDEV ); + + writel(value, SYS_CTRL_RST_SET_CTRL); + + // Release reset to cores as per power on defaults + writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL); + + // Disable clocks to cores as per power-on defaults - must leave DDR + // related clocks enabled otherwise we'll stop rather abruptly. + value = + BIT(SYS_CTRL_CLK_COPRO) | + BIT(SYS_CTRL_CLK_DMA) | + BIT(SYS_CTRL_CLK_CIPHER) | + BIT(SYS_CTRL_CLK_SD) | + BIT(SYS_CTRL_CLK_SATA) | + BIT(SYS_CTRL_CLK_I2S) | + BIT(SYS_CTRL_CLK_USBHS) | + BIT(SYS_CTRL_CLK_MAC) | + BIT(SYS_CTRL_CLK_PCIEA) | + BIT(SYS_CTRL_CLK_STATIC) | + BIT(SYS_CTRL_CLK_MACB) | + BIT(SYS_CTRL_CLK_PCIEB) | + BIT(SYS_CTRL_CLK_REF600) | + BIT(SYS_CTRL_CLK_USBDEV); + + writel(value, SYS_CTRL_CLK_CLR_CTRL); + + // Enable clocks to cores as per power-on defaults + + // Set sys-control pin mux'ing as per power-on defaults + + writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL); + writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL); + writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL); + writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL); + writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL); + writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL); + + writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL); + writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL); + writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL); + writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL); + writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL); + writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL); + + // No need to save any state, as the ROM loader can determine whether reset + // is due to power cycling or programatic action, just hit the (self- + // clearing) CPU reset bit of the block reset register + value = + BIT(SYS_CTRL_RST_SCU) | + BIT(SYS_CTRL_RST_ARM0) | + BIT(SYS_CTRL_RST_ARM1); + + writel(value, SYS_CTRL_RST_SET_CTRL); +} diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c new file mode 100644 index 0000000..5e87608 --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * Richard Woodruff <r-woodruff2@ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4))) +#define TIMER_LOAD_VAL 0xFFFFFF + +/* macro to read the 32 bit timer */ +#define READ_TIMER (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \ + / (TIMER_CLOCK / CONFIG_SYS_HZ) + +#define READ_TIMER_HW (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) + +DECLARE_GLOBAL_DATA_PTR; + +int timer_init (void) +{ + int32_t val; + + /* Start the counter ticking up */ + writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD); /* reload value on overflow*/ + + val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) | + (TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) | + (TIMER_ENABLE << TIMER_ENABLE_SHIFT); /* mask to enable timer*/ + writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL); /* start timer */ + + /* reset time */ + gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */ + gd->arch.tbl = 0; /* start "advancing" time stamp */ + + return(0); +} +/* + * timer without interrupts + */ +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +/* delay x useconds AND preserve advance timestamp value */ +void __udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec > 100000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + + tmp = get_timer (0); /* get current timestamp */ + while (get_timer (tmp) < tmo)/* loop till event */ + /*NOP*/; + } else { /* else small number, convert to hw ticks */ + tmo = usec * (TIMER_CLOCK / 1000) / 1000; + /* timeout is no more than 0.1s, and the hw timer will roll over at most once */ + tmp = READ_TIMER_HW; + while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */ + /*NOP*/; + } +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ + /* move stamp fordward with absoulte diff ticks */ + gd->arch.tbl += (now - gd->arch.lastinc); + } else { + /* we have rollover of incrementer */ + gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ)) + - gd->arch.lastinc) + now; + } + gd->arch.lastinc = now; + return gd->arch.tbl; +} + + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h new file mode 100644 index 0000000..da7dd1c --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h @@ -0,0 +1,84 @@ +#ifndef _NAS782X_CLOCK_H +#define _NAS782X_CLOCK_H + +#include <asm/arch/sysctl.h> +#include <asm/arch/cpu.h> + +/* bit numbers of clock control register */ +#define SYS_CTRL_CLK_COPRO 0 +#define SYS_CTRL_CLK_DMA 1 +#define SYS_CTRL_CLK_CIPHER 2 +#define SYS_CTRL_CLK_SD 3 +#define SYS_CTRL_CLK_SATA 4 +#define SYS_CTRL_CLK_I2S 5 +#define SYS_CTRL_CLK_USBHS 6 +#define SYS_CTRL_CLK_MACA 7 +#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA +#define SYS_CTRL_CLK_PCIEA 8 +#define SYS_CTRL_CLK_STATIC 9 +#define SYS_CTRL_CLK_MACB 10 +#define SYS_CTRL_CLK_PCIEB 11 +#define SYS_CTRL_CLK_REF600 12 +#define SYS_CTRL_CLK_USBDEV 13 +#define SYS_CTRL_CLK_DDR 14 +#define SYS_CTRL_CLK_DDRPHY 15 +#define SYS_CTRL_CLK_DDRCK 16 + +/* bit numbers of reset control register */ +#define SYS_CTRL_RST_SCU 0 +#define SYS_CTRL_RST_COPRO 1 +#define SYS_CTRL_RST_ARM0 2 +#define SYS_CTRL_RST_ARM1 3 +#define SYS_CTRL_RST_USBHS 4 +#define SYS_CTRL_RST_USBHSPHYA 5 +#define SYS_CTRL_RST_MACA 6 +#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA +#define SYS_CTRL_RST_PCIEA 7 +#define SYS_CTRL_RST_SGDMA 8 +#define SYS_CTRL_RST_CIPHER 9 +#define SYS_CTRL_RST_DDR 10 +#define SYS_CTRL_RST_SATA 11 +#define SYS_CTRL_RST_SATA_LINK 12 +#define SYS_CTRL_RST_SATA_PHY 13 +#define SYS_CTRL_RST_PCIEPHY 14 +#define SYS_CTRL_RST_STATIC 15 +#define SYS_CTRL_RST_GPIO 16 +#define SYS_CTRL_RST_UART1 17 +#define SYS_CTRL_RST_UART2 18 +#define SYS_CTRL_RST_MISC 19 +#define SYS_CTRL_RST_I2S 20 +#define SYS_CTRL_RST_SD 21 +#define SYS_CTRL_RST_MACB 22 +#define SYS_CTRL_RST_PCIEB 23 +#define SYS_CTRL_RST_VIDEO 24 +#define SYS_CTRL_RST_DDR_PHY 25 +#define SYS_CTRL_RST_USBHSPHYB 26 +#define SYS_CTRL_RST_USBDEV 27 +#define SYS_CTRL_RST_ARMDBG 29 +#define SYS_CTRL_RST_PLLA 30 +#define SYS_CTRL_RST_PLLB 31 + +static inline void reset_block(int block, int reset) +{ + u32 reg; + if (reset) + reg = SYS_CTRL_RST_SET_CTRL; + else + reg = SYS_CTRL_RST_CLR_CTRL; + + writel(BIT(block), reg); +} + +static inline void enable_clock(int block) +{ + writel(BIT(block), SYS_CTRL_CLK_SET_CTRL); +} + +static inline void disable_clock(int block) +{ + writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL); +} + +int plla_set_config(int idx); + +#endif /* _NAS782X_CLOCK_H */ diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h new file mode 100644 index 0000000..11e803c --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h @@ -0,0 +1,26 @@ +#ifndef _NAS782X_CPU_H +#define _NAS782X_CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#include <asm/io.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include <asm/arch/hardware.h> +#include <asm/arch/timer.h> + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ + +#define BIT(x) (1 << (x)) + +/* fix "implicit declaration of function" warnning */ +void *memalign(size_t alignment, size_t bytes); +void free(void* mem); +void *malloc(size_t bytes); +void *calloc(size_t n, size_t elem_size); + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _NAS782X_CPU_H */ diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h new file mode 100644 index 0000000..f26b17f --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h @@ -0,0 +1,30 @@ +#ifndef _NAS782X_HARDWARE_H +#define _NAS782X_HARDWARE_H + +/* Core addresses */ +#define USB_HOST_BASE 0x40200000 +#define MACA_BASE 0x40400000 +#define MACB_BASE 0x40800000 +#define MAC_BASE MACA_BASE +#define STATIC_CS0_BASE 0x41000000 +#define STATIC_CS1_BASE 0x41400000 +#define STATIC_CONTROL_BASE 0x41C00000 +#define SATA_DATA_BASE 0x42000000 /* non-functional, DMA just needs an address */ +#define GPIO_1_BASE 0x44000000 +#define GPIO_2_BASE 0x44100000 +#define UART_1_BASE 0x44200000 +#define UART_2_BASE 0x44300000 +#define SYS_CONTROL_BASE 0x44e00000 +#define SEC_CONTROL_BASE 0x44f00000 +#define RPSA_BASE 0x44400000 +#define RPSC_BASE 0x44500000 +#define DDR_BASE 0x44700000 + +#define SATA_BASE 0x45900000 +#define SATA_0_REGS_BASE 0x45900000 +#define SATA_1_REGS_BASE 0x45910000 +#define SATA_DMA_REGS_BASE 0x459a0000 +#define SATA_SGDMA_REGS_BASE 0x459b0000 +#define SATA_HOST_REGS_BASE 0x459e0000 + +#endif /* _NAS782X_HARDWARE_H */ diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h new file mode 100644 index 0000000..810ba5c --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h @@ -0,0 +1,46 @@ +#ifndef _NAS782X_PINMUX_H +#define _NAS782X_PINMUX_H + +#include <asm/arch/cpu.h> + +#define PINMUX_GPIO 0 +#define PINMUX_2 1 +#define PINMUX_3 2 +#define PINMUX_4 3 +#define PINMUX_DEBUG 4 +#define PINMUX_ALT 5 + +#define PINMUX_BANK_MFA 0 +#define PINMUX_BANK_MFB 1 + +/* System control multi-function pin function selection */ +#define PINMUX_SECONDARY_SEL 0x14 +#define PINMUX_TERTIARY_SEL 0x8c +#define PINMUX_QUATERNARY_SEL 0x94 +#define PINMUX_DEBUG_SEL 0x9c +#define PINMUX_ALTERNATIVE_SEL 0xa4 +#define PINMUX_PULLUP_SEL 0xac + +#define PINMUX_UARTA_SIN PINMUX_ALT +#define PINMUX_UARTA_SOUT PINMUX_ALT + +#define PINMUX_STATIC_DATA0 PINMUX_2 +#define PINMUX_STATIC_DATA1 PINMUX_2 +#define PINMUX_STATIC_DATA2 PINMUX_2 +#define PINMUX_STATIC_DATA3 PINMUX_2 +#define PINMUX_STATIC_DATA4 PINMUX_2 +#define PINMUX_STATIC_DATA5 PINMUX_2 +#define PINMUX_STATIC_DATA6 PINMUX_2 +#define PINMUX_STATIC_DATA7 PINMUX_2 +#define PINMUX_STATIC_NWE PINMUX_2 +#define PINMUX_STATIC_NOE PINMUX_2 +#define PINMUX_STATIC_NCS PINMUX_2 +#define PINMUX_STATIC_ADDR18 PINMUX_2 +#define PINMUX_STATIC_ADDR19 PINMUX_2 + +#define PINMUX_MACA_MDC PINMUX_2 +#define PINMUX_MACA_MDIO PINMUX_2 + +extern void pinmux_set(int bank, int pin, int func); + +#endif /* _NAS782X_PINMUX_H */ diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h new file mode 100644 index 0000000..f73afda --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h @@ -0,0 +1,6 @@ +#ifndef _NAS782X_SPL_H +#define _NAS782X_SPL_H + +#include <asm/arch/cpu.h> + +#endif /* _NAS782X_SPL_H */ diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h new file mode 100644 index 0000000..3867e45 --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h @@ -0,0 +1,125 @@ +#ifndef _NAS782X_SYSCTL_H +#define _NAS782X_SYSCTL_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include <asm/arch/hardware.h> + +/** + * System block reset and clock control + */ +#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20) +#define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C) +#define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30) +#define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34) +#define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38) +#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48) +#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C) +#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78) + +/* Scratch registers */ +#define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4) +#define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8) +#define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc) +#define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0) + +#define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0) +#define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4) +#define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8) +#define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC) + +#define SYS_CTRL_GMAC_AUTOSPEED 3 +#define SYS_CTRL_GMAC_RGMII 2 +#define SYS_CTRL_GMAC_SIMPLE_MUX 1 +#define SYS_CTRL_GMAC_CKEN_GTX 0 + +#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64) + +#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0 +#define SYS_CTRL_CKCTRL_SLOW_BIT 8 + + +#define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40) +#define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44) +#define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8) +#define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84) +#define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90) + +/* System control multi-function pin function selection */ +#define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14) +#define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c) +#define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94) +#define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c) +#define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4) +#define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac) + +/* Secure control multi-function pin function selection */ +#define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14) +#define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c) +#define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94) +#define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c) +#define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4) +#define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac) + +#define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68) +#define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98) +#define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0) +#define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8) +#define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0) +#define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4) +#define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4) + +#define REF300_DIV_INT_SHIFT 8 +#define REF300_DIV_FRAC_SHIFT 0 +#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) +#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) + +#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 +#define USBHSPHY_SUSPENDM_MANUAL_STATE 15 +#define USBHSPHY_ATE_ESET 14 +#define USBHSPHY_TEST_DIN 6 +#define USBHSPHY_TEST_ADD 2 +#define USBHSPHY_TEST_DOUT_SEL 1 +#define USBHSPHY_TEST_CLK 0 + +#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 +#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) +#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) +#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) + +#define USBAMUX_DEVICE BIT(4) + +#define USBPHY_REFCLKDIV_SHIFT 2 +#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) +#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) +#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) + +#define USB_CTRL_USB_CKO_SEL_BIT 0 + +#define USB_INT_CLK_XTAL 0 +#define USB_INT_CLK_REF300 2 +#define USB_INT_CLK_PLLB 3 + +#define SYS_CTRL_GMAC_AUTOSPEED 3 +#define SYS_CTRL_GMAC_RGMII 2 +#define SYS_CTRL_GMAC_SIMPLE_MUX 1 +#define SYS_CTRL_GMAC_CKEN_GTX 0 + + +#define PLLB_ENSAT 3 +#define PLLB_OUTDIV 4 +#define PLLB_REFDIV 8 +#define PLLB_DIV_INT_SHIFT 8 +#define PLLB_DIV_FRAC_SHIFT 0 +#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) +#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _NAS782X_SYSCTL_H */ diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h new file mode 100644 index 0000000..ea4d71e --- /dev/null +++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h @@ -0,0 +1,23 @@ +#ifndef _NAS782X_TIMER_H +#define _NAS782X_TIMER_H + +#define TIMER1_BASE (RPSA_BASE + 0x200) +#define TIMER2_BASE (RPSA_BASE + 0x220) + +#define TIMER_LOAD 0 +#define TIMER_CURR 4 +#define TIMER_CTRL 8 +#define TIMER_INTR 0x0C + +#define TIMER_PRESCALE_SHIFT 2 +#define TIMER_PRESCALE_1 0 +#define TIMER_PRESCALE_16 1 +#define TIMER_PRESCALE_256 2 +#define TIMER_MODE_SHIFT 6 +#define TIMER_MODE_FREE_RUNNING 0 +#define TIMER_MODE_PERIODIC 1 +#define TIMER_ENABLE_SHIFT 7 +#define TIMER_DISABLE 0 +#define TIMER_ENABLE 1 + +#endif /* _NAS782X_TIMER_H */ diff --git a/package/boot/uboot-oxnas/files/board/ox820/Kconfig b/package/boot/uboot-oxnas/files/board/ox820/Kconfig new file mode 100644 index 0000000..8f631aa --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/Kconfig @@ -0,0 +1,15 @@ +if TARGET_OX820 + +config SYS_CPU + default "arm1136" + +config SYS_SOC + default "nas782x" + +config SYS_BOARD + default "ox820" + +config SYS_CONFIG_NAME + default "ox820" + +endif diff --git a/package/boot/uboot-oxnas/files/board/ox820/MAINTAINERS b/package/boot/uboot-oxnas/files/board/ox820/MAINTAINERS new file mode 100644 index 0000000..a86ba26 --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/MAINTAINERS @@ -0,0 +1,6 @@ +SHEEVAPLUG BOARD +M: Daniel Golle <daniel@makrotopia.org> +S: Maintained +F: board/ox820/ +F: include/configs/ox820.h +F: configs/ox820_defconfig diff --git a/package/boot/uboot-oxnas/files/board/ox820/Makefile b/package/boot/uboot-oxnas/files/board/ox820/Makefile new file mode 100644 index 0000000..445fc4c --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/Makefile @@ -0,0 +1,15 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ox820.o +obj-y += lowlevel_init.o + +obj-$(CONFIG_SPL_BUILD) += spl_start.o +obj-$(CONFIG_SPL_BUILD) += ddr.o + diff --git a/package/boot/uboot-oxnas/files/board/ox820/ddr.c b/package/boot/uboot-oxnas/files/board/ox820/ddr.c new file mode 100755 index 0000000..a665722 --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/ddr.c @@ -0,0 +1,477 @@ +/******************************************************************* + * + * File: ddr_oxsemi.c + * + * Description: Declarations for DDR routines and data objects + * + * Author: Julien Margetts + * + * Copyright: Oxford Semiconductor Ltd, 2009 + */ +#include <common.h> +#include <asm/arch/clock.h> + +#include "ddr.h" + +typedef unsigned int UINT; + +// DDR TIMING PARAMETERS +typedef struct { + unsigned int holdoff_cmd_A; + unsigned int holdoff_cmd_ARW; + unsigned int holdoff_cmd_N; + unsigned int holdoff_cmd_LM; + unsigned int holdoff_cmd_R; + unsigned int holdoff_cmd_W; + unsigned int holdoff_cmd_PC; + unsigned int holdoff_cmd_RF; + unsigned int holdoff_bank_R; + unsigned int holdoff_bank_W; + unsigned int holdoff_dir_RW; + unsigned int holdoff_dir_WR; + unsigned int holdoff_FAW; + unsigned int latency_CAS; + unsigned int latency_WL; + unsigned int recovery_WR; + unsigned int width_update; + unsigned int odt_offset; + unsigned int odt_drive_all; + unsigned int use_fixed_re; + unsigned int delay_wr_to_re; + unsigned int wr_slave_ratio; + unsigned int rd_slave_ratio0; + unsigned int rd_slave_ratio1; +} T_DDR_TIMING_PARAMETERS; + +// DDR CONFIG PARAMETERS + +typedef struct { + unsigned int ddr_mode; + unsigned int width; + unsigned int blocs; + unsigned int banks8; + unsigned int rams; + unsigned int asize; + unsigned int speed; + unsigned int cmd_mode_wr_cl_bl; +} T_DDR_CONFIG_PARAMETERS; + +//cmd_mode_wr_cl_bl +//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8 +//else cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8 + +// cmd_ bank_ dir_ lat_ rec_ width_ odt_ odt_ fix delay ratio +// A F C update offset all re re_to_we w r0 r1 +// R L P R R W A A W W +//Timing Parameters A W N M R W C F R W W R W S L R +static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4, + 5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device. +static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4, + 5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; +static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4, + 4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts) + +// D B B R A S +// D W L K A S P +//Config Parameters R D C 8 M Z D CMD_MODE +//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte +static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64, + 25, 0x80200A53 }; // 128 MByte +static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128, + 25, 0x80200A63 }; // 256 MByte + +static void ddr_phy_poll_until_locked(void) +{ + volatile UINT reg_tmp = 0; + volatile UINT locked = 0; + + //Extra read to put in delay before starting to poll... + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read + + //POLL C_DDR_PHY2_REG register until clock and flock + //!!! Ideally have a timeout on this. + while (locked == 0) { + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read + + //locked when bits 30 and 31 are set + if (reg_tmp & 0xC0000000) { + locked = 1; + } + } +} + +static void ddr_poll_until_not_busy(void) +{ + volatile UINT reg_tmp = 0; + volatile UINT busy = 1; + + //Extra read to put in delay before starting to poll... + reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read + + //POLL DDR_STAT register until no longer busy + //!!! Ideally have a timeout on this. + while (busy == 1) { + reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read + + //when bit 31 is clear - core is no longer busy + if ((reg_tmp & 0x80000000) == 0x00000000) { + busy = 0; + } + } +} + +static void ddr_issue_command(int commmand) +{ + *(volatile UINT *) C_DDR_CMD_REG = commmand; + ddr_poll_until_not_busy(); +} + +static void ddr_timing_initialisation( + const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters) +{ + volatile UINT reg_tmp = 0; + /* update the DDR controller registers for timing parameters */ + reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24); + *(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp; + + reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28); + *(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp; + + reg_tmp = (ddr_timing_parameters->latency_CAS << 0); + reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4); + reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8); + reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16); + reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21); + reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24); + + *(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp; + + /* Program the timing parameters in the PHY too */ + reg_tmp = (ddr_timing_parameters->use_fixed_re << 16) + | (ddr_timing_parameters->delay_wr_to_re << 8) + | (ddr_timing_parameters->latency_WL << 4) + | (ddr_timing_parameters->latency_CAS << 0); + + *(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp; + + reg_tmp = ddr_timing_parameters->wr_slave_ratio; + + *(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp; + + reg_tmp = ddr_timing_parameters->rd_slave_ratio0; + reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8; + + *(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp; + +} + +static void ddr_normal_initialisation( + const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz) +{ + int i; + volatile UINT tmp = 0; + volatile UINT reg_tmp = 0; + volatile UINT emr_cmd = 0; + UINT refresh; + + //Total size of memory in Mbits... + tmp = ddr_config_parameters->rams * ddr_config_parameters->asize + * ddr_config_parameters->width; + //Deduce value to program into DDR_CFG register... + switch (tmp) { + case 16: + reg_tmp = 0x00020000 * 1; + break; + case 32: + reg_tmp = 0x00020000 * 2; + break; + case 64: + reg_tmp = 0x00020000 * 3; + break; + case 128: + reg_tmp = 0x00020000 * 4; + break; + case 256: + reg_tmp = 0x00020000 * 5; + break; + case 512: + reg_tmp = 0x00020000 * 6; + break; + case 1024: + reg_tmp = 0x00020000 * 7; + break; + case 2048: + reg_tmp = 0x00020000 * 8; + break; + default: + reg_tmp = 0; //forces sims not to work if badly configured + } + + //Memory width + tmp = ddr_config_parameters->rams * ddr_config_parameters->width; + switch (tmp) { + case 8: + reg_tmp = reg_tmp + 0x00400000; + break; + case 16: + reg_tmp = reg_tmp + 0x00200000; + break; + case 32: + reg_tmp = reg_tmp + 0x00000000; + break; + default: + reg_tmp = 0; //forces sims not to work if badly configured + } + + //Setup DDR Mode + switch (ddr_config_parameters->ddr_mode) { + case 0: + reg_tmp = reg_tmp + 0x00000000; + break; //SDR + case 1: + reg_tmp = reg_tmp + 0x40000000; + break; //DDR + case 2: + reg_tmp = reg_tmp + 0x80000000; + break; //DDR2 + default: + reg_tmp = 0; //forces sims not to work if badly configured + } + + //Setup Banks + if (ddr_config_parameters->banks8 == 1) { + reg_tmp = reg_tmp + 0x00800000; + } + + //Program DDR_CFG register... + *(volatile UINT *) C_DDR_CFG_REG = reg_tmp; + + //Configure PHY0 reg - se_mode is bit 1, + //needs to be 1 for DDR (single_ended drive) + switch (ddr_config_parameters->ddr_mode) { + case 0: + reg_tmp = 2 + (0 << 4); + break; //SDR + case 1: + reg_tmp = 2 + (4 << 4); + break; //DDR + case 2: + reg_tmp = 0 + (4 << 4); + break; //DDR2 + default: + reg_tmp = 0; + } + + //Program DDR_PHY0 register... + *(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp; + + //Read DDR_PHY* registers to exercise paths for vcd + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3; + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1; + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0; + + //Start up sequences - Different dependant on DDR mode + switch (ddr_config_parameters->ddr_mode) { + case 2: //DDR2 + //Start-up sequence: follows procedure described in Micron datasheet. + //start up DDR PHY DLL + reg_tmp = 0x00022828; // dll on, start point and inc = h28 + *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp; + + reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28 + *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp; + + ddr_phy_poll_until_locked(); + + udelay(200); //200us + + //Startup SDRAM... + //!!! Software: CK should be running for 200us before wake-up + ddr_issue_command( C_CMD_WAKE_UP); + ddr_issue_command( C_CMD_NOP); + ddr_issue_command( C_CMD_PRECHARGE_ALL); + ddr_issue_command( C_CMD_DDR2_EMR2); + ddr_issue_command( C_CMD_DDR2_EMR3); + + emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE + + C_CMD_ENABLE_DLL; + + ddr_issue_command(emr_cmd); + //Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation... + udelay(1); //1us + ddr_issue_command( + ddr_config_parameters->cmd_mode_wr_cl_bl + + C_CMD_RESET_DLL); + udelay(1); //1us + + //!!! Software: Wait 200 CK cycles before... + //for(i=1; i<=2; i++) { + ddr_issue_command(C_CMD_PRECHARGE_ALL); + // !!! Software: Wait here at least 8 CK cycles + //} + //need a wait here to ensure PHY DLL lock before the refresh is issued + udelay(1); //1us + for (i = 1; i <= 2; i++) { + ddr_issue_command( C_CMD_AUTO_REFRESH); + //!!! Software: Wait here at least 8 CK cycles to satify tRFC + udelay(1); //1us + } + //As before but without 'RESET_DLL' bit set... + ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl); + udelay(1); //1us + // OCD commands + ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT); + ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT); + break; + + default: + break; //Do nothing + } + + //Enable auto-refresh + + // 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us + // We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles + // Our core now does 8 refreshes in a go, so we multiply this period by 8 + + refresh = (64000 * mhz) / 8192; // Refresh period in clocks + + reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read +#ifdef BURST_REFRESH_ENABLE + reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8); + reg_tmp |= C_CFG_BURST_REFRESH_ENABLE; +#else + reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1); + reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE; +#endif + *(volatile UINT *) C_DDR_CFG_REG = reg_tmp; + + //Verify register contents + reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read + //printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX"); + //TBD Check_data (read_data, dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass); + reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read + //TBD Check_data (read_data, cfg_reg, "Error: bad DDR_CFG read", tb_pass); + + //disable optimised wrapping + if (ddr_config_parameters->ddr_mode == 2) { + reg_tmp = 0xFFFF0000; + *(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp; + } + + //enable midbuffer followon + reg_tmp = *(volatile UINT *) C_DDR_ARB_REG; // read + reg_tmp = 0xFFFF0000 | reg_tmp; + *(volatile UINT *) C_DDR_ARB_REG = reg_tmp; + + // Enable write behind coherency checking for all clients + + reg_tmp = 0xFFFF0000; + *(volatile UINT *) C_DDR_AHB4_REG = reg_tmp; + + //Wait for 200 clock cycles for SDRAM DLL to lock... + udelay(1); //1us +} + +// Function used to Setup DDR core + +void ddr_setup(int mhz) +{ + static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters = + &C_TP_DDR2_25_CL6_1GB; + static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters = + &C_CP_DDR2_25_CL6; + + //Bring core out of Reset + *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON; + + //DDR TIMING INITIALISTION + ddr_timing_initialisation(ddr_timing_parameters); + + //DDR NORMAL INITIALISATION + ddr_normal_initialisation(ddr_config_parameters, mhz); + + // route all writes through one client + *(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0 + << DDR_ROUTE_CPU0_INSTR_SHIFT) + | (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT) + | (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT) + | (2 << DDR_ROUTE_CPU1_INSTR_SHIFT) + | (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT) + | (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT); + + //Bring all clients out of reset + *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF; + +} + +void set_ddr_timing(unsigned int w, unsigned int i) +{ + unsigned int reg; + unsigned int wnow = 16; + unsigned int inow = 32; + + /* reset all timing controls to known value (31) */ + writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING); + writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK, + DDR_PHY_TIMING); + writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING); + + /* step up or down read delay to the requested value */ + while (wnow != w) { + if (wnow < w) { + reg = DDR_PHY_TIMING_INC; + wnow++; + } else { + reg = 0; + wnow--; + } + writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING); + writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg, + DDR_PHY_TIMING); + writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING); + } + + /* now write delay */ + while (inow != i) { + if (inow < i) { + reg = DDR_PHY_TIMING_INC; + inow++; + } else { + reg = 0; + inow--; + } + writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING); + writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg, + DDR_PHY_TIMING); + writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING); + } +} + +//Function used to Setup SDRAM in DDR/SDR mode +void init_ddr(int mhz) +{ + /* start clocks */ + enable_clock(SYS_CTRL_CLK_DDRPHY); + enable_clock(SYS_CTRL_CLK_DDR); + enable_clock(SYS_CTRL_CLK_DDRCK); + + /* bring phy and core out of reset */ + reset_block(SYS_CTRL_RST_DDR_PHY, 0); + reset_block(SYS_CTRL_RST_DDR, 0); + + /* DDR runs at half the speed of the CPU */ + ddr_setup(mhz >> 1); + return; +} diff --git a/package/boot/uboot-oxnas/files/board/ox820/ddr.h b/package/boot/uboot-oxnas/files/board/ox820/ddr.h new file mode 100644 index 0000000..a3c1990 --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/ddr.h @@ -0,0 +1,148 @@ +/******************************************************************* +* +* File: ddr_oxsemi.h +* +* Description: Declarations for DDR routines and data objects +* +* Author: Julien Margetts +* +* Copyright: Oxford Semiconductor Ltd, 2009 +*/ + +void ddr_oxsemi_setup(int mhz); + +/* define to refresh in bursts of 8 */ +#define BURST_REFRESH_ENABLE + +#define DDR_BASE 0x44700000 + +#define C_DDR_CFG_REG (DDR_BASE + 0x00) +#define C_CFG_DDR 0x80000000 +#define C_CFG_SDR 0x00000000 +#define C_CFG_WIDTH8 0x00200000 +#define C_CFG_WIDTH16 0x00100000 +#define C_CFG_WIDTH32 0x00000000 +#define C_CFG_SIZE_FACTOR 0x00020000 +#define C_CFG_REFRESH_ENABLE 0x00010000 +#define C_CFG_BURST_REFRESH_ENABLE 0x01000000 +#define C_CFG_SIZE(x) (x << 17) +#define CFG_SIZE_2MB 1 +#define CFG_SIZE_4MB 2 +#define CFG_SIZE_8MB 3 +#define CFG_SIZE_16MB 4 +#define CFG_SIZE_32MB 5 +#define CFG_SIZE_64MB 6 +#define CFG_SIZE_128MB 7 + +#define C_DDR_BLKEN_REG (DDR_BASE + 0x04) +#define C_BLKEN_DDR_ON 0x80000000 + +#define C_DDR_STAT_REG (DDR_BASE + 0x08) + +#define C_DDR_CMD_REG (DDR_BASE + 0x0C) +#define C_CMD_SEND_COMMAND (1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates +#define C_CMD_WAKE_UP 0x80FC0000 // Asserts CKE +#define C_CMD_MODE_SDR 0x80200022 // Sets CL=2 BL=4 +#define C_CMD_MODE_DDR 0x80200063 // Sets CL=2.5 BL=8 +#define C_CMD_RESET_DLL 0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR +#define C_CMD_PRECHARGE_ALL 0x80280400 +#define C_CMD_AUTO_REFRESH 0x80240000 +#define C_CMD_SELF_REFRESH 0x80040000 // As AUTO-REFRESH but with CKE low +#define C_CMD_NOP 0x803C0000 // NOP just to insert guaranteed delay +#define C_CMD_DDR2_EMR1 0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set +//#define C_CMD_DDR2_EMR1 0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set +#define C_CMD_ENABLE_DLL 0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1 +#define C_CMD_DISABLE_DLL 0x00000001 +#define C_CMD_REDUCED_DRIVE 0x00000002 +#define C_CMD_ODT_DISABLED 0x00000000 +#define C_CMD_ODT_50 0x00000044 +#define C_CMD_ODT_75 0x00000004 +#define C_CMD_ODT_150 0x00000040 +#define C_CMD_MODE_DDR2_OCD_DFLT 0x00000380 +#define C_CMD_MODE_DDR2_OCD_EXIT 0x00000000 + +#define C_CMD_DDR2_EMR2 0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set +#define C_CMD_DDR2_EMR3 0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set + +#define C_DDR_AHB_REG (DDR_BASE + 0x10) +#define C_AHB_NO_RCACHES 0xFFFF0000 +#define C_AHB_FLUSH_ALL_RCACHES 0x0000FFFF +#define C_AHB_FLUSH_AHB0_RCACHE 0x00000001 +#define C_AHB_FLUSH_AHB1_RCACHE 0x00000002 + +#define C_DDR_DLL_REG (DDR_BASE + 0x14) +#define C_DLL_DISABLED 0x00000000 +#define C_DLL_MANUAL 0x80000000 +#define C_DLL_AUTO_OFFSET 0xA0000000 +#define C_DLL_AUTO_IN_REFRESH 0xC0000000 +#define C_DLL_AUTOMATIC 0xE0000000 + +#define C_DDR_MON_REG (DDR_BASE + 0x18) +#define C_MON_ALL 0x00000010 +#define C_MON_CLIENT 0x00000000 + +#define C_DDR_DIAG_REG (DDR_BASE + 0x1C) +#define C_DDR_DIAG2_REG (DDR_BASE + 0x20) + +#define C_DDR_IOC_REG (DDR_BASE + 0x24) +#define C_DDR_IOC_PWR_DWN (1 << 10) +#define C_DDR_IOC_SEL_SSTL (1 << 9) +#define C_DDR_IOC_CK_DRIVE(x) ((x) << 6) +#define C_DDR_IOC_DQ_DRIVE(x) ((x) << 3) +#define C_DDR_IOC_XX_DRIVE(x) ((x) << 0) + +#define C_DDR_ARB_REG (DDR_BASE + 0x28) +#define C_DDR_ARB_MIDBUF (1 << 4) +#define C_DDR_ARB_LRUBANK (1 << 3) +#define C_DDR_ARB_REQAGE (1 << 2) +#define C_DDR_ARB_DATDIR (1 << 1) +#define C_DDR_ARB_DATDIR_NC (1 << 0) + +#define C_TOP_ADDRESS_BIT_TEST 22 +#define C_MEM_BASE C_SDRAM_BASE + +#define C_MEM_TEST_BASE 0 +#define C_MEM_TEST_LEN 1920 +#define C_MAX_RAND_ACCESS_LEN 16 + +#define C_DDR_REG_IGNORE (DDR_BASE + 0x2C) +#define C_DDR_AHB4_REG (DDR_BASE + 0x44) + +#define C_DDR_REG_TIMING0 (DDR_BASE + 0x34) +#define C_DDR_REG_TIMING1 (DDR_BASE + 0x38) +#define C_DDR_REG_TIMING2 (DDR_BASE + 0x3C) + +#define C_DDR_REG_PHY0 (DDR_BASE + 0x48) +#define C_DDR_REG_PHY1 (DDR_BASE + 0x4C) +#define C_DDR_REG_PHY2 (DDR_BASE + 0x50) +#define C_DDR_REG_PHY3 (DDR_BASE + 0x54) + +#define C_DDR_REG_GENERIC (DDR_BASE + 0x60) + +#define C_OXSEMI_DDRC_SIGNATURE 0x054415AA + +#define DDR_PHY_BASE (DDR_BASE + 0x80000) +#define DDR_PHY_TIMING (DDR_PHY_BASE + 0x48) +#define DDR_PHY_TIMING_CK (1 << 12) +#define DDR_PHY_TIMING_INC (1 << 13) +#define DDR_PHY_TIMING_W_CE (1 << 14) +#define DDR_PHY_TIMING_W_RST (1 << 15) +#define DDR_PHY_TIMING_I_CE (1 << 16) +#define DDR_PHY_TIMING_I_RST (1 << 17) + +#define C_DDR_REG_PHY_TIMING (DDR_PHY_BASE + 0x50) +#define C_DDR_REG_PHY_WR_RATIO (DDR_PHY_BASE + 0x74) +#define C_DDR_REG_PHY_RD_RATIO (DDR_PHY_BASE + 0x78) + +#define C_DDR_TRANSACTION_ROUTING (DDR_PHY_BASE + 0xC8) +#define DDR_ROUTE_CPU0_INSTR_SHIFT 0 +#define DDR_ROUTE_CPU0_RDDATA_SHIFT 4 +#define DDR_ROUTE_CPU0_WRDATA_SHIFT 6 +#define DDR_ROUTE_CPU1_INSTR_SHIFT 8 +#define DDR_ROUTE_CPU1_RDDATA_SHIFT 12 +#define DDR_ROUTE_CPU1_WRDATA_SHIFT 14 + +unsigned int ddrc_signature(void); +void set_ddr_timing(unsigned int w, unsigned int i); +int pause(unsigned int us); +void set_ddr_sel(int val); diff --git a/package/boot/uboot-oxnas/files/board/ox820/lowlevel_init.S b/package/boot/uboot-oxnas/files/board/ox820/lowlevel_init.S new file mode 100644 index 0000000..3328b7a --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/lowlevel_init.S @@ -0,0 +1,20 @@ +#include <config.h> +#ifndef CONFIG_SPL_BUILD + +.globl lowlevel_init +lowlevel_init: + /* + * Copy exception table to relocated address in internal SRAM + */ + ldr r0, src /* Address of exception table in flash */ + ldr r1, dest /* Relocated address of exception table */ + ldmia r0!, {r3-r10} /* Copy exception table and jump values from */ + stmia r1!, {r3-r10} /* FLASH to relocated address */ + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + mov pc, lr + +src: .word CONFIG_SYS_TEXT_BASE +dest: .word CONFIG_SRAM_BASE + +#endif
\ No newline at end of file diff --git a/package/boot/uboot-oxnas/files/board/ox820/ox820.c b/package/boot/uboot-oxnas/files/board/ox820/ox820.c new file mode 100644 index 0000000..f93cc9c --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/ox820.c @@ -0,0 +1,374 @@ +#include <common.h> +#include <spl.h> +#include <phy.h> +#include <netdev.h> +#include <ide.h> +#include <nand.h> +#include <asm/arch/spl.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> +#include <asm/arch/sysctl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD + +#ifdef DEBUG +#define DILIGENCE (1048576/4) +static int test_memory(u32 memory) +{ + volatile u32 *read; + volatile u32 *write; + const u32 INIT_PATTERN = 0xAA55AA55; + const u32 INC_PATTERN = 0x01030507; + u32 pattern; + int check; + int i; + + check = 0; + read = write = (volatile u32 *) memory; + pattern = INIT_PATTERN; + for (i = 0; i < DILIGENCE; i++) { + *write++ = pattern; + pattern += INC_PATTERN; + } + puts("testing\n"); + pattern = INIT_PATTERN; + for (i = 0; i < DILIGENCE; i++) { + check += (pattern == *read++) ? 1 : 0; + pattern += INC_PATTERN; + } + return (check == DILIGENCE) ? 0 : -1; +} +#endif + +void uart_init(void) +{ + /* Reset UART1 */ + reset_block(SYS_CTRL_RST_UART1, 1); + udelay(100); + reset_block(SYS_CTRL_RST_UART1, 0); + udelay(100); + + /* Setup pin mux'ing for UART1 */ + pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN); + pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT); +} + +extern void init_ddr(int mhz); + +void board_inithw(void) +{ + int plla_freq; +#ifdef DEBUG + int i; +#endif /* DEBUG */ + + timer_init(); + uart_init(); + preloader_console_init(); + + plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ); + init_ddr(plla_freq); + +#ifdef DEBUG + if(test_memory(CONFIG_SYS_SDRAM_BASE)) { + puts("memory test failed\n"); + } else { + puts("memory test done\n"); + } +#endif /* DEBUG */ +#ifdef CONFIG_SPL_BSS_DRAM_START + extern char __bss_dram_start[]; + extern char __bss_dram_end[]; + memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start); +#endif +} + +void board_init_f(ulong dummy) +{ + /* Set the stack pointer. */ + asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Set global data pointer. */ + gd = &gdata; + + board_inithw(); + + board_init_r(NULL, 0); +} + +u32 spl_boot_device(void) +{ + return CONFIG_SPL_BOOT_DEVICE; +} + +#ifdef CONFIG_SPL_BLOCK_SUPPORT +void spl_block_device_init(void) +{ + ide_init(); +} +#endif + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return (serial_tstc() && serial_getc() == 'c'); +} +#endif + +void spl_display_print(void) +{ + /* print a hint, so that we will not use the wrong SPL by mistake */ + puts(" Boot device: " BOOT_DEVICE_TYPE "\n" ); +} + +void lowlevel_init(void) +{ +} + +#ifdef USE_DL_PREFIX +/* quick and dirty memory allocation */ +static ulong next_mem = CONFIG_SPL_MALLOC_START; + +void *memalign(size_t alignment, size_t bytes) +{ + ulong mem = ALIGN(next_mem, alignment); + + next_mem = mem + bytes; + + if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) { + printf("spl: out of memory\n"); + hang(); + } + + return (void *)mem; +} + +void free(void* mem) +{ +} +#endif + +#endif /* CONFIG_SPL_BUILD */ + +int board_early_init_f(void) +{ + return 0; +} + +#define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4) +#define STATIC_READ_CYCLE_SHIFT 0 +#define STATIC_DELAYED_OE (1 << 7) +#define STATIC_WRITE_CYCLE_SHIFT 8 +#define STATIC_WRITE_PULSE_SHIFT 16 +#define STATIC_WRITE_BURST_EN (1 << 23) +#define STATIC_TURN_AROUND_SHIFT 24 +#define STATIC_BUFFER_PRESENT (1 << 28) +#define STATIC_READ_BURST_EN (1 << 29) +#define STATIC_BUS_WIDTH8 (0 << 30) +#define STATIC_BUS_WIDTH16 (1 << 30) +#define STATIC_BUS_WIDTH32 (2 << 30) + +void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN)); + if (ctrl & NAND_CLE) + nandaddr |= BIT(NAND_CLE_ADDR_PIN); + else if (ctrl & NAND_ALE) + nandaddr |= BIT(NAND_ALE_ADDR_PIN); + this->IO_ADDR_W = (void __iomem *) nandaddr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, (void __iomem *) nandaddr); +} + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND) + +int nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + udelay(chip->chip_delay); + + return 1; +} + +void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = readb(chip->IO_ADDR_R); +} + +void nand_dev_reset(struct nand_chip *chip) +{ + writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN)); + udelay(chip->chip_delay); + writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN)); + while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) { + ; + } +} + +#else + +#define nand_dev_reset(chip) /* framework will reset the chip anyway */ +#define nand_read_buf NULL /* framework will provide a default one */ +#define nand_dev_ready NULL /* dev_ready is optional */ + +#endif + +int board_nand_init(struct nand_chip *chip) +{ + /* Block reset Static core */ + reset_block(SYS_CTRL_RST_STATIC, 1); + reset_block(SYS_CTRL_RST_STATIC, 0); + + /* Enable clock to Static core */ + enable_clock(SYS_CTRL_CLK_STATIC); + + /* enable flash support on static bus. + * Enable static bus onto GPIOs, only CS0 */ + pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0); + pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1); + pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2); + pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3); + pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4); + pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5); + pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6); + pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7); + + pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE); + pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE); + pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS); + pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18); + pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19); + + /* Setup the static bus CS0 to access FLASH */ + + writel((0x3f << STATIC_READ_CYCLE_SHIFT) + | (0x3f << STATIC_WRITE_CYCLE_SHIFT) + | (0x1f << STATIC_WRITE_PULSE_SHIFT) + | (0x03 << STATIC_TURN_AROUND_SHIFT) | + STATIC_BUS_WIDTH16, + STATIC_CTL_BANK0); + + chip->cmd_ctrl = nand_hwcontrol; + chip->ecc.mode = NAND_ECC_SOFT; + chip->chip_delay = 30; + chip->dev_ready = nand_dev_ready; + chip->read_buf = nand_read_buf; + + nand_dev_reset(chip); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_arch_number = MACH_TYPE_OXNAS; + + /* assume uart is already initialized by SPL */ + +#if defined(CONFIG_START_IDE) + puts("IDE: "); + ide_init(); +#endif + + return 0; +} + +/* copied from board/evb64260/sdram_init.c */ +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +static long int dram_size (long int *base, long int maxsize) +{ + volatile long int *addr, *b = base; + long int cnt, val, save1, save2; + +#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */ + for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); + cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1 = *addr; /* save contents of addr */ + save2 = *b; /* save contents of base */ + + *addr = cnt; /* write cnt to addr */ + *b = 0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr = save1; /* restore *addr */ + *b = save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + + *addr = save1; + *b = save2; + + if (val != cnt) { + /* fix boundary condition.. STARTVAL means zero */ + if (cnt == STARTVAL / sizeof (long)) + cnt = 0; + return (cnt * sizeof (long)); + } + } + return maxsize; +} + +int dram_init(void) +{ + gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + u32 value; + + /* set the pin multiplexers to enable talking to Ethernent Phys */ + pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC); + pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO); + + // Ensure the MAC block is properly reset + reset_block(SYS_CTRL_RST_MAC, 1); + udelay(10); + reset_block(SYS_CTRL_RST_MAC, 0); + + // Enable the clock to the MAC block + enable_clock(SYS_CTRL_CLK_MAC); + + value = readl(SYS_CTRL_GMAC_CTRL); + /* Use simple mux for 25/125 Mhz clock switching */ + value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX); + /* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */ + value |= BIT(SYS_CTRL_GMAC_CKEN_GTX); + /* set auto tx speed */ + value |= BIT(SYS_CTRL_GMAC_AUTOSPEED); + + writel(value, SYS_CTRL_GMAC_CTRL); + + return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII); +} + diff --git a/package/boot/uboot-oxnas/files/board/ox820/spl_start.S b/package/boot/uboot-oxnas/files/board/ox820/spl_start.S new file mode 100644 index 0000000..2eab3f5 --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/spl_start.S @@ -0,0 +1,21 @@ +.section .init +.globl _spl_start +_spl_start: + b _start + b _start+0x4 + b _start+0x8 + b _start+0xc + b _start+0x10 + b _start+0x14 + b _start+0x18 + b _start+0x1c + .space 0x30 - (. - _spl_start) + .ascii "BOOT" /* 0x30 signature*/ + .word 0x50 /* 0x34 header size itself */ + .word 0 /* 0x38 */ + .word 0x5000f000 /* boot report location */ + .word _start /* 0x40 */ + +main_crc_size: .word code_size /* 0x44 filled by linker */ +main_crc: .word 0 /* 0x48 fill later */ +header_crc: .word 0 /* 0x4C header crc*/ diff --git a/package/boot/uboot-oxnas/files/board/ox820/u-boot-spl.lds b/package/boot/uboot-oxnas/files/board/ox820/u-boot-spl.lds new file mode 100644 index 0000000..a8d90df --- /dev/null +++ b/package/boot/uboot-oxnas/files/board/ox820/u-boot-spl.lds @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY +{ + sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE + dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE +} + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_spl_start) +SECTIONS +{ + .text.0 : + { + *(.init*) + } + + + /* Start of the rest of the SPL */ + code_start = . ; + + .text.1 : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + __image_copy_end = .; + code_size = . - code_start; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + . = ALIGN(0x800); + + _end = .; + + .bss.sram __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss.stdio_devices) + *(.bss.serial_current) + . = ALIGN(4); + __bss_end = .; + } + + .bss : { + __bss_dram_start = .; + *(.bss*) + __bss_dram_end = .; + } > dram + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/package/boot/uboot-oxnas/files/common/env_ext4.c b/package/boot/uboot-oxnas/files/common/env_ext4.c new file mode 100644 index 0000000..e98d94d --- /dev/null +++ b/package/boot/uboot-oxnas/files/common/env_ext4.c @@ -0,0 +1,116 @@ +/* + * (c) Copyright 2011 by Tigris Elektronik GmbH + * + * Author: + * Maximilian Schwerin <mvs@tigris.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <command.h> +#include <environment.h> +#include <linux/stddef.h> +#include <malloc.h> +#include <search.h> +#include <errno.h> +#include <ext4fs.h> + +char *env_name_spec = "EXT4"; + +env_t *env_ptr; + +DECLARE_GLOBAL_DATA_PTR; + +int env_init(void) +{ + /* use default */ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; + + return 0; +} + +#ifdef CONFIG_CMD_SAVEENV +int saveenv(void) +{ + env_t env_new; + ssize_t len; + char *res; + block_dev_desc_t *dev_desc = NULL; + int dev = EXT4_ENV_DEVICE; + int part = EXT4_ENV_PART; + int err; + + res = (char *)&env_new.data; + len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + + dev_desc = get_dev(EXT4_ENV_INTERFACE, dev); + if (dev_desc == NULL) { + printf("Failed to find %s%d\n", + EXT4_ENV_INTERFACE, dev); + return 1; + } + + err = ext4_register_device(dev_desc, part); + if (err) { + printf("Failed to register %s%d:%d\n", + EXT4_ENV_INTERFACE, dev, part); + return 1; + } + + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t)); + ext4fs_close(); + if (err == -1) { + printf("\n** Unable to write \"%s\" from %s%d:%d **\n", + EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part); + return 1; + } + + puts("done\n"); + return 0; +} +#endif /* CONFIG_CMD_SAVEENV */ + +void env_relocate_spec(void) +{ + char buf[CONFIG_ENV_SIZE]; + block_dev_desc_t *dev_desc = NULL; + int dev = EXT4_ENV_DEVICE; + int part = EXT4_ENV_PART; + int err; + + dev_desc = get_dev(EXT4_ENV_INTERFACE, dev); + if (dev_desc == NULL) { + printf("Failed to find %s%d\n", + EXT4_ENV_INTERFACE, dev); + set_default_env(NULL); + return; + } + + err = ext4_register_device(dev_desc, part); + if (err) { + printf("Failed to register %s%d:%d\n", + EXT4_ENV_INTERFACE, dev, part); + set_default_env(NULL); + return; + } + + err = ext4_read_file(EXT4_ENV_FILE, (uchar *)&buf, 0, CONFIG_ENV_SIZE); + ext4fs_close(); + + if (err == -1) { + printf("\n** Unable to read \"%s\" from %s%d:%d **\n", + EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part); + set_default_env(NULL); + return; + } + + env_import(buf, 1); +} diff --git a/package/boot/uboot-oxnas/files/common/spl/spl_block.c b/package/boot/uboot-oxnas/files/common/spl/spl_block.c new file mode 100644 index 0000000..f16413a --- /dev/null +++ b/package/boot/uboot-oxnas/files/common/spl/spl_block.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2013 + * + * Ma Haijun <mahaijuns@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <spl.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <version.h> +#include <part.h> +#include <fat.h> +#include <ext4fs.h> + +/* should be implemented by board */ +extern void spl_block_device_init(void); + +block_dev_desc_t * spl_get_block_device(void) +{ + block_dev_desc_t * device; + + spl_block_device_init(); + + device = get_dev(CONFIG_SPL_BLOCKDEV_INTERFACE, CONFIG_SPL_BLOCKDEV_ID); + if (!device) { + printf("blk device %s%d not exists\n", + CONFIG_SPL_BLOCKDEV_INTERFACE, + CONFIG_SPL_BLOCKDEV_ID); + hang(); + } + + return device; +} + +#ifdef CONFIG_SPL_FAT_SUPPORT +static int block_load_image_fat(const char *filename) +{ + int err; + struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + err = file_fat_read(filename, header, sizeof(struct image_header)); + if (err <= 0) + goto end; + + spl_parse_image_header(header); + + err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); + +end: + if (err <= 0) + printf("spl: error reading image %s, err - %d\n", + filename, err); + + return (err <= 0); +} + +#ifdef CONFIG_SPL_OS_BOOT +static int block_load_image_fat_os(void) +{ + int err; + + err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME, + (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0); + if (err <= 0) { + return -1; + } + + return block_load_image_fat(CONFIG_SPL_FAT_LOAD_KERNEL_NAME); +} +#endif + +void spl_block_load_image(void) +{ + int err; + block_dev_desc_t * device; + + device = spl_get_block_device(); + err = fat_register_device(device, CONFIG_BLOCKDEV_FAT_BOOT_PARTITION); + if (err) { + printf("spl: fat register err - %d\n", err); + hang(); + } +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || block_load_image_fat_os()) +#endif + { + err = block_load_image_fat(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + if (err) + hang(); + } +} +#elif defined(CONFIG_SPL_EXT4_SUPPORT) /* end CONFIG_SPL_FAT_SUPPORT */ +static int block_load_image_ext4(const char *filename) +{ + int err; + struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + err = ext4_read_file(filename, header, 0, sizeof(struct image_header)); + if (err <= 0) + goto end; + + spl_parse_image_header(header); + + err = ext4_read_file(filename, (u8 *)spl_image.load_addr, 0, 0); + +end: + return (err <= 0); +} + +#ifdef CONFIG_SPL_OS_BOOT +static int block_load_image_ext4_os(void) +{ + int err; + + err = ext4_read_file(CONFIG_SPL_EXT4_LOAD_ARGS_NAME, + (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, 0); + if (err <= 0) { + return -1; + } + + return block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_KERNEL_NAME); +} +#endif + +void spl_block_load_image(void) +{ + int err; + block_dev_desc_t * device; + + device = spl_get_block_device(); + err = ext4_register_device(device, CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION); + if (err) { + hang(); + } +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || block_load_image_ext4_os()) +#endif + { + err = block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME); + if (err) + hang(); + } +} +#else /* end CONFIG_SPL_EXT4_SUPPORT */ +static int block_load_image_raw(block_dev_desc_t * device, lbaint_t sector) +{ + int n; + u32 image_size_sectors; + struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + /* read image header to find the image size & load address */ + n = device->block_read(device->dev, sector, 1, header); + + if (n != 1) { + printf("spl: blk read err\n"); + return 1; + } + + spl_parse_image_header(header); + + /* convert size to sectors - round up */ + image_size_sectors = (spl_image.size + 512 - 1) / 512; + n = device->block_read(device->dev, sector, image_size_sectors, + (void *)spl_image.load_addr); + + if (n != image_size_sectors) { + printf("spl: blk read err\n"); + return 1; + } + return 0; +} + +#ifdef CONFIG_SPL_OS_BOOT +static int block_load_image_raw_os(block_dev_desc_t * device) +{ + int n; + + n = device->block_read(device->dev, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR, + CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS, + (u32 *)CONFIG_SYS_SPL_ARGS_ADDR); + /* flush cache after read */ + flush_cache(addr, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS * 512); + + if (n != CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS) { + printf("args blk read error\n"); + return -1; + } + + return block_load_image_raw(device, CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR); +} +#endif + +void spl_block_load_image(void) +{ + int err; + block_dev_desc_t * device; + + device = spl_get_block_device(); +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || block_load_image_raw_os(device)) +#endif + { + err = block_load_image_raw(device, + CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR); + if (err) + hang(); + } +} +#endif /* CONFIG_SPL_FAT_SUPPORT */ diff --git a/package/boot/uboot-oxnas/files/configs/ox820_defconfig b/package/boot/uboot-oxnas/files/configs/ox820_defconfig new file mode 100644 index 0000000..48a16d0 --- /dev/null +++ b/package/boot/uboot-oxnas/files/configs/ox820_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_OX820=y +CONFIG_TARGET_OX820=y diff --git a/package/boot/uboot-oxnas/files/drivers/block/plxsata_ide.c b/package/boot/uboot-oxnas/files/drivers/block/plxsata_ide.c new file mode 100644 index 0000000..7e0e78f --- /dev/null +++ b/package/boot/uboot-oxnas/files/drivers/block/plxsata_ide.c @@ -0,0 +1,1170 @@ +/* + * (C) Copyright 2005 + * Oxford Semiconductor Ltd + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,` + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/clock.h> + +/** + * SATA related definitions + */ +#define ATA_PORT_CTL 0 +#define ATA_PORT_FEATURE 1 +#define ATA_PORT_NSECT 2 +#define ATA_PORT_LBAL 3 +#define ATA_PORT_LBAM 4 +#define ATA_PORT_LBAH 5 +#define ATA_PORT_DEVICE 6 +#define ATA_PORT_COMMAND 7 + +/* The offsets to the SATA registers */ +#define SATA_ORB1_OFF 0 +#define SATA_ORB2_OFF 1 +#define SATA_ORB3_OFF 2 +#define SATA_ORB4_OFF 3 +#define SATA_ORB5_OFF 4 + +#define SATA_FIS_ACCESS 11 +#define SATA_INT_STATUS_OFF 12 /* Read only */ +#define SATA_INT_CLR_OFF 12 /* Write only */ +#define SATA_INT_ENABLE_OFF 13 /* Read only */ +#define SATA_INT_ENABLE_SET_OFF 13 /* Write only */ +#define SATA_INT_ENABLE_CLR_OFF 14 /* Write only */ +#define SATA_VERSION_OFF 15 +#define SATA_CONTROL_OFF 23 +#define SATA_COMMAND_OFF 24 +#define SATA_PORT_CONTROL_OFF 25 +#define SATA_DRIVE_CONTROL_OFF 26 + +/* The offsets to the link registers that are access in an asynchronous manner */ +#define SATA_LINK_DATA 28 +#define SATA_LINK_RD_ADDR 29 +#define SATA_LINK_WR_ADDR 30 +#define SATA_LINK_CONTROL 31 + +/* SATA interrupt status register fields */ +#define SATA_INT_STATUS_EOC_RAW_BIT ( 0 + 16) +#define SATA_INT_STATUS_ERROR_BIT ( 2 + 16) +#define SATA_INT_STATUS_EOADT_RAW_BIT ( 1 + 16) + +/* SATA core command register commands */ +#define SATA_CMD_WRITE_TO_ORB_REGS 2 +#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND 4 + +#define SATA_CMD_BUSY_BIT 7 + +#define SATA_SCTL_CLR_ERR 0x00000316UL + +#define SATA_LBAL_BIT 0 +#define SATA_LBAM_BIT 8 +#define SATA_LBAH_BIT 16 +#define SATA_HOB_LBAH_BIT 24 +#define SATA_DEVICE_BIT 24 +#define SATA_NSECT_BIT 0 +#define SATA_HOB_NSECT_BIT 8 +#define SATA_LBA32_BIT 0 +#define SATA_LBA40_BIT 8 +#define SATA_FEATURE_BIT 16 +#define SATA_COMMAND_BIT 24 +#define SATA_CTL_BIT 24 + +/* ATA status (7) register field definitions */ +#define ATA_STATUS_BSY_BIT 7 +#define ATA_STATUS_DRDY_BIT 6 +#define ATA_STATUS_DF_BIT 5 +#define ATA_STATUS_DRQ_BIT 3 +#define ATA_STATUS_ERR_BIT 0 + +/* ATA device (6) register field definitions */ +#define ATA_DEVICE_FIXED_MASK 0xA0 +#define ATA_DEVICE_DRV_BIT 4 +#define ATA_DEVICE_DRV_NUM_BITS 1 +#define ATA_DEVICE_LBA_BIT 6 + +/* ATA Command register initiated commands */ +#define ATA_CMD_INIT 0x91 +#define ATA_CMD_IDENT 0xEC + +#define SATA_STD_ASYNC_REGS_OFF 0x20 +#define SATA_SCR_STATUS 0 +#define SATA_SCR_ERROR 1 +#define SATA_SCR_CONTROL 2 +#define SATA_SCR_ACTIVE 3 +#define SATA_SCR_NOTIFICAION 4 + +#define SATA_BURST_BUF_FORCE_EOT_BIT 0 +#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT 1 +#define SATA_BURST_BUF_DIR_BIT 2 +#define SATA_BURST_BUF_DATA_INJ_END_BIT 3 +#define SATA_BURST_BUF_FIFO_DIS_BIT 4 +#define SATA_BURST_BUF_DIS_DREQ_BIT 5 +#define SATA_BURST_BUF_DREQ_BIT 6 + +#define SATA_OPCODE_MASK 0x3 + +#define SATA_DMA_CHANNEL 0 + +#define DMA_CTRL_STATUS (0x0) +#define DMA_BASE_SRC_ADR (0x4) +#define DMA_BASE_DST_ADR (0x8) +#define DMA_BYTE_CNT (0xC) +#define DMA_CURRENT_SRC_ADR (0x10) +#define DMA_CURRENT_DST_ADR (0x14) +#define DMA_CURRENT_BYTE_CNT (0x18) +#define DMA_INTR_ID (0x1C) +#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR) + +#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE + ((channel) << 5) + (register))) + +#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0) +#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1) +#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C) +#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2) +#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0) +#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6) +#define DMA_CTRL_STATUS_INTR (1 << 10) +#define DMA_CTRL_STATUS_NXT_FREE (1 << 11) +#define DMA_CTRL_STATUS_RESET (1 << 12) +#define DMA_CTRL_STATUS_DIR_MASK (0x00006000) +#define DMA_CTRL_STATUS_DIR_SHIFT (13) +#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15) +#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16) +#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17) +#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18) +#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000) +#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19) +#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000) +#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22) +#define DMA_CTRL_STATUS_PAUSE (1 << 25) +#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26) +#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27) +#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28) +#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29) +#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30) + +#define DMA_BYTE_CNT_MASK ((1 << 21) - 1) +#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30) +#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31) +#define DMA_BYTE_CNT_BURST_MASK (1 << 28) + +#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num)) + +typedef enum oxnas_dma_mode { + OXNAS_DMA_MODE_FIXED, OXNAS_DMA_MODE_INC +} oxnas_dma_mode_t; + +typedef enum oxnas_dma_direction { + OXNAS_DMA_TO_DEVICE, OXNAS_DMA_FROM_DEVICE +} oxnas_dma_direction_t; + +/* The available buses to which the DMA controller is attached */ +typedef enum oxnas_dma_transfer_bus { + OXNAS_DMA_SIDE_A, OXNAS_DMA_SIDE_B +} oxnas_dma_transfer_bus_t; + +/* Direction of data flow between the DMA controller's pair of interfaces */ +typedef enum oxnas_dma_transfer_direction { + OXNAS_DMA_A_TO_A, OXNAS_DMA_B_TO_A, OXNAS_DMA_A_TO_B, OXNAS_DMA_B_TO_B +} oxnas_dma_transfer_direction_t; + +/* The available data widths */ +typedef enum oxnas_dma_transfer_width { + OXNAS_DMA_TRANSFER_WIDTH_8BITS, + OXNAS_DMA_TRANSFER_WIDTH_16BITS, + OXNAS_DMA_TRANSFER_WIDTH_32BITS +} oxnas_dma_transfer_width_t; + +/* The mode of the DMA transfer */ +typedef enum oxnas_dma_transfer_mode { + OXNAS_DMA_TRANSFER_MODE_SINGLE, OXNAS_DMA_TRANSFER_MODE_BURST +} oxnas_dma_transfer_mode_t; + +/* The available transfer targets */ +typedef enum oxnas_dma_dreq { + OXNAS_DMA_DREQ_SATA = 0, OXNAS_DMA_DREQ_MEMORY = 15 +} oxnas_dma_dreq_t; + +typedef struct oxnas_dma_device_settings { + unsigned long address_; + unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer + unsigned char dreq_; + unsigned read_eot_ :1; + unsigned read_final_eot_ :1; + unsigned write_eot_ :1; + unsigned write_final_eot_ :1; + unsigned bus_ :1; + unsigned width_ :2; + unsigned transfer_mode_ :1; + unsigned address_mode_ :1; + unsigned address_really_fixed_ :1; +} oxnas_dma_device_settings_t; + +static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */ +static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */ +static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */ +static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */ +static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */ +static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */ + +/* The internal SATA drive on which we should attempt to find partitions */ +static volatile u32* sata_regs_base[2] = { (volatile u32*) SATA_0_REGS_BASE, + (volatile u32*) SATA_1_REGS_BASE, + +}; +static u32 wr_sata_orb1[2] = { 0, 0 }; +static u32 wr_sata_orb2[2] = { 0, 0 }; +static u32 wr_sata_orb3[2] = { 0, 0 }; +static u32 wr_sata_orb4[2] = { 0, 0 }; + +#ifdef CONFIG_LBA48 +/* need keeping a record of NSECT LBAL LBAM LBAH ide_outb values for lba48 support */ +#define OUT_HISTORY_BASE ATA_PORT_NSECT +#define OUT_HISTORY_MAX ATA_PORT_LBAH +static unsigned char out_history[2][OUT_HISTORY_MAX - OUT_HISTORY_BASE + 1] = {}; +#endif + +static oxnas_dma_device_settings_t oxnas_sata_dma_settings = { .address_ = + SATA_DATA_BASE, .fifo_size_ = 16, .dreq_ = OXNAS_DMA_DREQ_SATA, + .read_eot_ = 0, .read_final_eot_ = 1, .write_eot_ = 0, + .write_final_eot_ = 1, .bus_ = OXNAS_DMA_SIDE_B, .width_ = + OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ = + OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ = + OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 0 }; + +oxnas_dma_device_settings_t oxnas_ram_dma_settings = { .address_ = 0, + .fifo_size_ = 0, .dreq_ = OXNAS_DMA_DREQ_MEMORY, .read_eot_ = 1, + .read_final_eot_ = 1, .write_eot_ = 1, .write_final_eot_ = 1, + .bus_ = OXNAS_DMA_SIDE_A, .width_ = + OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ = + OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ = + OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 1 }; + +static void xfer_wr_shadow_to_orbs(int device) +{ + *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device]; + *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device]; + *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device]; + *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device]; +} + +static inline void device_select(int device) +{ + /* master/slave has no meaning to SATA core */ +} + +static int disk_present[CONFIG_SYS_IDE_MAXDEVICE]; + +#include <ata.h> + +unsigned char ide_inb(int device, int port) +{ + unsigned char val = 0; + + /* Only permit accesses to disks found to be present during ide_preinit() */ + if (!disk_present[device]) { + return ATA_STAT_FAULT; + } + + device_select(device); + + switch (port) { + case ATA_PORT_CTL: + val = (*(sata_regs_base[device] + SATA_ORB4_OFF) + & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT; + break; + case ATA_PORT_FEATURE: + val = (*(sata_regs_base[device] + SATA_ORB2_OFF) + & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT; + break; + case ATA_PORT_NSECT: + val = (*(sata_regs_base[device] + SATA_ORB2_OFF) + & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT; + break; + case ATA_PORT_LBAL: + val = (*(sata_regs_base[device] + SATA_ORB3_OFF) + & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT; + break; + case ATA_PORT_LBAM: + val = (*(sata_regs_base[device] + SATA_ORB3_OFF) + & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT; + break; + case ATA_PORT_LBAH: + val = (*(sata_regs_base[device] + SATA_ORB3_OFF) + & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT; + break; + case ATA_PORT_DEVICE: + val = (*(sata_regs_base[device] + SATA_ORB3_OFF) + & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT; + val |= (*(sata_regs_base[device] + SATA_ORB1_OFF) + & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT; + break; + case ATA_PORT_COMMAND: + val = (*(sata_regs_base[device] + SATA_ORB2_OFF) + & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT; + val |= ATA_STAT_DRQ; + break; + default: + printf("ide_inb() Unknown port = %d\n", port); + break; + } + + // printf("inb: %d:%01x => %02x\n", device, port, val); + + return val; +} + +/** + * Possible that ATA status will not become no-error, so must have timeout + * @returns An int which is zero on error + */ +static inline int wait_no_error(int device) +{ + int status = 0; + + /* Check for ATA core error */ + if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF) + & (1 << SATA_INT_STATUS_ERROR_BIT)) { + printf("wait_no_error() SATA core flagged error\n"); + } else { + int loops = MAX_NO_ERROR_LOOPS; + do { + /* Check for ATA device error */ + if (!(ide_inb(device, ATA_PORT_COMMAND) + & (1 << ATA_STATUS_ERR_BIT))) { + status = 1; + break; + } + udelay(10); + } while (--loops); + + if (!loops) { + printf("wait_no_error() Timed out of wait for SATA no-error condition\n"); + } + } + + return status; +} + +/** + * Expect SATA command to always finish, perhaps with error + * @returns An int which is zero on error + */ +static inline int wait_sata_command_not_busy(int device) +{ + /* Wait for data to be available */ + int status = 0; + int loops = MAX_NOT_BUSY_LOOPS; + do { + if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF) + & (1 << SATA_CMD_BUSY_BIT))) { + status = 1; + break; + } + udelay(100); + } while (--loops); + + if (!loops) { + printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n"); + } + + return status; +} + +void ide_outb(int device, int port, unsigned char val) +{ + typedef enum send_method { + SEND_NONE, SEND_SIMPLE, SEND_CMD, SEND_CTL, + } send_method_t; + + /* Only permit accesses to disks found to be present during ide_preinit() */ + if (!disk_present[device]) { + return; + } + + // printf("outb: %d:%01x <= %02x\n", device, port, val); + + device_select(device); + +#ifdef CONFIG_LBA48 + if (port >= OUT_HISTORY_BASE && port <= OUT_HISTORY_MAX) { + out_history[0][port - OUT_HISTORY_BASE] = + out_history[1][port - OUT_HISTORY_BASE]; + out_history[1][port - OUT_HISTORY_BASE] = val; + } +#endif + send_method_t send_regs = SEND_NONE; + switch (port) { + case ATA_PORT_CTL: + wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT); + wr_sata_orb4[device] |= (val << SATA_CTL_BIT); + send_regs = SEND_CTL; + break; + case ATA_PORT_FEATURE: + wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT); + wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT); + send_regs = SEND_SIMPLE; + break; + case ATA_PORT_NSECT: + wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT); + wr_sata_orb2[device] |= (val << SATA_NSECT_BIT); + send_regs = SEND_SIMPLE; + break; + case ATA_PORT_LBAL: + wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT); + wr_sata_orb3[device] |= (val << SATA_LBAL_BIT); + send_regs = SEND_SIMPLE; + break; + case ATA_PORT_LBAM: + wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT); + wr_sata_orb3[device] |= (val << SATA_LBAM_BIT); + send_regs = SEND_SIMPLE; + break; + case ATA_PORT_LBAH: + wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT); + wr_sata_orb3[device] |= (val << SATA_LBAH_BIT); + send_regs = SEND_SIMPLE; + break; + case ATA_PORT_DEVICE: + wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT); + wr_sata_orb1[device] |= (val << SATA_DEVICE_BIT); + send_regs = SEND_SIMPLE; + break; + case ATA_PORT_COMMAND: + wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT); + wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT); + send_regs = SEND_CMD; +#ifdef CONFIG_LBA48 + if (val == ATA_CMD_READ_EXT || val == ATA_CMD_WRITE_EXT) + { + /* fill high bytes of LBA48 && NSECT */ + wr_sata_orb2[device] &= ~(0xFFUL << SATA_HOB_NSECT_BIT); + wr_sata_orb2[device] |= + (out_history[0][ATA_PORT_NSECT - OUT_HISTORY_BASE] << SATA_HOB_NSECT_BIT); + + wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT); + wr_sata_orb3[device] |= + (out_history[0][ATA_PORT_LBAL - OUT_HISTORY_BASE] << SATA_HOB_LBAH_BIT); + + wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA32_BIT); + wr_sata_orb4[device] |= + (out_history[0][ATA_PORT_LBAM - OUT_HISTORY_BASE] << SATA_LBA32_BIT); + + wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA40_BIT); + wr_sata_orb4[device] |= + (out_history[0][ATA_PORT_LBAH - OUT_HISTORY_BASE] << SATA_LBA40_BIT); + } +#endif + break; + default: + printf("ide_outb() Unknown port = %d\n", port); + } + + u32 command; + switch (send_regs) { + case SEND_CMD: + wait_sata_command_not_busy(device); + command = *(sata_regs_base[device] + SATA_COMMAND_OFF); + command &= ~SATA_OPCODE_MASK; + command |= SATA_CMD_WRITE_TO_ORB_REGS; + xfer_wr_shadow_to_orbs(device); + wait_sata_command_not_busy(device); + *(sata_regs_base[device] + SATA_COMMAND_OFF) = command; + if (!wait_no_error(device)) { + printf("ide_outb() Wait for ATA no-error timed-out\n"); + } + break; + case SEND_CTL: + wait_sata_command_not_busy(device); + command = *(sata_regs_base[device] + SATA_COMMAND_OFF); + command &= ~SATA_OPCODE_MASK; + command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND; + xfer_wr_shadow_to_orbs(device); + wait_sata_command_not_busy(device); + *(sata_regs_base[device] + SATA_COMMAND_OFF) = command; + if (!wait_no_error(device)) { + printf("ide_outb() Wait for ATA no-error timed-out\n"); + } + break; + default: + break; + } +} + +static u32 encode_start(u32 ctrl_status) +{ + return ctrl_status & ~DMA_CTRL_STATUS_PAUSE; +} + +/* start a paused DMA transfer in channel 0 of the SATA DMA core */ +static void dma_start(void) +{ + unsigned int reg; + reg = readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS); + reg = encode_start(reg); + writel(reg, SATA_DMA_REGS_BASE + DMA_CTRL_STATUS); +} + +static unsigned long encode_control_status( + oxnas_dma_device_settings_t* src_settings, + oxnas_dma_device_settings_t* dst_settings) +{ + unsigned long ctrl_status; + oxnas_dma_transfer_direction_t direction; + + ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused + ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority + ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq + ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq + ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET + + // Use new interrupt clearing register + ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE; + + // Setup the transfer direction and burst/single mode for the two DMA busses + if (src_settings->bus_ == OXNAS_DMA_SIDE_A) { + // Set the burst/single mode for bus A based on src device's settings + if (src_settings->transfer_mode_ + == OXNAS_DMA_TRANSFER_MODE_BURST) { + ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A; + } else { + ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A; + } + + if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) { + direction = OXNAS_DMA_A_TO_A; + } else { + direction = OXNAS_DMA_A_TO_B; + + // Set the burst/single mode for bus B based on dst device's settings + if (dst_settings->transfer_mode_ + == OXNAS_DMA_TRANSFER_MODE_BURST) { + ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B; + } else { + ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B; + } + } + } else { + // Set the burst/single mode for bus B based on src device's settings + if (src_settings->transfer_mode_ + == OXNAS_DMA_TRANSFER_MODE_BURST) { + ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B; + } else { + ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B; + } + + if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) { + direction = OXNAS_DMA_B_TO_A; + + // Set the burst/single mode for bus A based on dst device's settings + if (dst_settings->transfer_mode_ + == OXNAS_DMA_TRANSFER_MODE_BURST) { + ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A; + } else { + ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A; + } + } else { + direction = OXNAS_DMA_B_TO_B; + } + } + ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT); + + // Setup source address mode fixed or increment + if (src_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) { + // Fixed address + ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE); + + // Set up whether fixed address is _really_ fixed + if (src_settings->address_really_fixed_) { + ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; + } else { + ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; + } + } else { + // Incrementing address + ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE; + ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED; + } + + // Setup destination address mode fixed or increment + if (dst_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) { + // Fixed address + ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE); + + // Set up whether fixed address is _really_ fixed + if (dst_settings->address_really_fixed_) { + ctrl_status |= + DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; + } else { + ctrl_status &= + ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; + } + } else { + // Incrementing address + ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE; + ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED; + } + + // Set up the width of the transfers on the DMA buses + ctrl_status |= + (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT); + ctrl_status |= + (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT); + + // Setup the priority arbitration scheme + ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority + + return ctrl_status; +} + +static u32 encode_final_eot(oxnas_dma_device_settings_t* src_settings, + oxnas_dma_device_settings_t* dst_settings, + unsigned long length) +{ + // Write the length, with EOT configuration for a final transfer + unsigned long encoded = length; + if (dst_settings->write_final_eot_) { + encoded |= DMA_BYTE_CNT_WR_EOT_MASK; + } else { + encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK; + } + if (src_settings->read_final_eot_) { + encoded |= DMA_BYTE_CNT_RD_EOT_MASK; + } else { + encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK; + } + /* if((src_settings->transfer_mode_) || + (src_settings->transfer_mode_)) { + encoded |= DMA_BYTE_CNT_BURST_MASK; + } else { + encoded &= ~DMA_BYTE_CNT_BURST_MASK; + }*/ + return encoded; +} + +static void dma_start_write(const ulong* buffer, int num_bytes) +{ + // Assemble complete memory settings + oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings; + mem_settings.address_ = (unsigned long) buffer; + mem_settings.address_mode_ = OXNAS_DMA_MODE_INC; + + writel(encode_control_status(&mem_settings, &oxnas_sata_dma_settings), + SATA_DMA_REGS_BASE + DMA_CTRL_STATUS); + writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR); + writel(oxnas_sata_dma_settings.address_, + SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR); + writel(encode_final_eot(&mem_settings, &oxnas_sata_dma_settings, + num_bytes), + SATA_DMA_REGS_BASE + DMA_BYTE_CNT); + + dma_start(); +} + +static void dma_start_read(ulong* buffer, int num_bytes) +{ + // Assemble complete memory settings + oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings; + mem_settings.address_ = (unsigned long) buffer; + mem_settings.address_mode_ = OXNAS_DMA_MODE_INC; + + writel(encode_control_status(&oxnas_sata_dma_settings, &mem_settings), + SATA_DMA_REGS_BASE + DMA_CTRL_STATUS); + writel(oxnas_sata_dma_settings.address_, + SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR); + writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR); + writel(encode_final_eot(&oxnas_sata_dma_settings, &mem_settings, + num_bytes), + SATA_DMA_REGS_BASE + DMA_BYTE_CNT); + + dma_start(); +} + +static inline int dma_busy(void) +{ + return readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS) + & DMA_CTRL_STATUS_IN_PROGRESS; +} + +static int wait_dma_not_busy(int device) +{ + unsigned int cleanup_required = 0; + + /* Poll for DMA completion */ + int loops = MAX_DMA_XFER_LOOPS; + do { + if (!dma_busy()) { + break; + } + udelay(100); + } while (--loops); + + if (!loops) { + printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n"); + cleanup_required = 1; + } + + if (cleanup_required) { + /* Abort DMA to make sure it has finished. */ + unsigned int ctrl_status = readl( + SATA_DMA_CHANNEL + DMA_CTRL_STATUS); + ctrl_status |= DMA_CTRL_STATUS_RESET; + writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS); + + // Wait for the channel to become idle - should be quick as should + // finish after the next AHB single or burst transfer + loops = MAX_DMA_ABORT_LOOPS; + do { + if (!dma_busy()) { + break; + } + udelay(10); + } while (--loops); + + if (!loops) { + printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n"); + } else { + /* Successfully cleanup the DMA channel */ + cleanup_required = 0; + } + + // Deassert reset for the channel + ctrl_status = readl(SATA_DMA_CHANNEL + DMA_CTRL_STATUS); + ctrl_status &= ~DMA_CTRL_STATUS_RESET; + writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS); + } + + return !cleanup_required; +} + +/** + * Possible that ATA status will not become not-busy, so must have timeout + */ +static unsigned int wait_not_busy(int device, unsigned long timeout_secs) +{ + int busy = 1; + unsigned long loops = (timeout_secs * 1000) / 50; + do { + // Test the ATA status register BUSY flag + if (!((*(sata_regs_base[device] + SATA_ORB2_OFF) + >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) { + /* Not busy, so stop polling */ + busy = 0; + break; + } + + // Wait for 50mS before sampling ATA status register again + udelay(50000); + } while (--loops); + + return busy; +} + +void ide_output_data(int device, const ulong *sect_buf, int words) +{ + /* Only permit accesses to disks found to be present during ide_preinit() */ + if (!disk_present[device]) { + return; + } + + /* Select the required internal SATA drive */ + device_select(device); + + /* Start the DMA channel sending data from the passed buffer to the SATA core */ + dma_start_write(sect_buf, words << 2); + + /* Don't know why we need this delay, but without it the wait for DMA not + busy times soemtimes out, e.g. when saving environment to second disk */ + udelay(1000); + + /* Wait for DMA to finish */ + if (!wait_dma_not_busy(device)) { + printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", + device); + } + + /* Sata core should finish after DMA */ + if (wait_not_busy(device, 30)) { + printf("Timed out of wait for SATA device %d to have BUSY clear\n", + device); + } + if (!wait_no_error(device)) { + printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n"); + } +} + + +#define SATA_DM_DBG1 (SATA_HOST_REGS_BASE + 0) +#define SATA_DATACOUNT_PORT0 (SATA_HOST_REGS_BASE + 0x10) +#define SATA_DATACOUNT_PORT1 (SATA_HOST_REGS_BASE + 0x14) +#define SATA_DATA_MUX_RAM0 (SATA_HOST_REGS_BASE + 0x8000) +#define SATA_DATA_MUX_RAM1 (SATA_HOST_REGS_BASE + 0xA000) +/* Sata core debug1 register bits */ +#define SATA_CORE_PORT0_DATA_DIR_BIT 20 +#define SATA_CORE_PORT1_DATA_DIR_BIT 21 +#define SATA_CORE_PORT0_DATA_DIR (1 << SATA_CORE_PORT0_DATA_DIR_BIT) +#define SATA_CORE_PORT1_DATA_DIR (1 << SATA_CORE_PORT1_DATA_DIR_BIT) + +/** + * Ref bug-6320 + * + * This code is a work around for a DMA hardware bug that will repeat the + * penultimate 8-bytes on some reads. This code will check that the amount + * of data transferred is a multiple of 512 bytes, if not the in it will + * fetch the correct data from a buffer in the SATA core and copy it into + * memory. + * + */ +static void sata_bug_6320_workaround(int port, ulong *candidate) +{ + int is_read; + int quads_transferred; + int remainder; + int sector_quads_remaining; + + /* Only want to apply fix to reads */ + is_read = !(*((unsigned long*) SATA_DM_DBG1) + & (port ? SATA_CORE_PORT1_DATA_DIR : SATA_CORE_PORT0_DATA_DIR)); + + /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes + transferred (datacount_port register counts quads transferred) */ + quads_transferred = *((unsigned long*) ( + port ? SATA_DATACOUNT_PORT1 : SATA_DATACOUNT_PORT0)); + + remainder = quads_transferred & 0x7f; + sector_quads_remaining = remainder ? (0x80 - remainder) : 0; + + if (is_read && (sector_quads_remaining == 2)) { + debug("SATA read fixup, only transfered %d quads, " + "sector_quads_remaining %d, port %d\n", + quads_transferred, sector_quads_remaining, port); + + int total_len = ATA_SECT_SIZE; + ulong *sata_data_ptr = (void*) ( + port ? SATA_DATA_MUX_RAM1 : SATA_DATA_MUX_RAM0) + + ((total_len - 8) % 2048); + + *candidate = *sata_data_ptr; + *(candidate + 1) = *(sata_data_ptr + 1); + } +} + + +void ide_input_data(int device, ulong *sect_buf, int words) +{ + /* Only permit accesses to disks found to be present during ide_preinit() */ + if (!disk_present[device]) { + return; + } + + /* Select the required internal SATA drive */ + device_select(device); + + /* Start the DMA channel receiving data from the SATA core into the passed buffer */ + dma_start_read(sect_buf, words << 2); + + /* Sata core should finish before DMA */ + if (wait_not_busy(device, 30)) { + printf("Timed out of wait for SATA device %d to have BUSY clear\n", + device); + } + if (!wait_no_error(device)) { + printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n"); + } + + /* Wait for DMA to finish */ + if (!wait_dma_not_busy(device)) { + printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", + device); + } + + if (words == ATA_SECTORWORDS) + sata_bug_6320_workaround(device, sect_buf + words - 2); +} + +static u32 scr_read(int device, unsigned int sc_reg) +{ + /* Setup adr of required register. std regs start eight into async region */ + *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg + * 4+ SATA_STD_ASYNC_REGS_OFF; + + /* Wait for data to be available */ + int loops = MAX_SRC_READ_LOOPS; + do { + if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) { + break; + } + udelay(10); + } while (--loops); + + if (!loops) { + printf("scr_read() Timed out of wait for read completion\n"); + } + + /* Read the data from the async register */ + return *(sata_regs_base[device] + SATA_LINK_DATA); +} + +static void scr_write(int device, unsigned int sc_reg, u32 val) +{ + /* Setup the data for the write */ + *(sata_regs_base[device] + SATA_LINK_DATA) = val; + + /* Setup adr of required register. std regs start eight into async region */ + *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg + * 4+ SATA_STD_ASYNC_REGS_OFF; + + /* Wait for data to be written */ + int loops = MAX_SRC_WRITE_LOOPS; + do { + if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) { + break; + } + udelay(10); + } while (--loops); + + if (!loops) { + printf("scr_write() Timed out of wait for write completion\n"); + } +} +extern void workaround5458(void); + +#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */ +#define LOS_AND_TX_LVL 0x2988 +#define TX_ATTEN 0x55629 + +static int phy_reset(int device) +{ + int phy_status = 0; + int loops = 0; + + scr_write(device, (0x60 - SATA_STD_ASYNC_REGS_OFF) / 4, LOS_AND_TX_LVL); + scr_write(device, (0x70 - SATA_STD_ASYNC_REGS_OFF) / 4, TX_ATTEN); + + /* limit it to Gen-1 SATA (1.5G) */ + scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */ + scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */ + udelay(1000); + scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */ + + /* Wait for upto 5 seconds for PHY to become ready */ + do { + udelay(200000); + if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 3) { + scr_write(device, SATA_SCR_ERROR, ~0); + phy_status = 1; + break; + } + //printf("No SATA PHY found status:0x%x\n", scr_read(device, SATA_SCR_STATUS)); + } while (++loops < PHY_LOOP_COUNT); + + if (phy_status) { + udelay(500000); /* wait half a second */ + } + + return phy_status; +} + +#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */ +static int wait_FIS(int device) +{ + int status = 0; + int loops = 0; + + do { + udelay(200000); + if (ide_inb(device, ATA_PORT_NSECT) > 0) { + status = 1; + break; + } + } while (++loops < FIS_LOOP_COUNT); + + return status; +} + + +#define SATA_PHY_ASIC_STAT (0x44900000) +#define SATA_PHY_ASIC_DATA (0x44900004) + +/** + * initialise functions and macros for ASIC implementation + */ +#define PH_GAIN 2 +#define FR_GAIN 3 +#define PH_GAIN_OFFSET 6 +#define FR_GAIN_OFFSET 8 +#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET) +#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET) +#define USE_INT_SETTING (1<<5) + +#define CR_READ_ENABLE (1<<16) +#define CR_WRITE_ENABLE (1<<17) +#define CR_CAP_DATA (1<<18) + +static void wait_cr_ack(void) +{ + while ((readl(SATA_PHY_ASIC_STAT) >> 16) & 0x1f) + /* wait for an ack bit to be set */; +} + +static unsigned short read_cr(unsigned short address) +{ + writel(address, SATA_PHY_ASIC_STAT); + wait_cr_ack(); + writel(CR_READ_ENABLE, SATA_PHY_ASIC_DATA); + wait_cr_ack(); + return readl(SATA_PHY_ASIC_STAT); +} + +static void write_cr(unsigned short data, unsigned short address) +{ + writel(address, SATA_PHY_ASIC_STAT); + wait_cr_ack(); + writel((data | CR_CAP_DATA), SATA_PHY_ASIC_DATA); + wait_cr_ack(); + writel(CR_WRITE_ENABLE, SATA_PHY_ASIC_DATA); + wait_cr_ack(); + return; +} + +void workaround5458(void) +{ + unsigned i; + + for (i = 0; i < 2; i++) { + unsigned short rx_control = read_cr(0x201d + (i << 8)); + rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK); + rx_control |= PH_GAIN << PH_GAIN_OFFSET; + rx_control |= FR_GAIN << FR_GAIN_OFFSET; + rx_control |= USE_INT_SETTING; + write_cr(rx_control, 0x201d + (i << 8)); + } +} + +int ide_preinit(void) +{ + int num_disks_found = 0; + + /* Initialise records of which disks are present to all present */ + int i; + for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) { + disk_present[i] = 1; + } + + /* Block reset SATA and DMA cores */ + reset_block(SYS_CTRL_RST_SATA, 1); + reset_block(SYS_CTRL_RST_SATA_LINK, 1); + reset_block(SYS_CTRL_RST_SATA_PHY, 1); + reset_block(SYS_CTRL_RST_SGDMA, 1); + + /* Enable clocks to SATA and DMA cores */ + enable_clock(SYS_CTRL_CLK_SATA); + enable_clock(SYS_CTRL_CLK_DMA); + + udelay(5000); + reset_block(SYS_CTRL_RST_SATA_PHY, 0); + udelay(50); + reset_block(SYS_CTRL_RST_SATA, 0); + reset_block(SYS_CTRL_RST_SATA_LINK, 0); + udelay(50); + reset_block(SYS_CTRL_RST_SGDMA, 0); + udelay(100); + /* Apply the Synopsis SATA PHY workarounds */ + workaround5458(); + udelay(10000); + + /* disable and clear core interrupts */ + *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) = + ~0UL; + *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL; + + int device; + for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) { + int found = 0; + int retries = 1; + + /* Disable SATA interrupts */ + *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL; + + /* Clear any pending SATA interrupts */ + *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL; + + do { + /* clear sector count register for FIS detection */ + ide_outb(device, ATA_PORT_NSECT, 0); + + /* Get the PHY working */ + if (!phy_reset(device)) { + printf("SATA PHY not ready for device %d\n", + device); + break; + } + + if (!wait_FIS(device)) { + printf("No FIS received from device %d\n", + device); + } else { + if ((scr_read(device, SATA_SCR_STATUS) & 0xf) + == 0x3) { + if (wait_not_busy(device, 30)) { + printf("Timed out of wait for SATA device %d to have BUSY clear\n", + device); + } else { + ++num_disks_found; + found = 1; + } + } else { + printf("No SATA device %d found, PHY status = 0x%08x\n", + device, + scr_read( + device, + SATA_SCR_STATUS)); + } + break; + } + } while (retries--); + + /* Record whether disk is present, so won't attempt to access it later */ + disk_present[device] = found; + } + + /* post disk detection clean-up */ + for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) { + if (disk_present[device]) { + /* set as ata-5 (28-bit) */ + *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) = + 0UL; + + /* clear phy/link errors */ + scr_write(device, SATA_SCR_ERROR, ~0); + + /* clear host errors */ + *(sata_regs_base[device] + SATA_CONTROL_OFF) |= + SATA_SCTL_CLR_ERR; + + /* clear interrupt register as this clears the error bit in the IDE + status register */ + *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL; + } + } + + return !num_disks_found; +} + diff --git a/package/boot/uboot-oxnas/files/drivers/usb/host/ehci-oxnas.c b/package/boot/uboot-oxnas/files/drivers/usb/host/ehci-oxnas.c new file mode 100644 index 0000000..6ab05c5 --- /dev/null +++ b/package/boot/uboot-oxnas/files/drivers/usb/host/ehci-oxnas.c @@ -0,0 +1,105 @@ +/* + * drivers/usb/host/ehci-oxnas.c + * + * Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sysctl.h> +#include <asm/arch/clock.h> + +#include "ehci.h" + +static struct ehci_hcor *ghcor; + +static int start_oxnas_usb_ehci(void) +{ +#ifdef CONFIG_USB_PLLB_CLK + reset_block(SYS_CTRL_RST_PLLB, 0); + enable_clock(SYS_CTRL_CLK_REF600); + + writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV), + SEC_CTRL_PLLB_CTRL0); + /* 600MHz pllb divider for 12MHz */ + writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), SEC_CTRL_PLLB_DIV_CTRL); +#else + /* ref 300 divider for 12MHz */ + writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), SYS_CTRL_REF300_DIV); +#endif + + /* Ensure the USB block is properly reset */ + reset_block(SYS_CTRL_RST_USBHS, 1); + reset_block(SYS_CTRL_RST_USBHS, 0); + + reset_block(SYS_CTRL_RST_USBHSPHYA, 1); + reset_block(SYS_CTRL_RST_USBHSPHYA, 0); + + reset_block(SYS_CTRL_RST_USBHSPHYB, 1); + reset_block(SYS_CTRL_RST_USBHSPHYB, 0); + + /* Force the high speed clock to be generated all the time, via serial + programming of the USB HS PHY */ + writel((2UL << USBHSPHY_TEST_ADD) | + (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + + writel((1UL << USBHSPHY_TEST_CLK) | + (2UL << USBHSPHY_TEST_ADD) | + (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + + writel((0xfUL << USBHSPHY_TEST_ADD) | + (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + + writel((1UL << USBHSPHY_TEST_CLK) | + (0xfUL << USBHSPHY_TEST_ADD) | + (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + +#ifdef CONFIG_USB_PLLB_CLK /* use pllb clock */ + writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL); +#else /* use ref300 derived clock */ + writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, SYS_CTRL_USB_CTRL); +#endif + /* Enable the clock to the USB block */ + enable_clock(SYS_CTRL_CLK_USBHS); + + return 0; +} +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + start_oxnas_usb_ehci(); + *hccr = (struct ehci_hccr *)(USB_HOST_BASE + 0x100); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + ghcor = *hcor; + return 0; +} + +int ehci_hcd_stop(int index) +{ + reset_block(SYS_CTRL_RST_USBHS, 1); + disable_clock(SYS_CTRL_CLK_USBHS); + return 0; +} + +extern void __ehci_set_usbmode(int index); +void ehci_set_usbmode(int index) +{ + #define or_txttfill_tuning _reserved_1_[0] + u32 tmp; + + __ehci_set_usbmode(index); + + tmp = ehci_readl(&ghcor->or_txfilltuning); + tmp &= ~0x00ff0000; + tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */ + tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/ + ehci_writel(&ghcor->or_txfilltuning, tmp); + + tmp = ehci_readl(&ghcor->or_txttfill_tuning); + tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */ + ehci_writel(&ghcor->or_txttfill_tuning, tmp); +} diff --git a/package/boot/uboot-oxnas/files/include/configs/ox820.h b/package/boot/uboot-oxnas/files/include/configs/ox820.h new file mode 100644 index 0000000..85ee3b4 --- /dev/null +++ b/package/boot/uboot-oxnas/files/include/configs/ox820.h @@ -0,0 +1,383 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_ARM1136 +#define CONFIG_OX820 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +/* make cmd_ide.c quiet when compile */ +#define __io + +/*#define CONFIG_ARCH_CPU_INIT*/ +/*#define CONFIG_DISPLAY_CPUINFO*/ +/*#define CONFIG_DISPLAY_BOARDINFO*/ +/*#define CONFIG_BOARD_EARLY_INIT_F*/ +/*#define CONFIG_SKIP_LOWLEVEL_INIT*/ + +/* mem */ +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MIN_SDRAM_SIZE (128 * 1024 * 1024) /* 128 MB */ +#define CONFIG_MAX_SDRAM_SIZE (512 * 1024 * 1024) /* 512 MB */ +#define CONFIG_SRAM_BASE 0x50000000 +#define CONFIG_SRAM_SIZE (64 * 1024) + +/* need do dma so better keep dcache off */ +#define CONFIG_SYS_DCACHE_OFF + +/* clock */ +#define CONFIG_PLLA_FREQ_MHZ 800 +#define CONFIG_RPSCLK 6250000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK_FREQ CONFIG_RPSCLK +#define CONFIG_SYS_TIMERBASE TIMER1_BASE +#define CONFIG_TIMER_PRESCALE TIMER_PRESCALE_16 + +/* serial */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK CONFIG_RPSCLK +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_NS16550_COM1 UART_1_BASE +#define CONFIG_CONS_INDEX 1 + +/* ide */ +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_IDE_PLX +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_IDE_PREINIT +#define CONFIG_LBA48 + +/* nand */ +#define CONFIG_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE STATIC_CS0_BASE +#define NAND_CLE_ADDR_PIN 19 +#define NAND_ALE_ADDR_PIN 18 +#define MTDPARTS_DEFAULT "mtdparts=41000000.nand:" \ + "14m(boot)," \ + "-(ubi)" +#define MTDIDS_DEFAULT "nand0=41000000.nand" +#define UBIPART_DEFAULT "ubi" + +/* net */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_ICPLUS + +/* spl */ +#ifdef CONFIG_SPL_BUILD +#define USE_DL_PREFIX /* rename malloc free etc, so we can override them */ +#endif + +#if defined(CONFIG_BOOT_FROM_NAND) || defined(CONFIG_BOOT_FROM_SATA) +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0x50000000 +#define CONFIG_SPL_STACK (CONFIG_SRAM_BASE + (48 * 1024)) +#define CONFIG_SPL_DISPLAY_PRINT +#define CONFIG_SPL_BSS_DRAM_START 0x65000000 +#define CONFIG_SPL_BSS_DRAM_SIZE 0x01000000 +#define CONFIG_SPL_MALLOC_START 0x66000000 +#endif + +#if defined(CONFIG_BOOT_FROM_NAND) +#define CONFIG_SPL_NAND_SUPPORT +#define BOOT_DEVICE_TYPE "NAND" +#define BOOT_DEVICE_NAND 0xfeedbacc +#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_NAND +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 6 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +/* pages per erase block */ +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE) +/* nand spl use 1 erase block, and use bit to byte encode for reliability */ +#define CONFIG_SPL_MAX_SIZE (128 * 1024 / 8) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 +/* spl kernel load is not enabled */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 +#define CONFIG_CMD_SPL_NAND_OFS 0 +#define CONFIG_CMD_SPL_WRITE_SIZE 1024 +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) +/* CONFIG_BOOT_FROM_NAND end */ + +#elif defined(CONFIG_BOOT_FROM_SATA) +#define CONFIG_SPL_BLOCK_SUPPORT +#define BOOT_DEVICE_TYPE "SATA" +#define BOOT_DEVICE_BLOCK 860202 +#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_BLOCK +#define CONFIG_SPL_MAX_SIZE (36 * 1024) +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_BLOCKDEV_INTERFACE "ide" +#define CONFIG_SPL_BLOCKDEV_ID 0 + +#ifdef CONFIG_BOOT_FROM_FAT /* u-boot in fat partition */ + +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_BLOCKDEV_FAT_BOOT_PARTITION 1 /* first partition */ +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* u-boot file name */ +/* enable U-Boot Falcon Mode */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "bootargs.bin" /* boot parameters */ +#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "falcon.img" /* kernel */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +#elif CONFIG_BOOT_FROM_EXT4 + +#define CONFIG_SPL_EXT4_SUPPORT +#define CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION 1 /* first partition */ +#define CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME "/boot/u-boot.img" /* u-boot file name */ +/* enable U-Boot Falcon Mode */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_EXT4_LOAD_ARGS_NAME "/boot/bootargs.bin" /* boot parameters */ +#define CONFIG_SPL_EXT4_LOAD_KERNEL_NAME "/boot/falcon.img" /* kernel */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +#else /* u-boot in raw sectors */ + +#define CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR 1024 +/* spl kernel load is not enabled */ +#define CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR 4096 +#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR 0 +#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS (1024 / 512) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +#endif /* CONFIG_BOOT_FROM_FAT */ +/* CONFIG_BOOT_FROM_SATA end */ + +#else +/* generic, no spl support */ +#endif + +/* boot */ +#define CONFIG_IDENT_STRING " for OXNAS" +#define CONFIG_MACH_TYPE MACH_TYPE_OXNAS +#ifndef CONFIG_SPL_BUILD +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT +#endif +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_DEFAULT_CONSOLE_PARM "console=ttyS0,115200n8 earlyprintk=serial" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE) +#define CONFIG_SYS_AUTOLOAD "no" + +#define CONFIG_DEFAULT_CONSOLE CONFIG_DEFAULT_CONSOLE_PARM "\0" +#define CONFIG_BOOTARGS CONFIG_DEFAULT_CONSOLE_PARM +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY 60 + +#define CONFIG_NETCONSOLE +#define CONFIG_IPADDR 192.168.50.100 +#define CONFIG_SERVERIP 192.168.50.59 + +/* A sane default configuration... + * When booting without a valid environment in ubi, first to loading and booting + * the kernel image directly above U-Boot, maybe both were loaded there by + * another bootloader. + * Also use that same offset (0x90000) to load the rescue image later on (by + * adding it onto the flash address where U-Boot is supposed to be stored by + * the legacy loader, 0x440000, resulting in offset 0x4d0000 on the flash). + * When coming up with a valid environment in ubi, first try to load the + * kernel from a ubi volume kernel, if that fails, fallback to the rescue + * image stored in boot partition. As a last resort try booting via + * DHCP/TFTP. + * In case there is no valid environment, first probe for a uimage in ram left + * behind by the first bootloader on a tftp boot. + * If that fails, switch to normal boot order and save environment. + * The loader is supposed to be written to flash at offset 0x440000 and loaded to + * RAM at 0x64000000 + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel_ubi=ubi readvol 0x62000000 kernel;\0" \ + "load_kernel_rescue=nand read 0x62000000 0x4e0000 0x400000;\0" \ + "load_kernel_dhcp=dhcp 0x62000000 oxnas-rescue.bin;\0" \ + "boot_kernel=bootm 0x62000000;\0" \ + "boot_ubi=run load_kernel_ubi && run boot_kernel;\0" \ + "boot_rescue=run load_kernel_rescue && run boot_kernel;\0" \ + "boot_dhcp=run load_kernel_dhcp && run boot_kernel;\0" \ + "normalboot=run boot_ubi; run boot_rescue; run boot_dhcp;\0" \ + "firstboot=bootm 0x640a0000; setenv bootcmd run normalboot; " \ + "setenv firstboot; saveenv; run bootcmd; \0" \ + "bootcmd=run firstboot; \0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "bootargs=" CONFIG_BOOTARGS "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + +/* env */ +#if defined(CONFIG_BOOT_FROM_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x000C0000 +#define CONFIG_ENV_SIZE 0x00020000 +#define CONFIG_ENV_OFFSET_REDUND 0x00100000 +#define CONFIG_ENV_SIZE_REDUND 0x00020000 +#define CONFIG_ENV_RANGE (CONFIG_ENV_SIZE * 2) +/* CONFIG_BOOT_FROM_NAND end */ + +#elif defined(CONFIG_BOOT_FROM_SATA) +#ifdef CONFIG_BOOT_FROM_EXT4 +#define CONFIG_ENV_IS_IN_EXT4 +#define CONFIG_START_IDE +#define EXT4_ENV_INTERFACE "ide" +#define EXT4_ENV_DEVICE 0 +#define EXT4_ENV_PART 1 +#define EXT4_ENV_FILE "/boot/u-boot.env" +#define CONFIG_ENV_SIZE (16 * 1024) +#else +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_START_IDE +#define FAT_ENV_INTERFACE "ide" +#define FAT_ENV_DEVICE 0 +#define FAT_ENV_PART 1 +#define FAT_ENV_FILE "u-boot.env" +#define CONFIG_ENV_SIZE (16 * 1024) +#endif +/* CONFIG_BOOT_FROM_SATA end */ +#elif defined(CONFIG_BOOT_FROM_SATA) + +#else +/* generic */ +#define CONFIG_ENV_IS_IN_UBI 1 +#define CONFIG_ENV_UBI_PART UBIPART_DEFAULT +#define CONFIG_ENV_UBI_VOLUME "ubootenv" +#define CONFIG_ENV_UBI_VOLUME_REDUND "ubootenv2" +#define CONFIG_ENV_SIZE (16 * 1024) +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_TEXT_BASE 0x64000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x65000000 +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "OX820 # " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size*/ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* usb */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_EHCI +#define CONFIG_EHCI_IS_TDI +/* #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x3F */ +#define CONFIG_USB_PLLB_CLK +#define CONFIG_USB_EHCI_OXNAS +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USB_STORAGE +#endif +#define CONFIG_CMD_USB + +/* cmds */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> + +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_ENV_FLAGS + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_PXE + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_EXT4_WRITE +#endif + +#define CONFIG_CMD_ZIP +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_TIME +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_HASH +#define CONFIG_CMD_INI +#define CONFIG_CMD_GETTIME +#define CONFIG_CMD_BOOTMENU +#define CONFIG_CMD_ELF + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* for CONFIG_CMD_MTDPARTS */ +#define CONFIG_MTD_DEVICE +/* for CONFIG_CMD_UBI */ +#define CONFIG_MTD_PARTITIONS +/* for CONFIG_CMD_UBI */ +#define CONFIG_RBTREE + +/* optional, for CONFIG_CMD_BOOTM & required by CONFIG_CMD_UBIFS */ +#define CONFIG_LZO +#define CONFIG_LZMA +#define CONFIG_BZIP2 + +/* for CONFIG_CMD_ZIP */ +#define CONFIG_GZIP_COMPRESSED +/* for CONFIG_CMD_MD5SUM */ +#define CONFIG_MD5 +#define CONFIG_MD5SUM_VERIFY +/* enable CONFIG_CMD_HASH's verification feature */ +#define CONFIG_HASH_VERIFY +#define CONFIG_REGEX +/* for CONFIG_CMD_BOOTMENU & CONFIG_CMD_PXE */ +#define CONFIG_MENU + +/* for new FIT uImage format generated in OpenWrt */ +#define CONFIG_FIT + +#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-oxnas/files/tools/mkox820crc.c b/package/boot/uboot-oxnas/files/tools/mkox820crc.c new file mode 100644 index 0000000..d100191 --- /dev/null +++ b/package/boot/uboot-oxnas/files/tools/mkox820crc.c @@ -0,0 +1,123 @@ +/* J J Larworthy 27 September 2006 */ + +/* file to read the boot sector of a dis and the loaded image and report + * if the boot rom would accept the data as intact and suitable for use + */ + +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/errno.h> + +#include <fcntl.h> +#include <unistd.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <assert.h> + +extern uint32_t crc32(uint32_t, const unsigned char *, unsigned int); + +#define NUMBER_VECTORS 12 +struct { + unsigned int start_vector[NUMBER_VECTORS]; + char code[4]; + unsigned int header_length; + unsigned int reserved[3]; + unsigned int length; + unsigned int img_CRC; + unsigned int CRC; +} img_header; + +void print_usage(void) +{ + printf("update_header file.bin\n"); +} + +void print_header(void) +{ + int i; + + printf("vectors in header\n"); + for (i = 0; i < NUMBER_VECTORS; i++) { + printf("%d:0x%08x\n", i, img_header.start_vector[i]); + } + printf("length:%8x\nimg_CRC:0x%08x\nHeader CRC:0x%08x\n", + img_header.length, img_header.img_CRC, img_header.CRC); +} + +int main(int argc, char **argv) +{ + int in_file; + int status; + int unsigned crc; + int file_length; + int len; + + struct stat file_stat; + + void *executable; + + in_file = open(argv[1], O_RDWR); + + if (in_file < 0) { + printf("failed to open file:%s\n", argv[optind]); + return -ENOENT; + } + + status = fstat(in_file, &file_stat); + + /* read header and obtain size of image */ + status = read(in_file, &img_header, sizeof(img_header)); + + file_length = file_stat.st_size - sizeof(img_header); + + if (img_header.length != file_length) { + printf("size in header:%d, size of file: %d\n", + img_header.length, file_length); + } + img_header.length = file_length; + + /* read working image and CRC */ + executable = malloc(file_length); + + status = read(in_file, executable, file_length); + + if (status != file_length) { + printf("Failed to load image\n"); + return -ENOENT; + } + + /* verify image CRC */ + crc = crc32(0, (const unsigned char *) executable, img_header.length); + + if (crc != img_header.img_CRC) { + printf("New Image CRC:0x%08x, hdr:0x%08x\n", crc, + img_header.img_CRC); + img_header.img_CRC = crc; + } + memcpy(img_header.code, "BOOT", 4); + img_header.header_length = sizeof(img_header); + + /* check header CRC */ + crc = crc32(0, (const unsigned char *) &img_header, + sizeof(img_header) - sizeof(unsigned int)); + if (crc != img_header.CRC) { + printf("New header CRC - crc:0x%08x hdr:0x%08x\n", crc, + img_header.CRC); + img_header.CRC = crc; + } + + /* re-write the file */ + status = lseek(in_file, 0, SEEK_SET); + if (status != 0) { + printf("failed to rewind\n"); + return 1; + } + len = write(in_file, &img_header, sizeof(img_header)); + assert(len == sizeof(img_header)); + len = write(in_file, executable, file_length); + assert(len == file_length); + close(in_file); + + return 0; +} |