diff options
Diffstat (limited to 'target/linux/sunxi/patches-4.1/126-3-dt-sun7i-add-nand-ctrlpin-defs.patch')
| -rw-r--r-- | target/linux/sunxi/patches-4.1/126-3-dt-sun7i-add-nand-ctrlpin-defs.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-4.1/126-3-dt-sun7i-add-nand-ctrlpin-defs.patch b/target/linux/sunxi/patches-4.1/126-3-dt-sun7i-add-nand-ctrlpin-defs.patch new file mode 100644 index 0000000..0f3dc61 --- /dev/null +++ b/target/linux/sunxi/patches-4.1/126-3-dt-sun7i-add-nand-ctrlpin-defs.patch @@ -0,0 +1,102 @@ +From 576701449b01fb0dfaa76bb71f2b94ab5194c1dc Mon Sep 17 00:00:00 2001 +From: Boris BREZILLON <boris.brezillon@free-electrons.com> +Date: Mon, 28 Jul 2014 14:08:15 +0200 +Subject: [PATCH] ARM: dts: sun7i: Add NAND controller pin definitions + +Define the NAND controller pin configs. + +Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> +Signed-off-by: Hans de Goede <hdegoede@redhat.com> +--- + arch/arm/boot/dts/sun7i-a20.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 80 insertions(+) + +--- a/arch/arm/boot/dts/sun7i-a20.dtsi ++++ b/arch/arm/boot/dts/sun7i-a20.dtsi +@@ -978,6 +978,86 @@ + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; ++ ++ nand_pins_a: nand_base0@0 { ++ allwinner,pins = "PC0", "PC1", "PC2", ++ "PC5", "PC8", "PC9", "PC10", ++ "PC11", "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs0_pins_a: nand_cs@0 { ++ allwinner,pins = "PC4"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs1_pins_a: nand_cs@1 { ++ allwinner,pins = "PC3"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs2_pins_a: nand_cs@2 { ++ allwinner,pins = "PC17"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs3_pins_a: nand_cs@3 { ++ allwinner,pins = "PC18"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs4_pins_a: nand_cs@4 { ++ allwinner,pins = "PC19"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs5_pins_a: nand_cs@5 { ++ allwinner,pins = "PC20"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs6_pins_a: nand_cs@6 { ++ allwinner,pins = "PC21"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_cs7_pins_a: nand_cs@7 { ++ allwinner,pins = "PC22"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_rb0_pins_a: nand_rb@0 { ++ allwinner,pins = "PC6"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ nand_rb1_pins_a: nand_rb@1 { ++ allwinner,pins = "PC7"; ++ allwinner,function = "nand0"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; + }; + + timer@01c20c00 { |