diff options
Diffstat (limited to 'target/linux/ramips/dts/mt7621.dtsi')
| -rw-r--r-- | target/linux/ramips/dts/mt7621.dtsi | 345 |
1 files changed, 345 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi new file mode 100644 index 0000000..fd2e100 --- /dev/null +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -0,0 +1,345 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mtk7621-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips1004Kc"; + }; + + cpu@1 { + compatible = "mips,mips1004Kc"; + }; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@1E000000 { + compatible = "palmbus"; + reg = <0x1E000000 0x100000>; + ranges = <0x0 0x1E000000 0x0FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "mtk,mt7621-sysc"; + reg = <0x0 0x100>; + }; + + wdt@100 { + compatible = "mtk,mt7621-wdt"; + reg = <0x100 0x100>; + }; + + gpio@600 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "mtk,mt7621-gpio"; + reg = <0x600 0x100>; + + gpio0: bank@0 { + reg = <0>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: bank@1 { + reg = <1>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: bank@2 { + reg = <2>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + memc@5000 { + compatible = "mtk,mt7621-memc"; + reg = <0x300 0x100>; + }; + + uartlite@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&gic>; + interrupts = <26>; + + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test; + }; + + spi@b00 { + status = "okay"; + + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x100>; + + resets = <&rstctrl 18>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0>; + spi-max-frequency = <10000000>; + m25p,chunked-io = <32>; + }; + }; + }; + + pinctrl { + compatible = "ralink,rt2880-pinmux"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinctrl0 { + }; + + spi_pins: spi { + spi { + ralink,group = "spi"; + ralink,function = "spi"; + }; + }; + + i2c_pins: i2c { + i2c { + ralink,group = "i2c"; + ralink,function = "i2c"; + }; + }; + + uart1_pins: uart1 { + uart1 { + ralink,group = "uart1"; + ralink,function = "uart1"; + }; + }; + + uart2_pins: uart2 { + uart2 { + ralink,group = "uart2"; + ralink,function = "uart2"; + }; + }; + + uart3_pins: uart3 { + uart3 { + ralink,group = "uart3"; + ralink,function = "uart3"; + }; + }; + + rgmii1_pins: rgmii1 { + rgmii1 { + ralink,group = "rgmii1"; + ralink,function = "rgmii1"; + }; + }; + + rgmii2_pins: rgmii2 { + rgmii2 { + ralink,group = "rgmii2"; + ralink,function = "rgmii2"; + }; + }; + + mdio_pins: mdio { + mdio { + ralink,group = "mdio"; + ralink,function = "mdio"; + }; + }; + + pcie_pins: pcie { + pcie { + ralink,group = "pcie"; + ralink,function = "pcie rst"; + }; + }; + + nand_pins: nand { + spi-nand { + ralink,group = "spi"; + ralink,function = "nand1"; + }; + + sdhci-nand { + ralink,group = "sdhci"; + ralink,function = "nand2"; + }; + }; + + sdhci_pins: sdhci { + sdhci { + ralink,group = "sdhci"; + ralink,function = "sdhci"; + }; + }; + }; + + rstctrl: rstctrl { + compatible = "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + sdhci@1E130000 { + compatible = "ralink,mt7620-sdhci"; + reg = <0x1E130000 4000>; + + interrupt-parent = <&gic>; + interrupts = <20>; + }; + + xhci@1E1C0000 { + status = "disabled"; + + compatible = "xhci-platform"; + reg = <0x1E1C0000 4000>; + + interrupt-parent = <&gic>; + interrupts = <22>; + }; + + gic: gic@1fbc0000 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "ralink,mt7621-gic"; + reg = < 0x1fbc0000 0x80 /* gic */ + 0x1fbf0000 0x8000 /* cpc */ + 0x1fbf8000 0x8000 /* gpmc */ + >; + }; + + nand@1e003000 { + compatible = "mtk,mt7621-nand"; + bank-width = <2>; + reg = <0x1e003000 0x800 + 0x1e003800 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x80000>; /* 64 KB */ + }; + + partition@80000 { + label = "uboot_env"; + reg = <0x80000 0x80000>; /* 64 KB */ + }; + + partition@100000 { + label = "factory"; + reg = <0x100000 0x40000>; + }; + + partition@140000 { + label = "rootfs"; + reg = <0x140000 0xec0000>; + }; + }; + + ethernet@1e100000 { + compatible = "ralink,mt7621-eth"; + reg = <0x1e100000 10000>; + + #address-cells = <1>; + #size-cells = <0>; + + resets = <&rstctrl 6 &rstctrl 23>; + reset-names = "fe", "eth"; + + interrupt-parent = <&gic>; + interrupts = <3>; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy1f: ethernet-phy@1f { + reg = <0x1f>; + phy-mode = "rgmii"; + }; + }; + }; + + gsw@1e110000 { + compatible = "ralink,mt7620a-gsw"; + reg = <0x1e110000 8000>; + interrupt-parent = <&gic>; + interrupts = <23>; + }; + + pcie@1e140000 { + compatible = "mediatek,mt7621-pci"; + reg = <0x1e140000 0x100 + 0x1e142000 0x100>; + + #address-cells = <3>; + #size-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + + device_type = "pci"; + + bus-range = <0 255>; + ranges = < + 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ + 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ + >; + + status = "okay"; + + pcie0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + }; + + pcie1 { + reg = <0x0800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + }; + + pcie2 { + reg = <0x1000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + }; + }; +}; |