diff options
Diffstat (limited to 'target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu')
4 files changed, 714 insertions, 0 deletions
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c new file mode 100644 index 0000000..609e674 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c @@ -0,0 +1,207 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "mvOs.h" +#include "mvCpuCntrs.h" + + +const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = +{ + /*0*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, + MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, + }, + /*1*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, + }, + /*2*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, + MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, + }, + /*3*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, + MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, + MV_CPU_CNTRS_INVALID, + } +}; + +MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; + +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; + +void mvCpuCntrsReset(void) +{ + MV_U32 reg = 0; + + MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); +} + +void program_counter(int counter, int op) +{ + MV_U32 reg = (1 << op) | 0x1; /*enable*/ + + switch(counter) + { + case 0: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); + return; + + case 1: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); + return; + + case 2: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); + return; + + case 3: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); + return; + + default: + mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); + } + return; +} + +void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + { + pEvent->counters_sum[i] = 0; + } + pEvent->num_of_measurements = 0; +} + + +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) +{ + int i; + MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); + + if(event) + { + strncpy(event->name, name, sizeof(event->name)); + event->num_of_measurements = 0; + event->avg_sample_count = print_threshold; + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + { + event->counters_before[i] = 0; + event->counters_after[i] = 0; + event->counters_sum[i] = 0; + } + } + return event; +} + +void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) +{ + if(event != NULL) + mvOsFree(event); +} + + +MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, + char* name, MV_U32 overhead) +{ + int i; + + /* Find required operations */ + for(i=0; i<MV_CPU_CNTRS_OPS_NUM; i++) + { + if( mvCpuCntrsOpsTbl[counter][i] == op) + { + strncpy(mvCpuCntrsTbl[counter].name, name, sizeof(mvCpuCntrsTbl[counter].name)); + mvCpuCntrsTbl[counter].operation = op; + mvCpuCntrsTbl[counter].opIdx = i+1; + mvCpuCntrsTbl[counter].overhead = overhead; + program_counter(counter, mvCpuCntrsTbl[counter].opIdx); + mvOsPrintf("Counter=%d, opIdx=%d, overhead=%d\n", + counter, mvCpuCntrsTbl[counter].opIdx, mvCpuCntrsTbl[counter].overhead); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +void mvCpuCntrsShow(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + MV_U64 counters_avg; + + if(pEvent->num_of_measurements < pEvent->avg_sample_count) + return; + + mvOsPrintf("%16s: ", pEvent->name); + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + { + counters_avg = mvOsDivMod64(pEvent->counters_sum[i], + pEvent->num_of_measurements, NULL); + if(counters_avg >= mvCpuCntrsTbl[i].overhead) + counters_avg -= mvCpuCntrsTbl[i].overhead; + else + counters_avg = 0; + + mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); + } + mvOsPrintf("\n"); + mvCpuCntrsEventClear(pEvent); + mvCpuCntrsReset(); +} + +void mvCpuCntrsStatus(void) +{ + int i; + + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + { + mvOsPrintf("#%d: %s, overhead=%d\n", + i, mvCpuCntrsTbl[i].name, mvCpuCntrsTbl[i].overhead); + } +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h new file mode 100644 index 0000000..8d49af0 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h @@ -0,0 +1,213 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +#ifndef __mvCpuCntrs_h__ +#define __mvCpuCntrs_h__ + +#include "mvTypes.h" +#include "mvOs.h" + + +#define MV_CPU_CNTRS_NUM 4 +#define MV_CPU_CNTRS_OPS_NUM 32 + +typedef enum +{ + MV_CPU_CNTRS_INVALID = 0, + MV_CPU_CNTRS_CYCLES, + MV_CPU_CNTRS_ICACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_ACCESS, + MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_READ_HIT, + MV_CPU_CNTRS_DCACHE_WRITE_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_HIT, + MV_CPU_CNTRS_DTLB_MISS, + MV_CPU_CNTRS_TLB_MISS, + MV_CPU_CNTRS_ITLB_MISS, + MV_CPU_CNTRS_INSTRUCTIONS, + MV_CPU_CNTRS_SINGLE_ISSUE, + MV_CPU_CNTRS_MMU_READ_LATENCY, + MV_CPU_CNTRS_MMU_READ_BEAT, + MV_CPU_CNTRS_BRANCH_RETIRED, + MV_CPU_CNTRS_BRANCH_TAKEN, + MV_CPU_CNTRS_BRANCH_PREDICT_MISS, + MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, + MV_CPU_CNTRS_WB_FULL_CYCLES, + MV_CPU_CNTRS_WB_WRITE_LATENCY, + MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_ICACHE_READ_LATENCY, + MV_CPU_CNTRS_ICACHE_READ_BEAT, + MV_CPU_CNTRS_DCACHE_READ_LATENCY, + MV_CPU_CNTRS_DCACHE_READ_BEAT, + MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, + MV_CPU_CNTRS_DCACHE_WRITE_BEAT, + MV_CPU_CNTRS_LDM_STM_HOLD, + MV_CPU_CNTRS_IS_HOLD, + MV_CPU_CNTRS_DATA_WRITE_ACCESS, + MV_CPU_CNTRS_DATA_READ_ACCESS, + MV_CPU_CNTRS_BIU_SIMULT_ACCESS, + MV_CPU_CNTRS_BIU_ANY_ACCESS, + +} MV_CPU_CNTRS_OPS; + +typedef struct +{ + char name[16]; + MV_CPU_CNTRS_OPS operation; + int opIdx; + MV_U32 overhead; + +} MV_CPU_CNTRS_ENTRY; + + +typedef struct +{ + char name[16]; + MV_U32 num_of_measurements; + MV_U32 avg_sample_count; + MV_U64 counters_before[MV_CPU_CNTRS_NUM]; + MV_U64 counters_after[MV_CPU_CNTRS_NUM]; + MV_U64 counters_sum[MV_CPU_CNTRS_NUM]; + +} MV_CPU_CNTRS_EVENT; + +extern MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; + + +MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, + char* name, MV_U32 overhead); +void mvCpuCntrsInit(void); +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold); +void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event); +void mvCpuCntrsReset(void); +void mvCpuCntrsShow(MV_CPU_CNTRS_EVENT* pEvent); +void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent); + +/* internal */ +void program_counter(int counter, int op); + +static INLINE MV_U64 mvCpuCntrsRead(const int counter) +{ + MV_U32 low = 0, high = 0; + MV_U32 ll = 0; + + switch(counter) + { + case 0: + MV_ASM ("mcr p15, 0, %0, c15, c12, 0" : : "r" (ll)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 0" : "=r" (low)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 1" : "=r" (high)); + break; + + case 1: + MV_ASM ("mcr p15, 0, %0, c15, c12, 1" : : "r" (ll)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 2" : "=r" (low)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 3" : "=r" (high)); + break; + + case 2: + MV_ASM ("mcr p15, 0, %0, c15, c12, 2" : : "r" (ll)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 4" : "=r" (low)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 5" : "=r" (high)); + break; + + case 3: + MV_ASM ("mcr p15, 0, %0, c15, c12, 3" : : "r" (ll)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 6" : "=r" (low)); + MV_ASM ("mrc p15, 0, %0, c15, c13, 7" : "=r" (high)); + break; + + default: + mvOsPrintf("mv_cpu_cntrs_read: bad counter number (%d)\n", counter); + } + program_counter(counter, mvCpuCntrsTbl[counter].opIdx); + return (((MV_U64)high << 32 ) | low); + +} + + +static INLINE void mvCpuCntrsReadBefore(MV_CPU_CNTRS_EVENT* pEvent) +{ +#if 0 + int i; + + /* order is important - we want to measure the cycle count last here! */ + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + pEvent->counters_before[i] = mvCpuCntrsRead(i); +#else + pEvent->counters_before[1] = mvCpuCntrsRead(1); + pEvent->counters_before[3] = mvCpuCntrsRead(3); + pEvent->counters_before[0] = mvCpuCntrsRead(0); + pEvent->counters_before[2] = mvCpuCntrsRead(2); +#endif +} + +static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + +#if 0 + /* order is important - we want to measure the cycle count first here! */ + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + pEvent->counters_after[i] = mvCpuCntrsRead(i); +#else + pEvent->counters_after[2] = mvCpuCntrsRead(2); + pEvent->counters_after[0] = mvCpuCntrsRead(0); + pEvent->counters_after[3] = mvCpuCntrsRead(3); + pEvent->counters_after[1] = mvCpuCntrsRead(1); +#endif + + for(i=0; i<MV_CPU_CNTRS_NUM; i++) + { + pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); + } + pEvent->num_of_measurements++; +} + + +#ifdef CONFIG_MV_CPU_PERF_CNTRS + +#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) + +#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) + +#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) + +#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) + +#else + +#define MV_CPU_CNTRS_READ(counter) +#define MV_CPU_CNTRS_START(event) +#define MV_CPU_CNTRS_STOP(event) +#define MV_CPU_CNTRS_SHOW(event) + +#endif /* CONFIG_MV_CPU_PERF_CNTRS */ + + +#endif /* __mvCpuCntrs_h__ */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c new file mode 100644 index 0000000..0333862 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c @@ -0,0 +1,143 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "mvOs.h" +#include "mvCpuL2Cntrs.h" + + + +MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; + +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; + +void mvCpuL2CntrsReset(void) +{ + MV_U32 reg = 0; + + MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); +} + +static void mvCpuL2CntrConfig(int counter, int op) +{ + MV_U32 reg = (1 << op) | 0x1; /*enable*/ + + switch(counter) + { + case 0: + MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); + return; + + case 1: + MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); + return; + + default: + mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); + } + return; +} + +void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++) + { + pEvent->counters_sum[i] = 0; + } + pEvent->num_of_measurements = 0; +} + + +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) +{ + int i; + MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); + + if(event) + { + strncpy(event->name, name, sizeof(event->name)); + event->num_of_measurements = 0; + event->avg_sample_count = print_threshold; + for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++) + { + event->counters_before[i] = 0; + event->counters_after[i] = 0; + event->counters_sum[i] = 0; + } + } + return event; +} + +void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) +{ + if(event != NULL) + mvOsFree(event); +} + + +MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, + char* name, MV_U32 overhead) +{ + strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); + mvCpuL2CntrsTbl[counter].operation = op; + mvCpuL2CntrsTbl[counter].opIdx = op; + mvCpuL2CntrsTbl[counter].overhead = overhead; + mvCpuL2CntrConfig(counter, op); + mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", + counter, op, overhead); + return MV_OK; +} + +void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + MV_U64 counters_avg; + + if(pEvent->num_of_measurements < pEvent->avg_sample_count) + return; + + mvOsPrintf("%16s: ", pEvent->name); + for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++) + { + counters_avg = mvOsDivMod64(pEvent->counters_sum[i], + pEvent->num_of_measurements, NULL); + + if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) + counters_avg -= mvCpuL2CntrsTbl[i].overhead; + else + counters_avg = 0; + + mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); + } + mvOsPrintf("\n"); + mvCpuL2CntrsEventClear(pEvent); + mvCpuL2CntrsReset(); +} + +void mvCpuL2CntrsStatus(void) +{ + int i; + + for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++) + { + mvOsPrintf("#%d: %s, overhead=%d\n", + i, mvCpuL2CntrsTbl[i].name, mvCpuL2CntrsTbl[i].overhead); + } +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h new file mode 100644 index 0000000..570d701 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h @@ -0,0 +1,151 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +#ifndef __mvCpuL2Cntrs_h__ +#define __mvCpuL2Cntrs_h__ + +#include "mvTypes.h" +#include "mvOs.h" + + +#define MV_CPU_L2_CNTRS_NUM 2 + +typedef enum +{ + MV_CPU_L2_CNTRS_ENABLE = 0, + MV_CPU_L2_CNTRS_DATA_REQ, + MV_CPU_L2_CNTRS_DATA_MISS_REQ, + MV_CPU_L2_CNTRS_INST_REQ, + MV_CPU_L2_CNTRS_INST_MISS_REQ, + MV_CPU_L2_CNTRS_DATA_READ_REQ, + MV_CPU_L2_CNTRS_DATA_READ_MISS_REQ, + MV_CPU_L2_CNTRS_DATA_WRITE_REQ, + MV_CPU_L2_CNTRS_DATA_WRITE_MISS_REQ, + MV_CPU_L2_CNTRS_RESERVED, + MV_CPU_L2_CNTRS_DIRTY_EVICT_REQ, + MV_CPU_L2_CNTRS_EVICT_BUFF_STALL, + MV_CPU_L2_CNTRS_ACTIVE_CYCLES, + +} MV_CPU_L2_CNTRS_OPS; + +typedef struct +{ + char name[16]; + MV_CPU_L2_CNTRS_OPS operation; + int opIdx; + MV_U32 overhead; + +} MV_CPU_L2_CNTRS_ENTRY; + + +typedef struct +{ + char name[16]; + MV_U32 num_of_measurements; + MV_U32 avg_sample_count; + MV_U64 counters_before[MV_CPU_L2_CNTRS_NUM]; + MV_U64 counters_after[MV_CPU_L2_CNTRS_NUM]; + MV_U64 counters_sum[MV_CPU_L2_CNTRS_NUM]; + +} MV_CPU_L2_CNTRS_EVENT; + + +MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, + char* name, MV_U32 overhead); +void mvCpuL2CntrsInit(void); +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold); +void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event); +void mvCpuL2CntrsReset(void); +void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent); +void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent); + +static INLINE MV_U64 mvCpuL2CntrsRead(const int counter) +{ + MV_U32 low = 0, high = 0; + + switch(counter) + { + case 0: + MV_ASM ("mrc p15, 6, %0, c15, c13, 0" : "=r" (low)); + MV_ASM ("mrc p15, 6, %0, c15, c13, 1" : "=r" (high)); + break; + + case 1: + MV_ASM ("mrc p15, 6, %0, c15, c13, 2" : "=r" (low)); + MV_ASM ("mrc p15, 6, %0, c15, c13, 3" : "=r" (high)); + break; + + default: + mvOsPrintf("mvCpuL2CntrsRead: bad counter number (%d)\n", counter); + } + return (((MV_U64)high << 32 ) | low); + +} + +static INLINE void mvCpuL2CntrsReadBefore(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++) + pEvent->counters_before[i] = mvCpuL2CntrsRead(i); +} + +static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; i<MV_CPU_L2_CNTRS_NUM; i++) + { + pEvent->counters_after[i] = mvCpuL2CntrsRead(i); + pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); + } + pEvent->num_of_measurements++; +} + + +#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS + +#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) + +#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) + +#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) + +#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) + +#else + +#define MV_CPU_L2_CNTRS_READ(counter) +#define MV_CPU_L2_CNTRS_START(event) +#define MV_CPU_L2_CNTRS_STOP(event) +#define MV_CPU_L2_CNTRS_SHOW(event) + +#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ + + +#endif /* __mvCpuL2Cntrs_h__ */ + |