diff options
Diffstat (limited to 'target/linux/bcm53xx/patches-4.3')
37 files changed, 4539 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-4.3/043-clk-iproc-Fix-PLL-output-frequency-calculation.patch b/target/linux/bcm53xx/patches-4.3/043-clk-iproc-Fix-PLL-output-frequency-calculation.patch new file mode 100644 index 0000000..20dd90e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/043-clk-iproc-Fix-PLL-output-frequency-calculation.patch @@ -0,0 +1,59 @@ +From 63243a4da7d0dfa19dcacd0a529782eeb2f86f92 Mon Sep 17 00:00:00 2001 +From: Simran Rai <ssimran@broadcom.com> +Date: Mon, 19 Oct 2015 15:27:19 -0700 +Subject: [PATCH] clk: iproc: Fix PLL output frequency calculation + +This patch affects the clocks that use fractional ndivider in their +PLL output frequency calculation. Instead of 2^20 divide factor, the +clock's ndiv integer shift was used. Fixed the bug by replacing ndiv +integer shift with 2^20 factor. + +Signed-off-by: Simran Rai <ssimran@broadcom.com> +Signed-off-by: Ray Jui <rjui@broadcom.com> +Reviewed-by: Scott Branden <sbranden@broadcom.com> +Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") +Cc: <stable@vger.kernel.org> # v4.1+ +Signed-off-by: Michael Turquette <mturquette@baylibre.com> +--- + drivers/clk/bcm/clk-iproc-pll.c | 13 +++++-------- + 1 file changed, 5 insertions(+), 8 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_ra + struct iproc_pll *pll = clk->pll; + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + u32 val; +- u64 ndiv; +- unsigned int ndiv_int, ndiv_frac, pdiv; ++ u64 ndiv, ndiv_int, ndiv_frac; ++ unsigned int pdiv; + + if (parent_rate == 0) + return 0; +@@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_ra + val = readl(pll->pll_base + ctrl->ndiv_int.offset); + ndiv_int = (val >> ctrl->ndiv_int.shift) & + bit_mask(ctrl->ndiv_int.width); +- ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift; ++ ndiv = ndiv_int << 20; + + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { + val = readl(pll->pll_base + ctrl->ndiv_frac.offset); + ndiv_frac = (val >> ctrl->ndiv_frac.shift) & + bit_mask(ctrl->ndiv_frac.width); +- +- if (ndiv_frac != 0) +- ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) | +- ndiv_frac; ++ ndiv += ndiv_frac; + } + + val = readl(pll->pll_base + ctrl->pdiv.offset); + pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); + +- clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift; ++ clk->rate = (ndiv * parent_rate) >> 20; + + if (pdiv == 0) + clk->rate *= 2; diff --git a/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch b/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch new file mode 100644 index 0000000..f65aa9c --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch @@ -0,0 +1,292 @@ +From b5116083e227fa478e20d5ed945430088aa1a00b Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 15:48:25 -0400 +Subject: [PATCH 44/50] clk: cygnus: Convert all macros to all caps + +The macros that are being used to initialize the values of the clk +structures should be all caps. Find and replace all of them with their +relevant counterparts. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++---------------------- + 1 file changed, 73 insertions(+), 73 deletions(-) + +--- a/drivers/clk/bcm/clk-cygnus.c ++++ b/drivers/clk/bcm/clk-cygnus.c +@@ -23,28 +23,28 @@ + #include <dt-bindings/clock/bcm-cygnus.h> + #include "clk-iproc.h" + +-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, } ++#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } + +-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ ++#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ + .pwr_shift = ps, .iso_shift = is } + +-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, } ++#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, } + +-#define asiu_div_val(o, es, hs, hw, ls, lw) \ ++#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ + { .offset = o, .en_shift = es, .high_shift = hs, \ + .high_width = hw, .low_shift = ls, .low_width = lw } + +-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ ++#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ + .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ + .ka_width = kaw } + +-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } ++#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } + +-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \ ++#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ + .hold_shift = hs, .bypass_shift = bs } + +-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es } ++#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } + + static void __init cygnus_armpll_init(struct device_node *node) + { +@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygn + static const struct iproc_pll_ctrl genpll = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_PLL_NEEDS_SW_CFG, +- .aon = aon_val(0x0, 2, 1, 0), +- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), +- .sw_ctrl = sw_ctrl_val(0x10, 31), +- .ndiv_int = reg_val(0x10, 20, 10), +- .ndiv_frac = reg_val(0x10, 0, 20), +- .pdiv = reg_val(0x14, 0, 4), +- .vco_ctrl = vco_ctrl_val(0x18, 0x1c), +- .status = reg_val(0x28, 12, 1), ++ .aon = AON_VAL(0x0, 2, 1, 0), ++ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .sw_ctrl = SW_CTRL_VAL(0x10, 31), ++ .ndiv_int = REG_VAL(0x10, 20, 10), ++ .ndiv_frac = REG_VAL(0x10, 0, 20), ++ .pdiv = REG_VAL(0x14, 0, 4), ++ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), ++ .status = REG_VAL(0x28, 12, 1), + }; + + static const struct iproc_clk_ctrl genpll_clk[] = { + [BCM_CYGNUS_GENPLL_AXI21_CLK] = { + .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 6, 0, 12), +- .mdiv = reg_val(0x20, 0, 8), ++ .enable = ENABLE_VAL(0x4, 6, 0, 12), ++ .mdiv = REG_VAL(0x20, 0, 8), + }, + [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { + .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 7, 1, 13), +- .mdiv = reg_val(0x20, 10, 8), ++ .enable = ENABLE_VAL(0x4, 7, 1, 13), ++ .mdiv = REG_VAL(0x20, 10, 8), + }, + [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { + .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 8, 2, 14), +- .mdiv = reg_val(0x20, 20, 8), ++ .enable = ENABLE_VAL(0x4, 8, 2, 14), ++ .mdiv = REG_VAL(0x20, 20, 8), + }, + [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { + .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 9, 3, 15), +- .mdiv = reg_val(0x24, 0, 8), ++ .enable = ENABLE_VAL(0x4, 9, 3, 15), ++ .mdiv = REG_VAL(0x24, 0, 8), + }, + [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { + .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 10, 4, 16), +- .mdiv = reg_val(0x24, 10, 8), ++ .enable = ENABLE_VAL(0x4, 10, 4, 16), ++ .mdiv = REG_VAL(0x24, 10, 8), + }, + [BCM_CYGNUS_GENPLL_CAN_CLK] = { + .channel = BCM_CYGNUS_GENPLL_CAN_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 11, 5, 17), +- .mdiv = reg_val(0x24, 20, 8), ++ .enable = ENABLE_VAL(0x4, 11, 5, 17), ++ .mdiv = REG_VAL(0x24, 20, 8), + }, + }; + +@@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn + + static const struct iproc_pll_ctrl lcpll0 = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, +- .aon = aon_val(0x0, 2, 5, 4), +- .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4), +- .sw_ctrl = sw_ctrl_val(0x4, 31), +- .ndiv_int = reg_val(0x4, 16, 10), +- .pdiv = reg_val(0x4, 26, 4), +- .vco_ctrl = vco_ctrl_val(0x10, 0x14), +- .status = reg_val(0x18, 12, 1), ++ .aon = AON_VAL(0x0, 2, 5, 4), ++ .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), ++ .sw_ctrl = SW_CTRL_VAL(0x4, 31), ++ .ndiv_int = REG_VAL(0x4, 16, 10), ++ .pdiv = REG_VAL(0x4, 26, 4), ++ .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14), ++ .status = REG_VAL(0x18, 12, 1), + }; + + static const struct iproc_clk_ctrl lcpll0_clk[] = { + [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 7, 1, 13), +- .mdiv = reg_val(0x8, 0, 8), ++ .enable = ENABLE_VAL(0x0, 7, 1, 13), ++ .mdiv = REG_VAL(0x8, 0, 8), + }, + [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 8, 2, 14), +- .mdiv = reg_val(0x8, 10, 8), ++ .enable = ENABLE_VAL(0x0, 8, 2, 14), ++ .mdiv = REG_VAL(0x8, 10, 8), + }, + [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 9, 3, 15), +- .mdiv = reg_val(0x8, 20, 8), ++ .enable = ENABLE_VAL(0x0, 9, 3, 15), ++ .mdiv = REG_VAL(0x8, 20, 8), + }, + [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 10, 4, 16), +- .mdiv = reg_val(0xc, 0, 8), ++ .enable = ENABLE_VAL(0x0, 10, 4, 16), ++ .mdiv = REG_VAL(0xc, 0, 8), + }, + [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 11, 5, 17), +- .mdiv = reg_val(0xc, 10, 8), ++ .enable = ENABLE_VAL(0x0, 11, 5, 17), ++ .mdiv = REG_VAL(0xc, 10, 8), + }, + [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { + .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 12, 6, 18), +- .mdiv = reg_val(0xc, 20, 8), ++ .enable = ENABLE_VAL(0x0, 12, 6, 18), ++ .mdiv = REG_VAL(0xc, 20, 8), + }, + }; + +@@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param + static const struct iproc_pll_ctrl mipipll = { + .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_NEEDS_READ_BACK, +- .aon = aon_val(0x0, 4, 17, 16), +- .asiu = asiu_gate_val(0x0, 3), +- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4), +- .ndiv_int = reg_val(0x10, 20, 10), +- .ndiv_frac = reg_val(0x10, 0, 20), +- .pdiv = reg_val(0x14, 0, 4), +- .vco_ctrl = vco_ctrl_val(0x18, 0x1c), +- .status = reg_val(0x28, 12, 1), ++ .aon = AON_VAL(0x0, 4, 17, 16), ++ .asiu = ASIU_GATE_VAL(0x0, 3), ++ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), ++ .ndiv_int = REG_VAL(0x10, 20, 10), ++ .ndiv_frac = REG_VAL(0x10, 0, 20), ++ .pdiv = REG_VAL(0x14, 0, 4), ++ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), ++ .status = REG_VAL(0x28, 12, 1), + }; + + static const struct iproc_clk_ctrl mipipll_clk[] = { + [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 12, 6, 18), +- .mdiv = reg_val(0x20, 0, 8), ++ .enable = ENABLE_VAL(0x4, 12, 6, 18), ++ .mdiv = REG_VAL(0x20, 0, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { + .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 13, 7, 19), +- .mdiv = reg_val(0x20, 10, 8), ++ .enable = ENABLE_VAL(0x4, 13, 7, 19), ++ .mdiv = REG_VAL(0x20, 10, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { + .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 14, 8, 20), +- .mdiv = reg_val(0x20, 20, 8), ++ .enable = ENABLE_VAL(0x4, 14, 8, 20), ++ .mdiv = REG_VAL(0x20, 20, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 15, 9, 21), +- .mdiv = reg_val(0x24, 0, 8), ++ .enable = ENABLE_VAL(0x4, 15, 9, 21), ++ .mdiv = REG_VAL(0x24, 0, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 16, 10, 22), +- .mdiv = reg_val(0x24, 10, 8), ++ .enable = ENABLE_VAL(0x4, 16, 10, 22), ++ .mdiv = REG_VAL(0x24, 10, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 17, 11, 23), +- .mdiv = reg_val(0x24, 20, 8), ++ .enable = ENABLE_VAL(0x4, 17, 11, 23), ++ .mdiv = REG_VAL(0x24, 20, 8), + }, + }; + +@@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_in + CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); + + static const struct iproc_asiu_div asiu_div[] = { +- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10), +- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10), +- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10), ++ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10), ++ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10), ++ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10), + }; + + static const struct iproc_asiu_gate asiu_gate[] = { +- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7), +- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9), +- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0), ++ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7), ++ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9), ++ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0), + }; + + static void __init cygnus_asiu_init(struct device_node *node) diff --git a/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch b/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch new file mode 100644 index 0000000..318bd5c --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch @@ -0,0 +1,120 @@ +From 7c70cb333deb6e2f88da9c94ddd6b3b00c97b93a Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 15:48:26 -0400 +Subject: [PATCH 45/50] clk: iproc: Add PWRCTRL support + +Some iProc SoC clocks use a different way to control clock power, via +the PWRDWN bit in the PLL control register. Since the PLL control +register is used to access the PWRDWN bit, there is no need for the +pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, +has been added to identify this usage. We can use the AON interface to +write the values to enable/disable PWRDOWN. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++------------- + drivers/clk/bcm/clk-iproc.h | 6 +++++ + 2 files changed, 44 insertions(+), 17 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_p + writel(val, pll->asiu_base + ctrl->asiu.offset); + } + +- /* latch input value so core power can be shut down */ +- val = readl(pll->pwr_base + ctrl->aon.offset); +- val |= (1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); +- +- /* power down the core */ +- val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { ++ val = readl(pll->pll_base + ctrl->aon.offset); ++ val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); ++ writel(val, pll->pll_base + ctrl->aon.offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) ++ readl(pll->pll_base + ctrl->aon.offset); ++ } ++ ++ if (pll->pwr_base) { ++ /* latch input value so core power can be shut down */ ++ val = readl(pll->pwr_base + ctrl->aon.offset); ++ val |= (1 << ctrl->aon.iso_shift); ++ writel(val, pll->pwr_base + ctrl->aon.offset); ++ ++ /* power down the core */ ++ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); ++ writel(val, pll->pwr_base + ctrl->aon.offset); ++ } + } + + static int __pll_enable(struct iproc_pll *pll) +@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + u32 val; + +- /* power up the PLL and make sure it's not latched */ +- val = readl(pll->pwr_base + ctrl->aon.offset); +- val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; +- val &= ~(1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { ++ val = readl(pll->pll_base + ctrl->aon.offset); ++ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); ++ writel(val, pll->pll_base + ctrl->aon.offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) ++ readl(pll->pll_base + ctrl->aon.offset); ++ } ++ ++ if (pll->pwr_base) { ++ /* power up the PLL and make sure it's not latched */ ++ val = readl(pll->pwr_base + ctrl->aon.offset); ++ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; ++ val &= ~(1 << ctrl->aon.iso_shift); ++ writel(val, pll->pwr_base + ctrl->aon.offset); ++ } + + /* certain PLLs also need to be ungated from the ASIU top level */ + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { +@@ -607,9 +629,8 @@ void __init iproc_pll_clk_setup(struct d + if (WARN_ON(!pll->pll_base)) + goto err_pll_iomap; + ++ /* Some SoCs do not require the pwr_base, thus failing is not fatal */ + pll->pwr_base = of_iomap(node, 1); +- if (WARN_ON(!pll->pwr_base)) +- goto err_pwr_iomap; + + /* some PLLs require gating control at the top ASIU level */ + if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { +@@ -692,9 +713,9 @@ err_pll_register: + iounmap(pll->asiu_base); + + err_asiu_iomap: +- iounmap(pll->pwr_base); ++ if (pll->pwr_base) ++ iounmap(pll->pwr_base); + +-err_pwr_iomap: + iounmap(pll->pll_base); + + err_pll_iomap: +--- a/drivers/clk/bcm/clk-iproc.h ++++ b/drivers/clk/bcm/clk-iproc.h +@@ -49,6 +49,12 @@ + #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4) + + /* ++ * Some PLLs use a different way to control clock power, via the PWRDWN bit in ++ * the PLL control register ++ */ ++#define IPROC_CLK_EMBED_PWRCTRL BIT(5) ++ ++/* + * Parameters for VCO frequency configuration + * + * VCO frequency = diff --git a/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch b/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch new file mode 100644 index 0000000..c8eda8d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch @@ -0,0 +1,219 @@ +From d358480591b34d081806ecb5a9474930a4d59f8a Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 15:48:27 -0400 +Subject: [PATCH 46/50] clk: nsp: add clock support for Broadcom Northstar Plus + SoC + +The Broadcom Northstar Plus SoC is architected under the iProc +architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all +derived from an onboard crystal. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + drivers/clk/bcm/Makefile | 2 + + drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++ + include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++ + 3 files changed, 188 insertions(+) + create mode 100644 drivers/clk/bcm/clk-nsp.c + create mode 100644 include/dt-bindings/clock/bcm-nsp.h + +--- a/drivers/clk/bcm/Makefile ++++ b/drivers/clk/bcm/Makefile +@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281 + obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o + obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o + obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o ++obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o ++obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o +--- /dev/null ++++ b/drivers/clk/bcm/clk-nsp.c +@@ -0,0 +1,135 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/err.h> ++#include <linux/clk-provider.h> ++#include <linux/io.h> ++#include <linux/of.h> ++#include <linux/of_address.h> ++ ++#include <dt-bindings/clock/bcm-nsp.h> ++#include "clk-iproc.h" ++ ++#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } ++ ++#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ ++ .pwr_shift = ps, .iso_shift = is } ++ ++#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ ++ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ ++ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ ++ .ka_width = kaw } ++ ++#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ ++ .hold_shift = hs, .bypass_shift = bs } ++ ++static void __init nsp_armpll_init(struct device_node *node) ++{ ++ iproc_armpll_setup(node); ++} ++CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); ++ ++static const struct iproc_pll_ctrl genpll = { ++ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, ++ .aon = AON_VAL(0x0, 1, 12, 0), ++ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .ndiv_int = REG_VAL(0x14, 20, 10), ++ .ndiv_frac = REG_VAL(0x14, 0, 20), ++ .pdiv = REG_VAL(0x18, 24, 3), ++ .status = REG_VAL(0x20, 12, 1), ++}; ++ ++static const struct iproc_clk_ctrl genpll_clk[] = { ++ [BCM_NSP_GENPLL_PHY_CLK] = { ++ .channel = BCM_NSP_GENPLL_PHY_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 12, 6, 18), ++ .mdiv = REG_VAL(0x18, 16, 8), ++ }, ++ [BCM_NSP_GENPLL_ENET_SW_CLK] = { ++ .channel = BCM_NSP_GENPLL_ENET_SW_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 13, 7, 19), ++ .mdiv = REG_VAL(0x18, 8, 8), ++ }, ++ [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = { ++ .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 14, 8, 20), ++ .mdiv = REG_VAL(0x18, 0, 8), ++ }, ++ [BCM_NSP_GENPLL_IPROCFAST_CLK] = { ++ .channel = BCM_NSP_GENPLL_IPROCFAST_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 15, 9, 21), ++ .mdiv = REG_VAL(0x1c, 16, 8), ++ }, ++ [BCM_NSP_GENPLL_SATA1_CLK] = { ++ .channel = BCM_NSP_GENPLL_SATA1_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 16, 10, 22), ++ .mdiv = REG_VAL(0x1c, 8, 8), ++ }, ++ [BCM_NSP_GENPLL_SATA2_CLK] = { ++ .channel = BCM_NSP_GENPLL_SATA2_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 17, 11, 23), ++ .mdiv = REG_VAL(0x1c, 0, 8), ++ }, ++}; ++ ++static void __init nsp_genpll_clk_init(struct device_node *node) ++{ ++ iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, ++ ARRAY_SIZE(genpll_clk)); ++} ++CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); ++ ++static const struct iproc_pll_ctrl lcpll0 = { ++ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, ++ .aon = AON_VAL(0x0, 1, 24, 0), ++ .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), ++ .ndiv_int = REG_VAL(0x4, 20, 8), ++ .ndiv_frac = REG_VAL(0x4, 0, 20), ++ .pdiv = REG_VAL(0x4, 28, 3), ++ .status = REG_VAL(0x10, 12, 1), ++}; ++ ++static const struct iproc_clk_ctrl lcpll0_clk[] = { ++ [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = { ++ .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x0, 6, 3, 9), ++ .mdiv = REG_VAL(0x8, 24, 8), ++ }, ++ [BCM_NSP_LCPLL0_SDIO_CLK] = { ++ .channel = BCM_NSP_LCPLL0_SDIO_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x0, 7, 4, 10), ++ .mdiv = REG_VAL(0x8, 16, 8), ++ }, ++ [BCM_NSP_LCPLL0_DDR_PHY_CLK] = { ++ .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x0, 8, 5, 11), ++ .mdiv = REG_VAL(0x8, 8, 8), ++ }, ++}; ++ ++static void __init nsp_lcpll0_clk_init(struct device_node *node) ++{ ++ iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, ++ ARRAY_SIZE(lcpll0_clk)); ++} ++CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init); +--- /dev/null ++++ b/include/dt-bindings/clock/bcm-nsp.h +@@ -0,0 +1,51 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef _CLOCK_BCM_NSP_H ++#define _CLOCK_BCM_NSP_H ++ ++/* GENPLL clock channel ID */ ++#define BCM_NSP_GENPLL 0 ++#define BCM_NSP_GENPLL_PHY_CLK 1 ++#define BCM_NSP_GENPLL_ENET_SW_CLK 2 ++#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 ++#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 ++#define BCM_NSP_GENPLL_SATA1_CLK 5 ++#define BCM_NSP_GENPLL_SATA2_CLK 6 ++ ++/* LCPLL0 clock channel ID */ ++#define BCM_NSP_LCPLL0 0 ++#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 ++#define BCM_NSP_LCPLL0_SDIO_CLK 2 ++#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 ++ ++#endif /* _CLOCK_BCM_NSP_H */ diff --git a/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch new file mode 100644 index 0000000..2f07cc6 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch @@ -0,0 +1,223 @@ +From acbb7a3de7e4d83b23c0bbb3eaf77d15a041d865 Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 15:48:28 -0400 +Subject: [PATCH 47/50] clk: iproc: Add PLL base write function + +All writes to the PLL base address must be flushed if the +IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the +necessary write and reads, we can make sure that any future code which +makes PLL base writes will do the correct thing. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + drivers/clk/bcm/clk-iproc-pll.c | 80 +++++++++++++++++------------------------ + 1 file changed, 33 insertions(+), 47 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct ipro + return -EIO; + } + ++static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, ++ const u32 offset, u32 val) ++{ ++ const struct iproc_pll_ctrl *ctrl = pll->ctrl; ++ ++ writel(val, base + offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && ++ base == pll->pll_base)) ++ val = readl(base + offset); ++} ++ + static void __pll_disable(struct iproc_pll *pll) + { + const struct iproc_pll_ctrl *ctrl = pll->ctrl; +@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_p + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { + val = readl(pll->asiu_base + ctrl->asiu.offset); + val &= ~(1 << ctrl->asiu.en_shift); +- writel(val, pll->asiu_base + ctrl->asiu.offset); ++ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); + } + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pll_base + ctrl->aon.offset); +- +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { + /* latch input value so core power can be shut down */ + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= (1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + + /* power down the core */ + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + } + } + +@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pll_base + ctrl->aon.offset); +- +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; + val &= ~(1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + } + + /* certain PLLs also need to be ungated from the ASIU top level */ + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { + val = readl(pll->asiu_base + ctrl->asiu.offset); + val |= (1 << ctrl->asiu.en_shift); +- writel(val, pll->asiu_base + ctrl->asiu.offset); ++ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); + } + + return 0; +@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct ip + + val = readl(pll->pll_base + reset->offset); + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); +- writel(val, pll->pll_base + reset->offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + reset->offset); ++ iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } + + static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, +@@ -228,9 +232,7 @@ static void __pll_bring_out_reset(struct + val |= ki << reset->ki_shift | kp << reset->kp_shift | + ka << reset->ka_shift; + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; +- writel(val, pll->pll_base + reset->offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + reset->offset); ++ iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } + + static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, +@@ -285,9 +287,8 @@ static int pll_set_rate(struct iproc_clk + /* put PLL in reset */ + __pll_put_in_reset(pll); + +- writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->vco_ctrl.u_offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); ++ + val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); + + if (rate >= VCO_LOW && rate < VCO_MID) +@@ -298,17 +299,13 @@ static int pll_set_rate(struct iproc_clk + else + val |= (1 << PLL_VCO_HIGH_SHIFT); + +- writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->vco_ctrl.l_offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); + + /* program integer part of NDIV */ + val = readl(pll->pll_base + ctrl->ndiv_int.offset); + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); + val |= vco->ndiv_int << ctrl->ndiv_int.shift; +- writel(val, pll->pll_base + ctrl->ndiv_int.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->ndiv_int.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); + + /* program fractional part of NDIV */ + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +@@ -316,18 +313,15 @@ static int pll_set_rate(struct iproc_clk + val &= ~(bit_mask(ctrl->ndiv_frac.width) << + ctrl->ndiv_frac.shift); + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; +- writel(val, pll->pll_base + ctrl->ndiv_frac.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, ++ val); + } + + /* program PDIV */ + val = readl(pll->pll_base + ctrl->pdiv.offset); + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); + val |= vco->pdiv << ctrl->pdiv.shift; +- writel(val, pll->pll_base + ctrl->pdiv.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->pdiv.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); + + __pll_bring_out_reset(pll, kp, ka, ki); + +@@ -464,14 +458,12 @@ static int iproc_clk_enable(struct clk_h + /* channel enable is active low */ + val = readl(pll->pll_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.enable_shift); +- writel(val, pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + + /* also make sure channel is not held */ + val = readl(pll->pll_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.hold_shift); +- writel(val, pll->pll_base + ctrl->enable.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + + return 0; + } +@@ -488,9 +480,7 @@ static void iproc_clk_disable(struct clk + + val = readl(pll->pll_base + ctrl->enable.offset); + val |= 1 << ctrl->enable.enable_shift; +- writel(val, pll->pll_base + ctrl->enable.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + } + + static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, +@@ -559,9 +549,7 @@ static int iproc_clk_set_rate(struct clk + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + val |= div << ctrl->mdiv.shift; + } +- writel(val, pll->pll_base + ctrl->mdiv.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->mdiv.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); + clk->rate = parent_rate / div; + + return 0; +@@ -588,9 +576,7 @@ static void iproc_pll_sw_cfg(struct ipro + + val = readl(pll->pll_base + ctrl->sw_ctrl.offset); + val |= BIT(ctrl->sw_ctrl.shift); +- writel(val, pll->pll_base + ctrl->sw_ctrl.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->sw_ctrl.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); + } + } + diff --git a/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch b/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch new file mode 100644 index 0000000..528311f --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch @@ -0,0 +1,158 @@ +From fb9e4932d17ad32786d03cb672fb62f2b337acf5 Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 15:48:29 -0400 +Subject: [PATCH 48/50] clk: iproc: Split off dig_filter + +The PLL loop filter/gain can be located in a separate register on some +SoCs. Split these off into a separate variable, so that an offset can +be added if necessary. Also, make the necessary modifications to the +Cygnus and NSP drivers for this change. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------ + drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++----- + drivers/clk/bcm/clk-iproc.h | 10 +++++++++- + drivers/clk/bcm/clk-nsp.c | 14 +++++++++----- + 4 files changed, 38 insertions(+), 17 deletions(-) + +--- a/drivers/clk/bcm/clk-cygnus.c ++++ b/drivers/clk/bcm/clk-cygnus.c +@@ -34,9 +34,11 @@ + { .offset = o, .en_shift = es, .high_shift = hs, \ + .high_width = hw, .low_shift = ls, .low_width = lw } + +-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ +- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ +- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ ++#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ ++ .p_reset_shift = prs } ++ ++#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ ++ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ + .ka_width = kaw } + + #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } +@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpl + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_PLL_NEEDS_SW_CFG, + .aon = AON_VAL(0x0, 2, 1, 0), +- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .reset = RESET_VAL(0x0, 11, 10), ++ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), + .sw_ctrl = SW_CTRL_VAL(0x10, 31), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), +@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn + static const struct iproc_pll_ctrl lcpll0 = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, + .aon = AON_VAL(0x0, 2, 5, 4), +- .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), ++ .reset = RESET_VAL(0x0, 31, 30), ++ .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4), + .sw_ctrl = SW_CTRL_VAL(0x4, 31), + .ndiv_int = REG_VAL(0x4, 16, 10), + .pdiv = REG_VAL(0x4, 26, 4), +@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipip + IPROC_CLK_NEEDS_READ_BACK, + .aon = AON_VAL(0x0, 4, 17, 16), + .asiu = ASIU_GATE_VAL(0x0, 3), +- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), ++ .reset = RESET_VAL(0x0, 11, 10), ++ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), + .pdiv = REG_VAL(0x14, 0, 4), +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct + u32 val; + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; ++ const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; ++ ++ val = readl(pll->pll_base + dig_filter->offset); ++ val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | ++ bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | ++ bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); ++ val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | ++ ka << dig_filter->ka_shift; ++ iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); + + val = readl(pll->pll_base + reset->offset); +- val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | +- bit_mask(reset->kp_width) << reset->kp_shift | +- bit_mask(reset->ka_width) << reset->ka_shift); +- val |= ki << reset->ki_shift | kp << reset->kp_shift | +- ka << reset->ka_shift; + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; + iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } +--- a/drivers/clk/bcm/clk-iproc.h ++++ b/drivers/clk/bcm/clk-iproc.h +@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl { + }; + + /* +- * Control of the PLL reset, with Ki, Kp, and Ka parameters ++ * Control of the PLL reset + */ + struct iproc_pll_reset_ctrl { + unsigned int offset; + unsigned int reset_shift; + unsigned int p_reset_shift; ++}; ++ ++/* ++ * Control of the Ki, Kp, and Ka parameters ++ */ ++struct iproc_pll_dig_filter_ctrl { ++ unsigned int offset; + unsigned int ki_shift; + unsigned int ki_width; + unsigned int kp_shift; +@@ -129,6 +136,7 @@ struct iproc_pll_ctrl { + struct iproc_pll_aon_pwr_ctrl aon; + struct iproc_asiu_gate asiu; + struct iproc_pll_reset_ctrl reset; ++ struct iproc_pll_dig_filter_ctrl dig_filter; + struct iproc_pll_sw_ctrl sw_ctrl; + struct iproc_clk_reg_op ndiv_int; + struct iproc_clk_reg_op ndiv_frac; +--- a/drivers/clk/bcm/clk-nsp.c ++++ b/drivers/clk/bcm/clk-nsp.c +@@ -26,9 +26,11 @@ + #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ + .pwr_shift = ps, .iso_shift = is } + +-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ +- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ +- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ ++#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ ++ .p_reset_shift = prs } ++ ++#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ ++ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ + .ka_width = kaw } + + #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ +@@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-arm + static const struct iproc_pll_ctrl genpll = { + .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, + .aon = AON_VAL(0x0, 1, 12, 0), +- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .reset = RESET_VAL(0x0, 11, 10), ++ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), + .ndiv_int = REG_VAL(0x14, 20, 10), + .ndiv_frac = REG_VAL(0x14, 0, 20), + .pdiv = REG_VAL(0x18, 24, 3), +@@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp + static const struct iproc_pll_ctrl lcpll0 = { + .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, + .aon = AON_VAL(0x0, 1, 24, 0), +- .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), ++ .reset = RESET_VAL(0x0, 23, 22), ++ .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4), + .ndiv_int = REG_VAL(0x4, 20, 8), + .ndiv_frac = REG_VAL(0x4, 0, 20), + .pdiv = REG_VAL(0x4, 28, 3), diff --git a/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch b/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch new file mode 100644 index 0000000..1e7cbc0 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch @@ -0,0 +1,319 @@ +From eeb32564795a3584dba6281f445ff2aa552be36b Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 15:48:30 -0400 +Subject: [PATCH 49/50] clk: iproc: Separate status and control variables + +Some PLLs have separate registers for Status and Control. The means the +pll_base needs to be split into 2 new variables, so that those PLLs can +specify device tree registers for those independently. Also, add a new +driver flag to identify this presence of the split, and let the driver +know that additional registers need to be used. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + drivers/clk/bcm/clk-iproc-pll.c | 96 ++++++++++++++++++++++++----------------- + drivers/clk/bcm/clk-iproc.h | 6 +++ + 2 files changed, 62 insertions(+), 40 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -74,7 +74,8 @@ struct iproc_clk { + }; + + struct iproc_pll { +- void __iomem *pll_base; ++ void __iomem *status_base; ++ void __iomem *control_base; + void __iomem *pwr_base; + void __iomem *asiu_base; + +@@ -127,7 +128,7 @@ static int pll_wait_for_lock(struct ipro + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + + for (i = 0; i < LOCK_DELAY; i++) { +- u32 val = readl(pll->pll_base + ctrl->status.offset); ++ u32 val = readl(pll->status_base + ctrl->status.offset); + + if (val & (1 << ctrl->status.shift)) + return 0; +@@ -145,7 +146,7 @@ static void iproc_pll_write(const struct + writel(val, base + offset); + + if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && +- base == pll->pll_base)) ++ (base == pll->status_base || base == pll->control_base))) + val = readl(base + offset); + } + +@@ -161,9 +162,9 @@ static void __pll_disable(struct iproc_p + } + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { +- val = readl(pll->pll_base + ctrl->aon.offset); ++ val = readl(pll->control_base + ctrl->aon.offset); + val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -184,9 +185,9 @@ static int __pll_enable(struct iproc_pll + u32 val; + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { +- val = readl(pll->pll_base + ctrl->aon.offset); ++ val = readl(pll->control_base + ctrl->aon.offset); + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -213,9 +214,9 @@ static void __pll_put_in_reset(struct ip + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; + +- val = readl(pll->pll_base + reset->offset); ++ val = readl(pll->control_base + reset->offset); + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); +- iproc_pll_write(pll, pll->pll_base, reset->offset, val); ++ iproc_pll_write(pll, pll->control_base, reset->offset, val); + } + + static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, +@@ -226,17 +227,17 @@ static void __pll_bring_out_reset(struct + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; + const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; + +- val = readl(pll->pll_base + dig_filter->offset); ++ val = readl(pll->control_base + dig_filter->offset); + val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | + bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | + bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); + val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | + ka << dig_filter->ka_shift; +- iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); ++ iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); + +- val = readl(pll->pll_base + reset->offset); ++ val = readl(pll->control_base + reset->offset); + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; +- iproc_pll_write(pll, pll->pll_base, reset->offset, val); ++ iproc_pll_write(pll, pll->control_base, reset->offset, val); + } + + static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, +@@ -291,9 +292,9 @@ static int pll_set_rate(struct iproc_clk + /* put PLL in reset */ + __pll_put_in_reset(pll); + +- iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); ++ iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0); + +- val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); ++ val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); + + if (rate >= VCO_LOW && rate < VCO_MID) + val |= (1 << PLL_VCO_LOW_SHIFT); +@@ -303,29 +304,29 @@ static int pll_set_rate(struct iproc_clk + else + val |= (1 << PLL_VCO_HIGH_SHIFT); + +- iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); + + /* program integer part of NDIV */ +- val = readl(pll->pll_base + ctrl->ndiv_int.offset); ++ val = readl(pll->control_base + ctrl->ndiv_int.offset); + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); + val |= vco->ndiv_int << ctrl->ndiv_int.shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); + + /* program fractional part of NDIV */ + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +- val = readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ val = readl(pll->control_base + ctrl->ndiv_frac.offset); + val &= ~(bit_mask(ctrl->ndiv_frac.width) << + ctrl->ndiv_frac.shift); + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, ++ iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset, + val); + } + + /* program PDIV */ +- val = readl(pll->pll_base + ctrl->pdiv.offset); ++ val = readl(pll->control_base + ctrl->pdiv.offset); + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); + val |= vco->pdiv << ctrl->pdiv.shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); + + __pll_bring_out_reset(pll, kp, ka, ki); + +@@ -372,7 +373,7 @@ static unsigned long iproc_pll_recalc_ra + return 0; + + /* PLL needs to be locked */ +- val = readl(pll->pll_base + ctrl->status.offset); ++ val = readl(pll->status_base + ctrl->status.offset); + if ((val & (1 << ctrl->status.shift)) == 0) { + clk->rate = 0; + return 0; +@@ -383,19 +384,19 @@ static unsigned long iproc_pll_recalc_ra + * + * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) + */ +- val = readl(pll->pll_base + ctrl->ndiv_int.offset); ++ val = readl(pll->control_base + ctrl->ndiv_int.offset); + ndiv_int = (val >> ctrl->ndiv_int.shift) & + bit_mask(ctrl->ndiv_int.width); + ndiv = ndiv_int << 20; + + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +- val = readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ val = readl(pll->control_base + ctrl->ndiv_frac.offset); + ndiv_frac = (val >> ctrl->ndiv_frac.shift) & + bit_mask(ctrl->ndiv_frac.width); + ndiv += ndiv_frac; + } + +- val = readl(pll->pll_base + ctrl->pdiv.offset); ++ val = readl(pll->control_base + ctrl->pdiv.offset); + pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); + + clk->rate = (ndiv * parent_rate) >> 20; +@@ -460,14 +461,14 @@ static int iproc_clk_enable(struct clk_h + u32 val; + + /* channel enable is active low */ +- val = readl(pll->pll_base + ctrl->enable.offset); ++ val = readl(pll->control_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.enable_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); + + /* also make sure channel is not held */ +- val = readl(pll->pll_base + ctrl->enable.offset); ++ val = readl(pll->control_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.hold_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); + + return 0; + } +@@ -482,9 +483,9 @@ static void iproc_clk_disable(struct clk + if (ctrl->flags & IPROC_CLK_AON) + return; + +- val = readl(pll->pll_base + ctrl->enable.offset); ++ val = readl(pll->control_base + ctrl->enable.offset); + val |= 1 << ctrl->enable.enable_shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); + } + + static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, +@@ -499,7 +500,7 @@ static unsigned long iproc_clk_recalc_ra + if (parent_rate == 0) + return 0; + +- val = readl(pll->pll_base + ctrl->mdiv.offset); ++ val = readl(pll->control_base + ctrl->mdiv.offset); + mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); + if (mdiv == 0) + mdiv = 256; +@@ -546,14 +547,14 @@ static int iproc_clk_set_rate(struct clk + if (div > 256) + return -EINVAL; + +- val = readl(pll->pll_base + ctrl->mdiv.offset); ++ val = readl(pll->control_base + ctrl->mdiv.offset); + if (div == 256) { + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + } else { + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + val |= div << ctrl->mdiv.shift; + } +- iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); + clk->rate = parent_rate / div; + + return 0; +@@ -578,9 +579,10 @@ static void iproc_pll_sw_cfg(struct ipro + if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { + u32 val; + +- val = readl(pll->pll_base + ctrl->sw_ctrl.offset); ++ val = readl(pll->control_base + ctrl->sw_ctrl.offset); + val |= BIT(ctrl->sw_ctrl.shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset, ++ val); + } + } + +@@ -615,8 +617,8 @@ void __init iproc_pll_clk_setup(struct d + if (WARN_ON(!pll->clks)) + goto err_clks; + +- pll->pll_base = of_iomap(node, 0); +- if (WARN_ON(!pll->pll_base)) ++ pll->control_base = of_iomap(node, 0); ++ if (WARN_ON(!pll->control_base)) + goto err_pll_iomap; + + /* Some SoCs do not require the pwr_base, thus failing is not fatal */ +@@ -629,6 +631,16 @@ void __init iproc_pll_clk_setup(struct d + goto err_asiu_iomap; + } + ++ if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { ++ /* Some SoCs have a split status/control. If this does not ++ * exist, assume they are unified. ++ */ ++ pll->status_base = of_iomap(node, 2); ++ if (!pll->status_base) ++ goto err_status_iomap; ++ } else ++ pll->status_base = pll->control_base; ++ + /* initialize and register the PLL itself */ + pll->ctrl = pll_ctrl; + +@@ -699,6 +711,10 @@ err_clk_register: + clk_unregister(pll->clk_data.clks[i]); + + err_pll_register: ++ if (pll->status_base != pll->control_base) ++ iounmap(pll->status_base); ++ ++err_status_iomap: + if (pll->asiu_base) + iounmap(pll->asiu_base); + +@@ -706,7 +722,7 @@ err_asiu_iomap: + if (pll->pwr_base) + iounmap(pll->pwr_base); + +- iounmap(pll->pll_base); ++ iounmap(pll->control_base); + + err_pll_iomap: + kfree(pll->clks); +--- a/drivers/clk/bcm/clk-iproc.h ++++ b/drivers/clk/bcm/clk-iproc.h +@@ -55,6 +55,12 @@ + #define IPROC_CLK_EMBED_PWRCTRL BIT(5) + + /* ++ * Some PLLs have separate registers for Status and Control. Identify this to ++ * let the driver know if additional registers need to be used ++ */ ++#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6) ++ ++/* + * Parameters for VCO frequency configuration + * + * VCO frequency = diff --git a/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch b/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch new file mode 100644 index 0000000..a9a5246 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch @@ -0,0 +1,153 @@ +From e96ef422d0095fe9ae39b03c0805a0db8ff7e382 Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Tue, 13 Oct 2015 17:22:25 -0400 +Subject: [PATCH 50/50] ARM: dts: enable clock support for BCM5301X + +Replace current device tree dummy clocks with real clock support for +Broadcom Northstar SoCs. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++--------- + 1 file changed, 69 insertions(+), 19 deletions(-) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -8,6 +8,7 @@ + * Licensed under the GNU/GPL. See COPYING for details. + */ + ++#include <dt-bindings/clock/bcm-nsp.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> +@@ -42,41 +43,48 @@ + + mpcore { + compatible = "simple-bus"; +- ranges = <0x00000000 0x19020000 0x00003000>; ++ ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + +- scu@0000 { ++ a9pll: arm_clk@00000 { ++ #clock-cells = <0>; ++ compatible = "brcm,nsp-armpll"; ++ clocks = <&osc>; ++ reg = <0x00000 0x1000>; ++ }; ++ ++ scu@20000 { + compatible = "arm,cortex-a9-scu"; +- reg = <0x0000 0x100>; ++ reg = <0x20000 0x100>; + }; + +- timer@0200 { ++ timer@20200 { + compatible = "arm,cortex-a9-global-timer"; +- reg = <0x0200 0x100>; ++ reg = <0x20200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk_periph>; ++ clocks = <&periph_clk>; + }; + +- local-timer@0600 { ++ local-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x0600 0x100>; ++ reg = <0x20600 0x100>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk_periph>; ++ clocks = <&periph_clk>; + }; + +- gic: interrupt-controller@1000 { ++ gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +- reg = <0x1000 0x1000>, +- <0x0100 0x100>; ++ reg = <0x21000 0x1000>, ++ <0x20100 0x100>; + }; + +- L2: cache-controller@2000 { ++ L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; +- reg = <0x2000 0x1000>; ++ reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; +@@ -94,14 +102,37 @@ + + clocks { + #address-cells = <1>; +- #size-cells = <0>; ++ #size-cells = <1>; ++ ranges; + +- /* As long as we do not have a real clock driver us this +- * fixed clock */ +- clk_periph: periph { ++ osc: oscillator { ++ #clock-cells = <0>; + compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++ }; ++ ++ iprocmed: iprocmed { + #clock-cells = <0>; +- clock-frequency = <400000000>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; ++ clock-div = <2>; ++ clock-mult = <1>; ++ }; ++ ++ iprocslow: iprocslow { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ ++ periph_clk: periph_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&a9pll>; ++ clock-div = <2>; ++ clock-mult = <1>; + }; + }; + +@@ -189,4 +220,23 @@ + + brcm,nand-has-wp; + }; ++ ++ lcpll0: lcpll0@1800c100 { ++ #clock-cells = <1>; ++ compatible = "brcm,nsp-lcpll0"; ++ reg = <0x1800c100 0x14>; ++ clocks = <&osc>; ++ clock-output-names = "lcpll0", "pcie_phy", "sdio", ++ "ddr_phy"; ++ }; ++ ++ genpll: genpll@1800c140 { ++ #clock-cells = <1>; ++ compatible = "brcm,nsp-genpll"; ++ reg = <0x1800c140 0x24>; ++ clocks = <&osc>; ++ clock-output-names = "genpll", "phy", "ethernetclk", ++ "usbclk", "iprocfast", "sata1", ++ "sata2"; ++ }; + }; diff --git a/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch b/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch new file mode 100644 index 0000000..ccb8e27 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch @@ -0,0 +1,32 @@ +From af8fe7176ec13de08b1bfb7ea2ae9cc147b2429a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 12 Sep 2015 12:56:37 +0200 +Subject: [PATCH] ARM: BCM5301X: add NAND flash chip description for Asus + RT-AC87U + +The NAND flash chip description were not imported for the Asus RT-AC87U +dts file when this was done for all the other dts files, because these +patches were send in parallel. + +This adds a missing NAND flash chip description to this patch: +commit 9faa5960eef3204cae6637b530f5e23e53b5a9ef +Author: Hauke Mehrtens <hauke@hauke-m.de> +Date: Fri May 29 23:39:47 2015 +0200 + +ARM: BCM5301X: add NAND flash chip description + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; diff --git a/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch b/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch new file mode 100644 index 0000000..044fb80 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch @@ -0,0 +1,128 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Wed, 26 Aug 2015 16:11:38 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7000 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ ++ bcm4709-netgear-r7000.dtb \ + bcm4709-netgear-r8000.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -0,0 +1,106 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Netgear R7000 ++ * ++ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; ++ model = "Netgear R7000"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power-white { ++ label = "bcm53xx:white:power"; ++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ power-amber { ++ label = "bcm53xx:amber:power"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 5ghz { ++ label = "bcm53xx:white:5ghz"; ++ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 2ghz { ++ label = "bcm53xx:white:2ghz"; ++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wireless { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = <KEY_WPS_BUTTON>; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ rfkill { ++ label = "WiFi"; ++ linux,code = <KEY_RFKILL>; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch b/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch new file mode 100644 index 0000000..0dae7c9 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch @@ -0,0 +1,218 @@ +From a0aef7fbab0d8b5a0d445c74990e5233beda246e Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Wed, 21 Oct 2015 18:46:04 -0400 +Subject: [PATCH] ARM: dts: bcm5301x: Add BCM SVK DT files + +Add device tree files for Broadcom Northstar based SVKs. Since the +bcm5301x.dtsi already exists, all that is necessary is the dts files to +enable the UARTs. With these files, the SVKs are able to boot to shell. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + arch/arm/boot/dts/Makefile | 5 +++- + arch/arm/boot/dts/bcm94708.dts | 56 +++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm94709.dts | 56 +++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm953012k.dts | 63 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 179 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/bcm94708.dts + create mode 100644 arch/arm/boot/dts/bcm94709.dts + create mode 100644 arch/arm/boot/dts/bcm953012k.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -73,7 +73,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-netgear-r7000.dtb \ +- bcm4709-netgear-r8000.dtb ++ bcm4709-netgear-r8000.dtb \ ++ bcm94708.dtb \ ++ bcm94709.dtb \ ++ bcm953012k.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb + dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm94708.dts +@@ -0,0 +1,56 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM94708)"; ++ compatible = "brcm,bcm94708", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm94709.dts +@@ -0,0 +1,56 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM94709)"; ++ compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm953012k.dts +@@ -0,0 +1,63 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM953012K)"; ++ compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x10000000>; ++ }; ++}; ++ ++&uart0 { ++ clock-frequency = <62499840>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ clock-frequency = <62499840>; ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch b/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch new file mode 100644 index 0000000..8d48673 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi ++++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +@@ -19,6 +19,8 @@ + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; ++ ++ linux,part-probe = "ofpart", "bcm47xxpart"; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-4.3/112-bcm53xx-sprom-add-sprom-driver.patch b/target/linux/bcm53xx/patches-4.3/112-bcm53xx-sprom-add-sprom-driver.patch new file mode 100644 index 0000000..70ab039 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/112-bcm53xx-sprom-add-sprom-driver.patch @@ -0,0 +1,69 @@ +From 4e0ab3269a6d260a41a3673157753147f5f71341 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sun, 4 May 2014 13:19:20 +0200 +Subject: [PATCH 03/17] bcm47xx-sprom: add Broadcom sprom parser driver + +This driver needs an nvram driver and fetches the sprom values from the +nvram and provides it to any other driver. The calibration data for the +wifi chip the mac address and some more board description data is +stores in the sprom. + +This is based on a copy of arch/mips/bcm47xx/sprom.c and my plan is to +make the bcm47xx MIPS SoCs also use this driver some time later. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + .../devicetree/bindings/misc/bcm47xx-sprom.txt | 16 + + drivers/misc/Kconfig | 11 + + drivers/misc/Makefile | 1 + + drivers/misc/bcm47xx-sprom.c | 690 +++++++++++++++++++++ + 4 files changed, 718 insertions(+) + create mode 100644 Documentation/devicetree/bindings/misc/bcm47xx-sprom.txt + create mode 100644 drivers/misc/bcm47xx-sprom.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/misc/bcm47xx-sprom.txt +@@ -0,0 +1,16 @@ ++Broadcom bcm47xx/bcm53xx sprom converter ++ ++This driver provbides an sprom based on a given nvram. ++ ++Required properties: ++ ++- compatible : brcm,bcm47xx-sprom ++ ++- nvram : reference to a nvram driver, e.g. bcm47xx-nvram ++ ++Example: ++ ++sprom0: sprom@0 { ++ compatible = "brcm,bcm47xx-sprom"; ++ nvram = <&nvram0>; ++}; +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -525,6 +525,17 @@ config VEXPRESS_SYSCFG + bus. System Configuration interface is one of the possible means + of generating transactions on this bus. + ++config BCM47XX_SPROM ++ tristate "BCM47XX sprom driver" ++ help ++ This driver parses the sprom from a given nvram which is found on ++ Broadcom bcm47xx and bcm53xx SoCs. ++ ++ The sprom contains board configuration data like the ++ calibration data fro the wifi chips, the mac addresses used ++ by the board and many other board configuration data. This ++ driver will provide the sprom to bcma. ++ + source "drivers/misc/c2port/Kconfig" + source "drivers/misc/eeprom/Kconfig" + source "drivers/misc/cb710/Kconfig" +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -56,3 +56,4 @@ obj-$(CONFIG_GENWQE) += genwqe/ + obj-$(CONFIG_ECHO) += echo/ + obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o + obj-$(CONFIG_CXL_BASE) += cxl/ ++obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx-sprom.o diff --git a/target/linux/bcm53xx/patches-4.3/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.3/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch new file mode 100644 index 0000000..5e3bd77 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch @@ -0,0 +1,635 @@ +From a0ad1511d5805b95ac4c454d7904c670a1696055 Mon Sep 17 00:00:00 2001 +From: Kapil Hali <kapilh@broadcom.com> +Date: Wed, 14 Oct 2015 13:47:00 -0400 +Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom NSP + +Add SMP support for Broadcom's Northstar Plus SoC, +cpu enable method and pen_release procedures. This +changes also consolidates iProc family's - BCM NSP +and BCM Kona, SMP handling in a common file. + +Northstar Plus SoC is based on ARM Cortex-A9 +revision r3p0 which requires configuration for ARM +Errata 764369 for SMP. This change adds the needed +configuration option. + +Signed-off-by: Kapil Hali <kapilh@broadcom.com> +--- + arch/arm/mach-bcm/Makefile | 2 +- + arch/arm/mach-bcm/bcm_nsp.h | 19 +++ + arch/arm/mach-bcm/headsmp.S | 37 +++++ + arch/arm/mach-bcm/kona_smp.c | 202 --------------------------- + arch/arm/mach-bcm/platsmp.c | 326 +++++++++++++++++++++++++++++++++++++++++++ + 5 files changed, 383 insertions(+), 203 deletions(-) + create mode 100644 arch/arm/mach-bcm/bcm_nsp.h + create mode 100644 arch/arm/mach-bcm/headsmp.S + delete mode 100644 arch/arm/mach-bcm/kona_smp.c + create mode 100644 arch/arm/mach-bcm/platsmp.c + +--- a/arch/arm/mach-bcm/Makefile ++++ b/arch/arm/mach-bcm/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bc + obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o + + # BCM281XX and BCM21664 SMP support +-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o ++obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o + + # BCM281XX and BCM21664 L2 cache control + obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o +--- /dev/null ++++ b/arch/arm/mach-bcm/bcm_nsp.h +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __BCM_NSP_H ++#define __BCM_NSP_H ++ ++extern void nsp_secondary_startup(void); ++ ++#endif /* __BCM_NSP_H */ +--- /dev/null ++++ b/arch/arm/mach-bcm/headsmp.S +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/linkage.h> ++ ++/* ++ * iProc specific entry point for secondary CPUs. This provides ++ * a "holding pen" into which all secondary cores are held until ++ * we are ready for them to initialise. ++ */ ++ENTRY(nsp_secondary_startup) ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ b secondary_startup ++ ++1: .long . ++ .long pen_release ++ ++ENDPROC(nsp_secondary_startup) +--- a/arch/arm/mach-bcm/kona_smp.c ++++ /dev/null +@@ -1,202 +0,0 @@ +-/* +- * Copyright (C) 2014 Broadcom Corporation +- * Copyright 2014 Linaro Limited +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <linux/init.h> +-#include <linux/errno.h> +-#include <linux/io.h> +-#include <linux/of.h> +-#include <linux/sched.h> +- +-#include <asm/smp.h> +-#include <asm/smp_plat.h> +-#include <asm/smp_scu.h> +- +-/* Size of mapped Cortex A9 SCU address space */ +-#define CORTEX_A9_SCU_SIZE 0x58 +- +-#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ +-#define BOOT_ADDR_CPUID_MASK 0x3 +- +-/* Name of device node property defining secondary boot register location */ +-#define OF_SECONDARY_BOOT "secondary-boot-reg" +- +-/* I/O address of register used to coordinate secondary core startup */ +-static u32 secondary_boot; +- +-/* +- * Enable the Cortex A9 Snoop Control Unit +- * +- * By the time this is called we already know there are multiple +- * cores present. We assume we're running on a Cortex A9 processor, +- * so any trouble getting the base address register or getting the +- * SCU base is a problem. +- * +- * Return 0 if successful or an error code otherwise. +- */ +-static int __init scu_a9_enable(void) +-{ +- unsigned long config_base; +- void __iomem *scu_base; +- +- if (!scu_a9_has_base()) { +- pr_err("no configuration base address register!\n"); +- return -ENXIO; +- } +- +- /* Config base address register value is zero for uniprocessor */ +- config_base = scu_a9_get_base(); +- if (!config_base) { +- pr_err("hardware reports only one core\n"); +- return -ENOENT; +- } +- +- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); +- if (!scu_base) { +- pr_err("failed to remap config base (%lu/%u) for SCU\n", +- config_base, CORTEX_A9_SCU_SIZE); +- return -ENOMEM; +- } +- +- scu_enable(scu_base); +- +- iounmap(scu_base); /* That's the last we'll need of this */ +- +- return 0; +-} +- +-static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) +-{ +- static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; +- struct device_node *node; +- int ret; +- +- BUG_ON(secondary_boot); /* We're called only once */ +- +- /* +- * This function is only called via smp_ops->smp_prepare_cpu(). +- * That only happens if a "/cpus" device tree node exists +- * and has an "enable-method" property that selects the SMP +- * operations defined herein. +- */ +- node = of_find_node_by_path("/cpus"); +- BUG_ON(!node); +- +- /* +- * Our secondary enable method requires a "secondary-boot-reg" +- * property to specify a register address used to request the +- * ROM code boot a secondary code. If we have any trouble +- * getting this we fall back to uniprocessor mode. +- */ +- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { +- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", +- node->name); +- ret = -ENOENT; /* Arrange to disable SMP */ +- goto out; +- } +- +- /* +- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is +- * returned, the SoC reported a uniprocessor configuration. +- * We bail on any other error. +- */ +- ret = scu_a9_enable(); +-out: +- of_node_put(node); +- if (ret) { +- /* Update the CPU present map to reflect uniprocessor mode */ +- BUG_ON(ret != -ENOENT); +- pr_warn("disabling SMP\n"); +- init_cpu_present(&only_cpu_0); +- } +-} +- +-/* +- * The ROM code has the secondary cores looping, waiting for an event. +- * When an event occurs each core examines the bottom two bits of the +- * secondary boot register. When a core finds those bits contain its +- * own core id, it performs initialization, including computing its boot +- * address by clearing the boot register value's bottom two bits. The +- * core signals that it is beginning its execution by writing its boot +- * address back to the secondary boot register, and finally jumps to +- * that address. +- * +- * So to start a core executing we need to: +- * - Encode the (hardware) CPU id with the bottom bits of the secondary +- * start address. +- * - Write that value into the secondary boot register. +- * - Generate an event to wake up the secondary CPU(s). +- * - Wait for the secondary boot register to be re-written, which +- * indicates the secondary core has started. +- */ +-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) +-{ +- void __iomem *boot_reg; +- phys_addr_t boot_func; +- u64 start_clock; +- u32 cpu_id; +- u32 boot_val; +- bool timeout = false; +- +- cpu_id = cpu_logical_map(cpu); +- if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { +- pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); +- return -EINVAL; +- } +- +- if (!secondary_boot) { +- pr_err("required secondary boot register not specified\n"); +- return -EINVAL; +- } +- +- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); +- if (!boot_reg) { +- pr_err("unable to map boot register for cpu %u\n", cpu_id); +- return -ENOSYS; +- } +- +- /* +- * Secondary cores will start in secondary_startup(), +- * defined in "arch/arm/kernel/head.S" +- */ +- boot_func = virt_to_phys(secondary_startup); +- BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); +- BUG_ON(boot_func > (phys_addr_t)U32_MAX); +- +- /* The core to start is encoded in the low bits */ +- boot_val = (u32)boot_func | cpu_id; +- writel_relaxed(boot_val, boot_reg); +- +- sev(); +- +- /* The low bits will be cleared once the core has started */ +- start_clock = local_clock(); +- while (!timeout && readl_relaxed(boot_reg) == boot_val) +- timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; +- +- iounmap(boot_reg); +- +- if (!timeout) +- return 0; +- +- pr_err("timeout waiting for cpu %u to start\n", cpu_id); +- +- return -ENOSYS; +-} +- +-static struct smp_operations bcm_smp_ops __initdata = { +- .smp_prepare_cpus = bcm_smp_prepare_cpus, +- .smp_boot_secondary = bcm_boot_secondary, +-}; +-CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", +- &bcm_smp_ops); +--- /dev/null ++++ b/arch/arm/mach-bcm/platsmp.c +@@ -0,0 +1,326 @@ ++/* ++ * Copyright (C) 2014-2015 Broadcom Corporation ++ * Copyright 2014 Linaro Limited ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/cpumask.h> ++#include <linux/delay.h> ++#include <linux/errno.h> ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/jiffies.h> ++#include <linux/of.h> ++#include <linux/sched.h> ++#include <linux/smp.h> ++ ++#include <asm/cacheflush.h> ++#include <asm/smp.h> ++#include <asm/smp_plat.h> ++#include <asm/smp_scu.h> ++ ++#include "bcm_nsp.h" ++ ++/* Size of mapped Cortex A9 SCU address space */ ++#define CORTEX_A9_SCU_SIZE 0x58 ++ ++#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ ++#define BOOT_ADDR_CPUID_MASK 0x3 ++ ++/* Name of device node property defining secondary boot register location */ ++#define OF_SECONDARY_BOOT "secondary-boot-reg" ++ ++/* I/O address of register used to coordinate secondary core startup */ ++static u32 secondary_boot; ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++static void write_pen_release(int val) ++{ ++ pen_release = val; ++ /* ++ * Ensure write to pen_release is visible to the other cores, ++ * here - primary core ++ */ ++ smp_wmb(); ++ sync_cache_w(&pen_release); ++} ++ ++/* ++ * Enable the Cortex A9 Snoop Control Unit ++ * ++ * By the time this is called we already know there are multiple ++ * cores present. We assume we're running on a Cortex A9 processor, ++ * so any trouble getting the base address register or getting the ++ * SCU base is a problem. ++ * ++ * Return 0 if successful or an error code otherwise. ++ */ ++static int __init scu_a9_enable(void) ++{ ++ unsigned long config_base; ++ void __iomem *scu_base; ++ ++ if (!scu_a9_has_base()) { ++ pr_err("no configuration base address register!\n"); ++ return -ENXIO; ++ } ++ ++ /* Config base address register value is zero for uniprocessor */ ++ config_base = scu_a9_get_base(); ++ if (!config_base) { ++ pr_err("hardware reports only one core\n"); ++ return -ENOENT; ++ } ++ ++ scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); ++ if (!scu_base) { ++ pr_err("failed to remap config base (%lu/%u) for SCU\n", ++ config_base, CORTEX_A9_SCU_SIZE); ++ return -ENOMEM; ++ } ++ ++ scu_enable(scu_base); ++ ++ iounmap(scu_base); /* That's the last we'll need of this */ ++ ++ return 0; ++} ++ ++static int nsp_write_lut(void (*secondary_startup) (void)) ++{ ++ void __iomem *sku_rom_lut; ++ phys_addr_t secondary_startup_phy; ++ ++ if (!secondary_boot) { ++ pr_warn("required secondary boot register not specified\n"); ++ return -EINVAL; ++ } ++ ++ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot, ++ sizeof(secondary_boot)); ++ if (!sku_rom_lut) { ++ pr_warn("unable to ioremap SKU-ROM LUT register\n"); ++ return -ENOMEM; ++ } ++ ++ secondary_startup_phy = virt_to_phys(secondary_startup); ++ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); ++ ++ writel_relaxed(secondary_startup_phy, sku_rom_lut); ++ /* ++ * Ensure the write is visible to the secondary core. ++ */ ++ smp_wmb(); ++ ++ iounmap(sku_rom_lut); ++ ++ return 0; ++} ++ ++static void nsp_secondary_init(unsigned int cpu) ++{ ++ /* ++ * Let the primary cpu know we are out of holding pen. ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; ++ struct device_node *node; ++ int ret; ++ ++ BUG_ON(secondary_boot); /* We're called only once */ ++ ++ /* ++ * This function is only called via smp_ops->smp_prepare_cpu(). ++ * That only happens if a "/cpus" device tree node exists ++ * and has an "enable-method" property that selects the SMP ++ * operations defined herein. ++ */ ++ node = of_find_node_by_path("/cpus"); ++ BUG_ON(!node); ++ ++ /* ++ * Our secondary enable method requires a "secondary-boot-reg" ++ * property to specify a register address used to request the ++ * ROM code boot a secondary core. If we have any trouble ++ * getting this we fall back to uniprocessor mode. ++ */ ++ if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { ++ pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", ++ node->name); ++ ret = -ENOENT; /* Arrange to disable SMP */ ++ goto out; ++ } ++ ++ /* ++ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is ++ * returned, the SoC reported a uniprocessor configuration. ++ * We bail on any other error. ++ */ ++ ret = scu_a9_enable(); ++out: ++ of_node_put(node); ++ if (ret) { ++ /* Update the CPU present map to reflect uniprocessor mode */ ++ pr_warn("disabling SMP\n"); ++ init_cpu_present(&only_cpu_0); ++ } ++} ++ ++/* ++ * The ROM code has the secondary cores looping, waiting for an event. ++ * When an event occurs each core examines the bottom two bits of the ++ * secondary boot register. When a core finds those bits contain its ++ * own core id, it performs initialization, including computing its boot ++ * address by clearing the boot register value's bottom two bits. The ++ * core signals that it is beginning its execution by writing its boot ++ * address back to the secondary boot register, and finally jumps to ++ * that address. ++ * ++ * So to start a core executing we need to: ++ * - Encode the (hardware) CPU id with the bottom bits of the secondary ++ * start address. ++ * - Write that value into the secondary boot register. ++ * - Generate an event to wake up the secondary CPU(s). ++ * - Wait for the secondary boot register to be re-written, which ++ * indicates the secondary core has started. ++ */ ++static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ void __iomem *boot_reg; ++ phys_addr_t boot_func; ++ u64 start_clock; ++ u32 cpu_id; ++ u32 boot_val; ++ bool timeout = false; ++ ++ cpu_id = cpu_logical_map(cpu); ++ if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { ++ pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); ++ return -EINVAL; ++ } ++ ++ if (!secondary_boot) { ++ pr_err("required secondary boot register not specified\n"); ++ return -EINVAL; ++ } ++ ++ boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); ++ if (!boot_reg) { ++ pr_err("unable to map boot register for cpu %u\n", cpu_id); ++ return -ENOMEM; ++ } ++ ++ /* ++ * Secondary cores will start in secondary_startup(), ++ * defined in "arch/arm/kernel/head.S" ++ */ ++ boot_func = virt_to_phys(secondary_startup); ++ BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); ++ BUG_ON(boot_func > (phys_addr_t)U32_MAX); ++ ++ /* The core to start is encoded in the low bits */ ++ boot_val = (u32)boot_func | cpu_id; ++ writel_relaxed(boot_val, boot_reg); ++ ++ sev(); ++ ++ /* The low bits will be cleared once the core has started */ ++ start_clock = local_clock(); ++ while (!timeout && readl_relaxed(boot_reg) == boot_val) ++ timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; ++ ++ iounmap(boot_reg); ++ ++ if (!timeout) ++ return 0; ++ ++ pr_err("timeout waiting for cpu %u to start\n", cpu_id); ++ ++ return -ENXIO; ++} ++ ++static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ unsigned long timeout; ++ int ret; ++ ++ /* ++ * After wake up, secondary core branches to the startup ++ * address programmed at SKU ROM LUT location. ++ */ ++ ret = nsp_write_lut(nsp_secondary_startup); ++ if (ret) { ++ pr_err("unable to write startup addr to SKU ROM LUT\n"); ++ goto out; ++ } ++ ++ /* ++ * The secondary processor is waiting to be released from ++ * the holding pen - release it, then wait for it to flag ++ * that it has been released by resetting pen_release. ++ */ ++ spin_lock(&boot_lock); ++ ++ write_pen_release(cpu_logical_map(cpu)); ++ /* ++ * Send an Event to wake up the secondary core which is in ++ * WFE state. Updated pen_release should also be visible to ++ * the secondary core. ++ */ ++ dsb_sev(); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ /* Make sure loads on other CPU is visible */ ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ spin_unlock(&boot_lock); ++ ++ ret = pen_release != -1 ? -ENXIO : 0; ++ ++out: ++ return ret; ++} ++ ++static struct smp_operations bcm_smp_ops __initdata = { ++ .smp_prepare_cpus = bcm_smp_prepare_cpus, ++ .smp_boot_secondary = kona_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", ++ &bcm_smp_ops); ++ ++struct smp_operations nsp_smp_ops __initdata = { ++ .smp_prepare_cpus = bcm_smp_prepare_cpus, ++ .smp_secondary_init = nsp_secondary_init, ++ .smp_boot_secondary = nsp_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); diff --git a/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch b/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch new file mode 100644 index 0000000..ad1c771 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch @@ -0,0 +1,50 @@ +From ddbf0ad85be06948dd214c7beb7b315ef2749e65 Mon Sep 17 00:00:00 2001 +From: Jon Mason <jonmason@broadcom.com> +Date: Thu, 15 Oct 2015 14:14:10 -0400 +Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom 4708 + +ARM: BCM: Add SMP support for Broadcom 4708 + +Add SMP support for Broadcom's 4708 SoCs. + +Signed-off-by: Jon Mason <jonmason@broadcom.com> +--- + arch/arm/boot/dts/bcm4708.dtsi | 2 ++ + arch/arm/mach-bcm/Kconfig | 2 ++ + arch/arm/mach-bcm/Makefile | 3 +++ + 3 files changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708.dtsi ++++ b/arch/arm/boot/dts/bcm4708.dtsi +@@ -15,6 +15,8 @@ + cpus { + #address-cells = <1>; + #size-cells = <0>; ++ enable-method = "brcm,bcm-nsp-smp"; ++ secondary-boot-reg = <0xffff0400>; + + cpu@0 { + device_type = "cpu"; +--- a/arch/arm/mach-bcm/Kconfig ++++ b/arch/arm/mach-bcm/Kconfig +@@ -38,6 +38,8 @@ config ARCH_BCM_CYGNUS + config ARCH_BCM_5301X + bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 + select ARCH_BCM_IPROC ++ select ARM_ERRATA_764369 if SMP ++ select HAVE_SMP + help + Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. + +--- a/arch/arm/mach-bcm/Makefile ++++ b/arch/arm/mach-bcm/Makefile +@@ -36,6 +36,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2 + + # BCM5301X + obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++obj-$(CONFIG_SMP) += headsmp.o platsmp.o ++endif + + # BCM63XXx + ifeq ($(CONFIG_ARCH_BCM_63XX),y) diff --git a/target/linux/bcm53xx/patches-4.3/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch b/target/linux/bcm53xx/patches-4.3/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch new file mode 100644 index 0000000..c117774 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch @@ -0,0 +1,57 @@ +From b58682598541262f967ecd6db04bacac38026d3c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Fri, 30 Oct 2015 15:29:52 +0100 +Subject: [PATCH] ARM: BCM5301X: Add missing Netgear R8000 LEDs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 30 +++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +index 446c586..b52927c 100644 +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -50,6 +50,36 @@ + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; ++ ++ wireless { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 5ghz-2 { ++ label = "bcm53xx:white:5ghz-2"; ++ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; + }; + + gpio-keys { +-- +1.8.4.5 + diff --git a/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch b/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch new file mode 100644 index 0000000..5031886 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch @@ -0,0 +1,75 @@ +From 0cb136f9882e4649ad6160bb7b48955ff728888c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Sun, 1 Nov 2015 08:17:21 +0100 +Subject: [PATCH V2] USB: bcma: switch to GPIO descriptor for power control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +So far we were using simple (legacy) GPIO functions & some poor logic to +control power. It got many drawbacks: we were ignoring OF flags +(GPIO_ACTIVE_LOW), we were not setting direction to output and we were +assuming gpio_request success all the time. +Fix it by switching to gpiod functions and adding appropriate checks. + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + drivers/usb/host/bcma-hcd.c | 21 ++++++++++----------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c +index 5398e3d..291aaa2 100644 +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -21,6 +21,7 @@ + */ + #include <linux/bcma/bcma.h> + #include <linux/delay.h> ++#include <linux/gpio/consumer.h> + #include <linux/platform_device.h> + #include <linux/module.h> + #include <linux/slab.h> +@@ -36,6 +37,7 @@ MODULE_LICENSE("GPL"); + struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; ++ struct gpio_desc *gpio_desc; + }; + + /* Wait for bitmask in a register to get set or cleared. +@@ -228,19 +230,12 @@ static void bcma_hcd_init_chip_arm(struct bcma_device *dev) + + static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val) + { +- int gpio; ++ struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + +- gpio = of_get_named_gpio(dev->dev.of_node, "vcc-gpio", 0); +- if (!gpio_is_valid(gpio)) ++ if (IS_ERR_OR_NULL(usb_dev->gpio_desc)) + return; + +- if (val) { +- gpio_request(gpio, "bcma-hcd-gpio"); +- gpio_set_value(gpio, 1); +- } else { +- gpio_set_value(gpio, 0); +- gpio_free(gpio); +- } ++ gpiod_set_value(usb_dev->gpio_desc, val); + } + + static const struct usb_ehci_pdata ehci_pdata = { +@@ -314,7 +309,11 @@ static int bcma_hcd_probe(struct bcma_device *dev) + if (!usb_dev) + return -ENOMEM; + +- bcma_hci_platform_power_gpio(dev, true); ++ if (dev->dev.of_node) ++ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", ++ &dev->dev.of_node->fwnode); ++ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) ++ gpiod_direction_output(usb_dev->gpio_desc, 1); + + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: diff --git a/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch b/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch new file mode 100644 index 0000000..a769650 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch @@ -0,0 +1,63 @@ +From 1420e53fc88673683f8990aa5342e7b2640ce165 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sun, 18 Oct 2015 19:13:27 +0200 +Subject: [PATCH v3 1/6] usb: xhci: plat: fix adding usb3-lpm-capable quirk + +The xhci->quirks member is overwritten in xhci_gen_setup() with the +quirks given through the module load parameter. Without this patch the +usb3-lpm-capable quirk will be over written before it gets used. This +patch moves the quirks code to the xhci_plat_quirks() callback function +which gets called directly after the quirks member variable is +overwritten with the module load parameter. + +I do not have any hardware which is using usb3-lpm-capabls so I can not +test this on real hardware. + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/usb/host/xhci-plat.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -37,12 +37,20 @@ static const struct xhci_driver_override + + static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) + { ++ struct platform_device *pdev = to_platform_device(dev); ++ struct device_node *node = pdev->dev.of_node; ++ struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); ++ + /* + * As of now platform drivers don't provide MSI support so we ensure + * here that the generic code does not try to make a pci_dev from our + * dev struct in order to setup MSI + */ + xhci->quirks |= XHCI_PLAT; ++ ++ if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || ++ (pdata && pdata->usb3_lpm_capable)) ++ xhci->quirks |= XHCI_LPM_SUPPORT; + } + + /* called during probe() after chip reset completes */ +@@ -74,8 +82,6 @@ static int xhci_plat_start(struct usb_hc + + static int xhci_plat_probe(struct platform_device *pdev) + { +- struct device_node *node = pdev->dev.of_node; +- struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); + const struct hc_driver *driver; + struct xhci_hcd *xhci; + struct resource *res; +@@ -148,10 +154,6 @@ static int xhci_plat_probe(struct platfo + goto disable_clk; + } + +- if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || +- (pdata && pdata->usb3_lpm_capable)) +- xhci->quirks |= XHCI_LPM_SUPPORT; +- + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) + xhci->shared_hcd->can_do_streams = 1; + diff --git a/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch b/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch new file mode 100644 index 0000000..ae70f42 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch @@ -0,0 +1,135 @@ +From dd0e5f9a6a4aed849bdb80641c2a2350476cede7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Sun, 21 Jun 2015 11:10:49 +0200 +Subject: [PATCH v3 2/6] usb: xhci: add Broadcom specific fake doorbell +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes problem with controller seeing devices only in some small +percentage of cold boots. +This quirk is also added to the platform data so we can activate it +when we register our platform driver. + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/usb/host/xhci-plat.c | 3 +++ + drivers/usb/host/xhci.c | 57 +++++++++++++++++++++++++++++++++++++--- + drivers/usb/host/xhci.h | 1 + + include/linux/usb/xhci_pdriver.h | 1 + + 4 files changed, 59 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -51,6 +51,9 @@ static void xhci_plat_quirks(struct devi + if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || + (pdata && pdata->usb3_lpm_capable)) + xhci->quirks |= XHCI_LPM_SUPPORT; ++ ++ if (pdata && pdata->usb3_fake_doorbell) ++ xhci->quirks |= XHCI_FAKE_DOORBELL; + } + + /* called during probe() after chip reset completes */ +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -121,6 +121,39 @@ int xhci_halt(struct xhci_hcd *xhci) + return ret; + } + ++static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id) ++{ ++ u32 temp; ++ ++ /* alloc a virt device for slot */ ++ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) { ++ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); ++ return -ENOMEM; ++ } ++ ++ /* ring fake doorbell for slot_id ep 0 */ ++ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0); ++ usleep_range(1000, 1500); ++ ++ /* read the status register to check if HSE is set or not? */ ++ temp = readl(&xhci->op_regs->status); ++ ++ /* clear HSE if set */ ++ if (temp & STS_FATAL) { ++ xhci_dbg(xhci, "HSE problem detected, status: 0x%x\n", temp); ++ temp &= ~(0x1fff); ++ temp |= STS_FATAL; ++ writel(temp, &xhci->op_regs->status); ++ usleep_range(1000, 1500); ++ readl(&xhci->op_regs->status); ++ } ++ ++ /* Free virt device */ ++ xhci_free_virt_device(xhci, slot_id); ++ ++ return 0; ++} ++ + /* + * Set the run bit and wait for the host to be running. + */ +@@ -557,10 +590,25 @@ int xhci_init(struct usb_hcd *hcd) + + static int xhci_run_finished(struct xhci_hcd *xhci) + { +- if (xhci_start(xhci)) { +- xhci_halt(xhci); +- return -ENODEV; ++ int err; ++ ++ err = xhci_start(xhci); ++ if (err) { ++ err = -ENODEV; ++ goto out_err; ++ } ++ if (xhci->quirks & XHCI_FAKE_DOORBELL) { ++ err = xhci_fake_doorbell(xhci, 1); ++ if (err) ++ goto out_err; ++ ++ err = xhci_start(xhci); ++ if (err) { ++ err = -ENODEV; ++ goto out_err; ++ } + } ++ + xhci->shared_hcd->state = HC_STATE_RUNNING; + xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; + +@@ -570,6 +618,9 @@ static int xhci_run_finished(struct xhci + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Finished xhci_run for USB3 roothub"); + return 0; ++out_err: ++ xhci_halt(xhci); ++ return err; + } + + /* +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1575,6 +1575,7 @@ struct xhci_hcd { + /* For controllers with a broken beyond repair streams implementation */ + #define XHCI_BROKEN_STREAMS (1 << 19) + #define XHCI_PME_STUCK_QUIRK (1 << 20) ++#define XHCI_FAKE_DOORBELL (1 << 21) + unsigned int num_active_eps; + unsigned int limit_active_eps; + /* There are two roothubs to keep track of bus suspend info for */ +--- a/include/linux/usb/xhci_pdriver.h ++++ b/include/linux/usb/xhci_pdriver.h +@@ -22,6 +22,7 @@ + */ + struct usb_xhci_pdata { + unsigned usb3_lpm_capable:1; ++ unsigned usb3_fake_doorbell:1; + }; + + #endif /* __USB_CORE_XHCI_PDRIVER_H */ diff --git a/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch b/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch new file mode 100644 index 0000000..17a9260 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch @@ -0,0 +1,75 @@ +From c7c7bf7fcbacadac7781783de25fe1e13e2a2c35 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Tue, 16 Jun 2015 12:33:46 +0200 +Subject: [PATCH v3 3/6] usb: bcma: make helper creating platform dev more + generic +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Having "bool ohci" argument bounded us to two cases only and didn't +allow re-using this code for XHCI. + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/usb/host/bcma-hcd.c | 24 +++++++++++++----------- + 1 file changed, 13 insertions(+), 11 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -244,7 +244,10 @@ static const struct usb_ehci_pdata ehci_ + static const struct usb_ohci_pdata ohci_pdata = { + }; + +-static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) ++static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, ++ const char *name, u32 addr, ++ const void *data, ++ size_t size) + { + struct platform_device *hci_dev; + struct resource hci_res[2]; +@@ -259,8 +262,7 @@ static struct platform_device *bcma_hcd_ + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + +- hci_dev = platform_device_alloc(ohci ? "ohci-platform" : +- "ehci-platform" , 0); ++ hci_dev = platform_device_alloc(name, 0); + if (!hci_dev) + return ERR_PTR(-ENOMEM); + +@@ -271,12 +273,8 @@ static struct platform_device *bcma_hcd_ + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; +- if (ohci) +- ret = platform_device_add_data(hci_dev, &ohci_pdata, +- sizeof(ohci_pdata)); +- else +- ret = platform_device_add_data(hci_dev, &ehci_pdata, +- sizeof(ehci_pdata)); ++ if (data) ++ ret = platform_device_add_data(hci_dev, data, size); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); +@@ -333,11 +331,15 @@ static int bcma_hcd_probe(struct bcma_de + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + +- usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); ++ usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform", ++ ohci_addr, &ohci_pdata, ++ sizeof(ohci_pdata)); + if (IS_ERR(usb_dev->ohci_dev)) + return PTR_ERR(usb_dev->ohci_dev); + +- usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); ++ usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform", ++ dev->addr, &ehci_pdata, ++ sizeof(ehci_pdata)); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; diff --git a/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch b/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch new file mode 100644 index 0000000..262192b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch @@ -0,0 +1,112 @@ +From fa5622c2fadae573dd6b0f5bffe436b230b411f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Tue, 16 Jun 2015 12:52:07 +0200 +Subject: [PATCH v3 4/6] usb: bcma: use separated function for USB 2.0 + initialization +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This will allow adding USB 3.0 (XHCI) support cleanly. + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/usb/host/bcma-hcd.c | 51 +++++++++++++++++++++++++++++++-------------- + 1 file changed, 35 insertions(+), 16 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -35,6 +35,7 @@ MODULE_DESCRIPTION("Common USB driver fo + MODULE_LICENSE("GPL"); + + struct bcma_hcd_device { ++ struct bcma_device *core; + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + struct gpio_desc *gpio_desc; +@@ -288,31 +289,16 @@ err_alloc: + return ERR_PTR(ret); + } + +-static int bcma_hcd_probe(struct bcma_device *dev) ++static int bcma_hcd_usb20_init(struct bcma_hcd_device *usb_dev) + { +- int err; ++ struct bcma_device *dev = usb_dev->core; ++ struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo; + u32 ohci_addr; +- struct bcma_hcd_device *usb_dev; +- struct bcma_chipinfo *chipinfo; +- +- chipinfo = &dev->bus->chipinfo; +- +- /* TODO: Probably need checks here; is the core connected? */ ++ int err; + + if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + +- usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), +- GFP_KERNEL); +- if (!usb_dev) +- return -ENOMEM; +- +- if (dev->dev.of_node) +- usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", +- &dev->dev.of_node->fwnode); +- if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) +- gpiod_direction_output(usb_dev->gpio_desc, 1); +- + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: + bcma_hcd_init_chip_arm(dev); +@@ -345,7 +331,6 @@ static int bcma_hcd_probe(struct bcma_de + goto err_unregister_ohci_dev; + } + +- bcma_set_drvdata(dev, usb_dev); + return 0; + + err_unregister_ohci_dev: +@@ -353,6 +338,40 @@ err_unregister_ohci_dev: + return err; + } + ++static int bcma_hcd_probe(struct bcma_device *dev) ++{ ++ int err; ++ struct bcma_hcd_device *usb_dev; ++ ++ /* TODO: Probably need checks here; is the core connected? */ ++ ++ usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), ++ GFP_KERNEL); ++ if (!usb_dev) ++ return -ENOMEM; ++ usb_dev->core = dev; ++ ++ if (dev->dev.of_node) ++ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", ++ &dev->dev.of_node->fwnode); ++ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) ++ gpiod_direction_output(usb_dev->gpio_desc, 1); ++ ++ switch (dev->id.id) { ++ case BCMA_CORE_USB20_HOST: ++ case BCMA_CORE_NS_USB20: ++ err = bcma_hcd_usb20_init(usb_dev); ++ if (err) ++ return err; ++ break; ++ default: ++ return -ENODEV; ++ } ++ ++ bcma_set_drvdata(dev, usb_dev); ++ return 0; ++} ++ + static void bcma_hcd_remove(struct bcma_device *dev) + { + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); diff --git a/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch b/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch new file mode 100644 index 0000000..34ab858 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch @@ -0,0 +1,295 @@ +From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Tue, 16 Jun 2015 17:14:26 +0200 +Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 225 insertions(+) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -29,6 +29,7 @@ + #include <linux/of_gpio.h> + #include <linux/usb/ehci_pdriver.h> + #include <linux/usb/ohci_pdriver.h> ++#include <linux/usb/xhci_pdriver.h> + + MODULE_AUTHOR("Hauke Mehrtens"); + MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +@@ -38,6 +39,7 @@ struct bcma_hcd_device { + struct bcma_device *core; + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; ++ struct platform_device *xhci_dev; + struct gpio_desc *gpio_desc; + }; + +@@ -245,6 +247,10 @@ static const struct usb_ehci_pdata ehci_ + static const struct usb_ohci_pdata ohci_pdata = { + }; + ++static const struct usb_xhci_pdata xhci_pdata = { ++ .usb3_fake_doorbell = 1 ++}; ++ + static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, + const char *name, u32 addr, + const void *data, +@@ -338,6 +344,216 @@ err_unregister_ohci_dev: + return err; + } + ++static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, ++ u32 value, int timeout) ++{ ++ unsigned long deadline = jiffies + timeout; ++ u32 val; ++ ++ do { ++ val = readl(addr); ++ if ((val & mask) == value) ++ return true; ++ cpu_relax(); ++ udelay(10); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ pr_err("Timeout waiting for register %p\n", addr); ++ ++ return false; ++} ++ ++static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd) ++{ ++ struct bcma_device *core = bcma_hcd->core; ++ struct bcma_bus *bus = core->bus; ++ struct bcma_chipinfo *chipinfo = &bus->chipinfo; ++ struct bcma_drv_cc_b *ccb = &bus->drv_cc_b; ++ struct bcma_device *arm_core; ++ void __iomem *dmu = NULL; ++ u32 cru_straps_ctrl; ++ ++ if (chipinfo->id != BCMA_CHIP_ID_BCM4707 && ++ chipinfo->id != BCMA_CHIP_ID_BCM53018) ++ return; ++ ++ arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9); ++ if (!arm_core) ++ return; ++ ++ dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000); ++ if (!dmu) ++ goto out; ++ ++ /* Check strapping of PCIE/USB3 SEL */ ++ cru_straps_ctrl = ioread32(dmu + 0x2a0); ++ if ((cru_straps_ctrl & 0x10) == 0) ++ goto out; ++ ++ /* Perform USB3 system soft reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); ++ ++ /* Enable MDIO. Setting MDCDIV as 26 */ ++ iowrite32(0x0000009a, ccb->mii + 0x000); ++ udelay(2); ++ ++ switch (chipinfo->id) { ++ case BCMA_CHIP_ID_BCM4707: ++ if (chipinfo->rev == 4) { ++ /* For NS-B0, USB3 PLL Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ /* Clear ana_pllSeqStart */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061000, ccb->mii + 0x004); ++ ++ /* CMOS Divider ratio to 25 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ /* Asserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582ec000, ccb->mii + 0x004); ++ ++ /* Deaaserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582e8000, ccb->mii + 0x004); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ ++ /* Set ana_pllSeqStart */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58069000, ccb->mii + 0x004); ++ ++ /* RXPMD block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8020, ccb->mii + 0x004); ++ ++ /* CDR int loop locking BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58120049, ccb->mii + 0x004); ++ ++ /* CDR int loop acquisition BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580e0049, ccb->mii + 0x004); ++ ++ /* CDR prop loop BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a005c, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ } else { ++ /* PLL30 block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e80e0, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a009c, ccb->mii + 0x004); ++ ++ /* Enable SSC */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8040, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a21d3, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061003, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ } ++ break; ++ case BCMA_CHIP_ID_BCM53018: ++ /* USB3 PLL Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ /* Assert Ana_Pllseq start */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061000, ccb->mii + 0x004); ++ ++ /* Assert CML Divider ratio to 26 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ /* Asserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582ec000, ccb->mii + 0x004); ++ ++ /* Deaaserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582e8000, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ ++ /* PLL frequency monitor enable */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58069000, ccb->mii + 0x004); ++ ++ /* PIPE Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8060, ccb->mii + 0x004); ++ ++ /* CMPMAX & CMPMINTH setting */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580af30d, ccb->mii + 0x004); ++ ++ /* DEGLITCH MIN & MAX setting */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580e6302, ccb->mii + 0x004); ++ ++ /* TXPMD block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8040, ccb->mii + 0x004); ++ ++ /* Enabling SSC */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061003, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ break; ++ } ++out: ++ if (dmu) ++ iounmap(dmu); ++} ++ ++static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd) ++{ ++ struct bcma_device *core = bcma_hcd->core; ++ ++ bcma_core_enable(core, 0); ++ ++ bcma_hcd_usb30_phy_init(bcma_hcd); ++ ++ bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr, ++ &xhci_pdata, ++ sizeof(xhci_pdata)); ++ if (IS_ERR(bcma_hcd->ohci_dev)) ++ return PTR_ERR(bcma_hcd->ohci_dev); ++ ++ return 0; ++} ++ + static int bcma_hcd_probe(struct bcma_device *dev) + { + int err; +@@ -364,6 +580,11 @@ static int bcma_hcd_probe(struct bcma_de + if (err) + return err; + break; ++ case BCMA_CORE_NS_USB30: ++ err = bcma_hcd_usb30_init(usb_dev); ++ if (err) ++ return err; ++ break; + default: + return -ENODEV; + } +@@ -377,11 +598,14 @@ static void bcma_hcd_remove(struct bcma_ + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; ++ struct platform_device *xhci_dev = usb_dev->xhci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); ++ if (xhci_dev) ++ platform_device_unregister(xhci_dev); + + bcma_core_disable(dev, 0); + } +@@ -418,6 +642,7 @@ static int bcma_hcd_resume(struct bcma_d + static const struct bcma_device_id bcma_hcd_table[] = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS), + {}, + }; + MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); diff --git a/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch b/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch new file mode 100644 index 0000000..06254b3 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch @@ -0,0 +1,86 @@ +From: Florian Fainelli <f.fainelli@gmail.com>
+Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression
+Date: Tue, 14 Jul 2015 16:12:08 -0700
+
+Use the existing __armv7_mmu_cache_flush() to perform the cache flush
+since this does what we are after.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/compressed/Makefile | 4 +++
+ arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++
+ arch/arm/boot/compressed/head.S | 2 ++
+ 3 files changed, 43 insertions(+)
+ create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
+
+--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y) + OBJS += ll_char_wr.o font.o + endif + ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++OBJS += head-bcm_5301x-mpcore.o ++endif ++ + ifeq ($(CONFIG_ARCH_SA1100),y) + OBJS += head-sa1100.o + endif +--- /dev/null ++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S +@@ -0,0 +1,37 @@ ++/* ++ * ++ * Platform specific tweaks. This is merged into head.S by the linker. ++ * ++ */ ++ ++#include <linux/linkage.h> ++#include <asm/assembler.h> ++#include <asm/cp15.h> ++ ++ .section ".start", "ax" ++ ++/* ++ * This code section is spliced into the head code by the linker ++ */ ++ ++__plat_uncompress_start: ++ ++ @ Preserve r8/r7 i.e. kernel entry values ++ mov r12, r8 ++ ++ @ Clear MMU enable and Dcache enable bits ++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR ++ bic r0, #CR_C|CR_M ++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR ++ nop ++ ++ @ Call the cache invalidation routine ++ bl __armv7_mmu_cache_flush_fn ++ nop ++ mov r0,#0 ++ ldr r3, =0x19022000 @ L2 cache controller, control reg ++ str r0, [r3, #0x100] @ Disable L2 cache ++ nop ++ ++ @ Restore ++ mov r8, r12 +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush: + hierarchical: + mcr p15, 0, r10, c7, c10, 5 @ DMB + stmfd sp!, {r0-r7, r9-r11} ++ENTRY(__armv7_mmu_cache_flush_fn) + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field +@@ -1201,6 +1202,7 @@ iflush: + mcr p15, 0, r10, c7, c10, 4 @ DSB + mcr p15, 0, r10, c7, c5, 4 @ ISB + mov pc, lr ++ENDPROC(__armv7_mmu_cache_flush_fn) + + __armv5tej_mmu_cache_flush: + tst r4, #1 diff --git a/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch b/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch new file mode 100644 index 0000000..ed6cc73 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch @@ -0,0 +1,26 @@ +From d404e0b22356078a51719fa911f6e09cb1a72d80 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Sun, 7 Jun 2015 16:18:18 +0200 +Subject: [PATCH] ARM: BCM5301X: Add SPROM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -136,6 +136,10 @@ + }; + }; + ++ sprom0: sprom@0 { ++ compatible = "brcm,bcm47xx-sprom"; ++ }; ++ + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; diff --git a/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch b/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch new file mode 100644 index 0000000..82ac24e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch @@ -0,0 +1,69 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Subject: [PATCH] ARM: BCM5301X: Add DT for Linksys EA6300 V1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ ++ bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +@@ -0,0 +1,48 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Linksys EA6300 V1 ++ * ++ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "linksys,ea6300v1", "brcm,bcm4708"; ++ model = "Linksys EA6300 V1"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = <KEY_WPS_BUTTON>; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch b/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch new file mode 100644 index 0000000..802188d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch @@ -0,0 +1,41 @@ +From 504dba5b073a9009ae1e3f2fc53ea9c3aa10c38a Mon Sep 17 00:00:00 2001 +From: Felix Fietkau <nbd@openwrt.org> +Date: Wed, 13 May 2015 20:56:38 +0200 +Subject: [PATCH] ARM: BCM5301X: Add Buffalo WXR-1900DHP clock and USB power + control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Felix Fietkau <nbd@openwrt.org> +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -24,6 +24,23 @@ + reg = <0x00000000 0x08000000>; + }; + ++ clocks { ++ clk_periph: periph { ++ clock-frequency = <500000000>; ++ }; ++ }; ++ ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + diff --git a/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch b/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch new file mode 100644 index 0000000..ed4d1bc --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch @@ -0,0 +1,86 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Subject: [PATCH] ARM: BCM5301X: Set vcc-gpio for USB controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -24,6 +24,26 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -24,6 +24,17 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -24,6 +24,26 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + diff --git a/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch b/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch new file mode 100644 index 0000000..4e25647 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch @@ -0,0 +1,170 @@ +From eb1075cc48d3c315c7403822c33da9588ab76492 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Wed, 14 Jan 2015 08:33:25 +0100 +Subject: [PATCH] ARM: BCM5310X: Enable earlyprintk on tested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 2 +- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 2 +- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 2 +- + 4 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-1750DHP (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -17,7 +17,7 @@ + model = "Netgear R6250 V1 (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-N18U (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-600DHP2 (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-900DHP (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -17,7 +17,7 @@ + model = "Netgear R8000 (BCM4709)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC56U (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC68U (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -17,7 +17,7 @@ + model = "Luxul XWC-1000 (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WXR-1900DHP"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -17,7 +17,7 @@ + model = "SmartRG SR400ac"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC87U"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -17,7 +17,7 @@ + model = "Netgear R7000"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts ++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +@@ -17,7 +17,7 @@ + model = "Linksys EA6300 V1"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { diff --git a/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch b/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch new file mode 100644 index 0000000..b53c57f --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch @@ -0,0 +1,173 @@ +From 36b2fbb3badf0e32b371e1f7579a95d4fe25c0e1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Wed, 14 Jan 2015 09:13:58 +0100 +Subject: [PATCH] ARM: BCM5301X: Specify RAM on devices by including HIGHMEM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 3 ++- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 3 ++- + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 3 ++- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 3 ++- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 3 ++- + 5 files changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x18000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + spi { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + gpio-keys { +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x18000000>; + }; + + clocks { +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { diff --git a/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch b/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch new file mode 100644 index 0000000..f9ca7eb --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch @@ -0,0 +1,20 @@ +From: Felix Fietkau <nbd@openwrt.org> +Subject: [PATCH] ARM: BCM5301X: Add power button for Buffalo WZR-1750DHP + +Signed-off-by: Felix Fietkau <nbd@openwrt.org> +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -123,6 +123,12 @@ + #address-cells = <1>; + #size-cells = <0>; + ++ power { ++ label = "Power"; ++ linux,code = <KEY_POWER>; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; ++ }; ++ + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; diff --git a/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch b/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch new file mode 100644 index 0000000..dad4f8a --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch @@ -0,0 +1,111 @@ +From b49d7bb4825654f81bcee8e219028712811515a5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Mon, 29 Jun 2015 08:11:36 +0200 +Subject: [PATCH] ARM: BCM5301X: Enable ChipCommon UART on untested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 4 ++++ + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 4 ++++ + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 4 ++++ + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 4 ++++ + arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++++ + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 5 +++++ + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 5 +++++ + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 5 +++++ + 8 files changed, 35 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -96,3 +96,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -83,3 +83,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -83,3 +83,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -77,3 +77,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -37,3 +37,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -65,3 +65,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -144,3 +144,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -127,3 +127,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -104,4 +104,5 @@ + + &uart0 { + status = "okay"; ++ clock-frequency = <125000000>; + }; diff --git a/target/linux/bcm53xx/patches-4.3/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch b/target/linux/bcm53xx/patches-4.3/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch new file mode 100644 index 0000000..ccdb28b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch @@ -0,0 +1,31 @@ +From d658c21d6697293a928434fd6ac19264b5a8948d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Fri, 30 Jan 2015 08:25:54 +0100 +Subject: [PATCH] mtd: bcm47xxpart: scan whole flash on ARCH_BCM_5301X +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + drivers/mtd/bcm47xxpart.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -120,9 +120,15 @@ static int bcm47xxpart_parse(struct mtd_ + /* Parse block by block looking for magics */ + for (offset = 0; offset <= master->size - blocksize; + offset += blocksize) { ++#ifndef CONFIG_ARCH_BCM_5301X ++ /* ++ * ARM routers may have partitions in higher memory. E.g. ++ * Netgear R8000 has board_data at 0x2600000. ++ */ + /* Nothing more in higher memory */ + if (offset >= 0x2000000) + break; ++#endif + + if (curr_part >= BCM47XXPART_MAX_PARTS) { + pr_warn("Reached maximum number of partitions, scanning stopped!\n"); diff --git a/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch b/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch new file mode 100644 index 0000000..79af785 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch @@ -0,0 +1,20 @@ +--- a/drivers/mtd/spi-nor/Kconfig ++++ b/drivers/mtd/spi-nor/Kconfig +@@ -40,4 +40,10 @@ config SPI_NXP_SPIFI + Flash. Enable this option if you have a device with a SPIFI + controller and want to access the Flash as a mtd device. + ++config MTD_SPI_BCM53XXSPIFLASH ++ tristate "SPI-NOR flashes connected to the Broadcom ARM SoC" ++ depends on MTD_SPI_NOR ++ help ++ SPI driver for flashes used on Broadcom ARM SoCs. ++ + endif # MTD_SPI_NOR +--- a/drivers/mtd/spi-nor/Makefile ++++ b/drivers/mtd/spi-nor/Makefile +@@ -1,3 +1,4 @@ + obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o + obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o ++obj-$(CONFIG_MTD_SPI_BCM53XXSPIFLASH) += bcm53xxspiflash.o + obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o diff --git a/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch new file mode 100644 index 0000000..a3d0f75 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch @@ -0,0 +1,59 @@ +From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Thu, 16 Oct 2014 20:52:16 +0200 +Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + drivers/mtd/ubi/attach.c | 5 +++++ + drivers/mtd/ubi/io.c | 4 ++++ + drivers/mtd/ubi/ubi.h | 1 + + 3 files changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -95,6 +95,9 @@ static int self_check_ai(struct ubi_devi + static struct ubi_ec_hdr *ech; + static struct ubi_vid_hdr *vidh; + ++/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */ ++bool erase_all_next; ++ + /** + * add_to_list - add physical eraseblock to a list. + * @ai: attaching information +@@ -1427,6 +1430,8 @@ int ubi_attach(struct ubi_device *ubi, i + if (!ai) + return -ENOMEM; + ++ erase_all_next = false; ++ + #ifdef CONFIG_MTD_UBI_FASTMAP + /* On small flash devices we disable fastmap in any case. */ + if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { +--- a/drivers/mtd/ubi/io.c ++++ b/drivers/mtd/ubi/io.c +@@ -755,6 +755,10 @@ int ubi_io_read_ec_hdr(struct ubi_device + } + + magic = be32_to_cpu(ec_hdr->magic); ++ if (magic == 0xdeadc0de) ++ erase_all_next = true; ++ if (erase_all_next) ++ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF; + if (magic != UBI_EC_HDR_MAGIC) { + if (mtd_is_eccerr(read_err)) + return UBI_IO_BAD_HDR_EBADMSG; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -781,6 +781,7 @@ extern struct mutex ubi_devices_mutex; + extern struct blocking_notifier_head ubi_notifiers; + + /* attach.c */ ++extern bool erase_all_next; + int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum, + int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips); + struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai, diff --git a/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch b/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch new file mode 100644 index 0000000..dfc422e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch @@ -0,0 +1,42 @@ +From 4abdde3ad6bc0b3b157c4bf6ec0bf139d11d07e8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Wed, 13 May 2015 14:13:28 +0200 +Subject: [PATCH] b53: add hacky CPU port fixes for devices not using port 5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + drivers/net/phy/b53/b53_common.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/phy/b53/b53_common.c ++++ b/drivers/net/phy/b53/b53_common.c +@@ -25,6 +25,7 @@ + #include <linux/module.h> + #include <linux/switch.h> + #include <linux/platform_data/b53.h> ++#include <linux/of.h> + + #include "b53_regs.h" + #include "b53_priv.h" +@@ -1313,6 +1314,18 @@ static int b53_switch_init(struct b53_de + sw_dev->cpu_port = 5; + } + ++ if (of_machine_is_compatible("asus,rt-ac87u")) ++ sw_dev->cpu_port = 7; ++ else if (of_machine_is_compatible("netgear,r8000")) ++ sw_dev->cpu_port = 8; ++ ++ /* ++ * Workaround for devices using port 8 (connected to the 3rd iface). ++ * For some reason it doesn't work (no packets on eth2). ++ */ ++ if (of_machine_is_compatible("netgear,r8000")) ++ sw_dev->cpu_port = 5; ++ + /* cpu port is always last */ + sw_dev->ports = sw_dev->cpu_port + 1; + dev->enabled_ports |= BIT(sw_dev->cpu_port); diff --git a/target/linux/bcm53xx/patches-4.3/800-bcma-use-two-different-initcalls-if-built-in.patch b/target/linux/bcm53xx/patches-4.3/800-bcma-use-two-different-initcalls-if-built-in.patch new file mode 100644 index 0000000..4e5793b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/800-bcma-use-two-different-initcalls-if-built-in.patch @@ -0,0 +1,65 @@ +From 666bdfc027cde41a171862dc698987a378c8b66a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Mon, 9 Feb 2015 18:00:42 +0100 +Subject: [PATCH RFC] bcma: use two different initcalls if built-in +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is needed as we can't initialize bus during fs_initcall. +Initialization requires SPROM which depends on NVRAM which depends on +mtd. Since mtd, spi, nand, spi-nor use standard module_init, we have to +do the same in bcma. +Without this we'll try to initialize SPROM without having a ready SPROM +proviver registered using bcma_arch_register_fallback_sprom. + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- +While this patch seems to work and I can compile bcma as built-in and +module, I'm not too proud of it. I don't really like these #if(n)def +tricks and I'm afraid bcma_modinit may be called even if +bcma_modinit_early failed. + +Do you see any better idea of solving this? +--- + drivers/bcma/main.c | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -673,13 +673,25 @@ static int bcma_device_uevent(struct dev + core->id.rev, core->id.class); + } + ++/* Bus has to be registered early, before any bcma driver */ ++static int __init bcma_modinit_early(void) ++{ ++ return bus_register(&bcma_bus_type); ++} ++#ifndef MODULE ++fs_initcall(bcma_modinit_early); ++#endif ++ ++/* Initialization has to be done later with SPI/mtd/NAND/SPROM available */ + static int __init bcma_modinit(void) + { + int err; + +- err = bus_register(&bcma_bus_type); ++#ifdef MODULE ++ err = bcma_modinit_early(); + if (err) + return err; ++#endif + + err = bcma_host_soc_register_driver(); + if (err) { +@@ -696,7 +708,7 @@ static int __init bcma_modinit(void) + + return err; + } +-fs_initcall(bcma_modinit); ++module_init(bcma_modinit); + + static void __exit bcma_modexit(void) + { diff --git a/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch b/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch new file mode 100644 index 0000000..c1dfa92 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch @@ -0,0 +1,42 @@ +From 21500872c1dba33848ddcf6bea97d58772675d36 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> +Date: Sun, 17 May 2015 14:00:52 +0200 +Subject: [PATCH] mtd: bcm47xxpart: workaround for Asus RT-AC87U "asus" + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki <zajec5@gmail.com> +--- + drivers/mtd/bcm47xxpart.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -14,6 +14,7 @@ + #include <linux/slab.h> + #include <linux/mtd/mtd.h> + #include <linux/mtd/partitions.h> ++#include <linux/of.h> + + #include <uapi/linux/magic.h> + +@@ -135,6 +136,17 @@ static int bcm47xxpart_parse(struct mtd_ + break; + } + ++ /* ++ * Ugly workaround for Asus RT-AC87U and its "asus" partition. ++ * It uses JFFS2 which we don't (want to) detect. We should ++ * probably use DT to define partitions but we need a working ++ * TRX firmware splitter first. ++ */ ++ if (of_machine_is_compatible("asus,rt-ac87u") && offset == 0x7ec0000) { ++ bcm47xxpart_add_part(&parts[curr_part++], "asus", offset, MTD_WRITEABLE); ++ continue; ++ } ++ + /* Read beginning of the block */ + if (mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ, + &bytes_read, (uint8_t *)buf) < 0) { |