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Diffstat (limited to 'cfe/cfe/arch/mips/board/bcm63xx_ram/include/bcmmii.h')
| -rwxr-xr-x | cfe/cfe/arch/mips/board/bcm63xx_ram/include/bcmmii.h | 164 |
1 files changed, 164 insertions, 0 deletions
diff --git a/cfe/cfe/arch/mips/board/bcm63xx_ram/include/bcmmii.h b/cfe/cfe/arch/mips/board/bcm63xx_ram/include/bcmmii.h new file mode 100755 index 0000000..a33de5c --- /dev/null +++ b/cfe/cfe/arch/mips/board/bcm63xx_ram/include/bcmmii.h @@ -0,0 +1,164 @@ +/* +<:copyright-broadcom + + Copyright (c) 2004 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +#ifndef _BCMMII_H_ +#define _BCMMII_H_ + +#include "dev_bcm63xx_eth.h" + +/*---------------------------------------------------------------------*/ +/* Broadcom PHY MII register address */ +/* use when PhyType is BP_ENET_INTERNAL_PHY */ +/*---------------------------------------------------------------------*/ +#define BCM_PHY_ID_M 0x1F +#define IsExtPhyId(id) ((id & BCM_PHY_ID_M) >= 0x10) +//#define BCM_WAN_PORT 0x40 +//#define IsWanPort(id) (((id) & BCM_WAN_PORT) && ((id) != 0xFF)) + +#define MII_ASR 0x19 +#define MII_INTERRUPT 0x1A +#define MII_RESERVED_1B 0x1B +#define MII_BRCM_TEST 0x1F + +/* MII ASR register. */ +#define MII_ASR_DONE(r) ((r & 0x8000) != 0) +#define MII_ASR_LINK(r) ((r & 0x0004) != 0) +#define MII_ASR_FDX(r) (((r & 0x0700) == 0x0700) || ((r & 0x0700) == 0x0500) || ((r & 0x0700) == 0x0200)) +#define MII_ASR_1000(r) (((r & 0x0700) == 0x0700) || ((r & 0x0700) == 0x0600)) +#define MII_ASR_100(r) (((r & 0x0700) == 0x0500) || ((r & 0x0700) == 0x0300)) +#define MII_ASR_10(r) (((r & 0x0700) == 0x0200) || ((r & 0x0700) == 0x0100)) + +/* Reserved 0x1B register */ +#define MII_RESERVED_1B_ACT_LED 0x0004 + +/* Broadcom Test register. */ +#define MII_BRCM_TEST_SHADOW2_ENABLE 0x0004 + +/* MII Interrupt register. */ +#define MII_INTR_ENABLE 0x4000 + +#define BCM54610_PHYID2 0xBD63 +#define BCM_PHYID_M 0xFFF0 + +#define MII_REGISTER_1C 0x1c + #define MII_1C_WRITE_ENABLE (1 << 15) + #define MII_1C_SHADOW_REG_SEL_S 10 + #define MII_1C_SHADOW_REG_SEL_M 0x1F +#define MII_1C_SHADOW_CLK_ALIGN_CTRL 0x3 + #define GTXCLK_DELAY_BYPASS_DISABLE (1 << 9) +#define MII_1C_SHADOW_LED_CONTROL 0x9 + #define ACT_LINK_LED_ENABLE (1 << 4) +#define MII_1C_EXTERNAL_CONTROL_1 0xB + #define LOM_LED_MODE (1 << 2) + +#define PAGE_CONTROL 0x00 +#define PAGE_SELECT 0xff +#define PAGE_MANAGEMENT 0x02 + +/* Control page registers */ +#define REG_MII_PORT_CONTROL 0x08 +#define REG_SWITCH_MODE 0x0b +#define REG_CONTROL_MII1_PORT_STATE_OVERRIDE 0x0e +#define REG_POWER_DOWN_MODE 0x0f + +/* MII Port Control Register, Page 0x00 Address 0x08 */ +#define REG_MII_PORT_CONTROL_RX_UCST_EN 0x10 +#define REG_MII_PORT_CONTROL_RX_MCST_EN 0x08 +#define REG_MII_PORT_CONTROL_RX_BCST_EN 0x04 + +/* Switch mode register, Page 0x00 Address 0x0b */ +#define REG_SWITCH_MODE_FRAME_MANAGE_MODE 0x01 +#define REG_SWITCH_MODE_SW_FWDG_EN 0x02 + +/* MII1 Port State Override Register Page 0x00 Address 0x0e */ +#define REG_CONTROL_MPSO_MII_SW_OVERRIDE 0x80 +#define REG_CONTROL_MPSO_REVERSE_MII 0x10 +#define REG_CONTROL_MPSO_LP_FLOW_CONTROL 0x08 +#define REG_CONTROL_MPSO_SPEED100 0x04 +#define REG_CONTROL_MPSO_SPEED1000 0x08 +#define REG_CONTROL_MPSO_FDX 0x02 +#define REG_CONTROL_MPSO_LINKPASS 0x01 + +/* Power down mode register Page 0x00 Address 0x0f */ +#define REG_POWER_DOWN_MODE_PORT1_PHY_DISABLE 0x01 +#define REG_POWER_DOWN_MODE_PORT2_PHY_DISABLE 0x02 +#define REG_POWER_DOWN_MODE_PORT3_PHY_DISABLE 0x04 +#define REG_POWER_DOWN_MODE_PORT4_PHY_DISABLE 0x08 +#define REG_POWER_DOWN_MODE_PORT5_PHY_DISABLE 0x10 + +/* Switch control register page 0x0 */ +#define REG_SWITCH_CONTROL 0x20 +#define REG_SWITCH_CONTROL_MII_DUMP_FWD_EN 0x1 + +/* Device ID register page 0x02 */ +#define REG_DEVICE_ID 0x30 +#define REG_GLOBAL_CONFIG 0x00 +#define REG_BRCM_HDR_CTRL 0x03 + +/* Global Configuration Regiater Page 0x02 Address 0x00 */ +#define ENABLE_MII_PORT 0x80 + +/* Broadcom Header Control Register Page 0x02 Address 0x03*/ +#define REG_BRCM_HDR_ENABLE 0x01 + + + +/*---------------------------------------------------------------------*/ +/* 5325 Switch SPI Interface */ +/* use when configuration type is BP_ENET_CONFIG_SPI_SSB_x */ +/*---------------------------------------------------------------------*/ +#define BCM5325_SPI_CMD_LEN 1 +#define BCM5325_SPI_ADDR_LEN 1 +#define BCM5325_SPI_PREPENDCNT (BCM5325_SPI_CMD_LEN+BCM5325_SPI_ADDR_LEN) + +/* 5325 SPI Status Register */ +#define BCM5325_SPI_STS 0xfe + +/* 5325 SPI Status Register definition */ +#define BCM5325_SPI_CMD_RACK 0x20 + +/* 5325 Command Byte definition */ +#define BCM5325_SPI_CMD_READ 0x00 /* bit 0 - Read/Write */ +#define BCM5325_SPI_CMD_WRITE 0x01 /* bit 0 - Read/Write */ +#define BCM5325_SPI_CHIPID_MASK 0x7 /* bit 3:1 - Chip ID */ +#define BCM5325_SPI_CHIPID_SHIFT 1 +#define BCM5325_SPI_CMD_NORMAL 0x60 /* bit 7:4 - Mode */ +#define BCM5325_SPI_CMD_FAST 0x10 /* bit 4 - Mode */ + +/*---------------------------------------------------------------------*/ +/* 5325 Switch Pseudo PHY MII Register */ +/* use when configuration type is BP_ENET_CONFIG_MDIO_PSEUDO_PHY */ +/*---------------------------------------------------------------------*/ +#define PSEUDO_PHY_ADDR 0x1e /* Pseduo PHY address */ + +/* Pseudo PHY MII registers */ +#define REG_PSEUDO_PHY_MII_REG16 0x10 /* register 16 - Switch Register Set Access Control Register */ +#define REG_PSEUDO_PHY_MII_REG17 0x11 /* register 17 - Switch Register Set Read/Write Control Register */ +#define REG_PSEUDO_PHY_MII_REG24 0x18 /* register 24 - Switch Accesss Register bit 15:0 */ +#define REG_PSEUDO_PHY_MII_REG25 0x19 /* register 25 - Switch Accesss Register bit 31:16 */ +#define REG_PSEUDO_PHY_MII_REG26 0x20 /* register 26 - Switch Accesss Register bit 47:32 */ +#define REG_PSEUDO_PHY_MII_REG27 0x21 /* register 27 - Switch Accesss Register bit 63:48 */ + +/*Pseudo PHY MII register 16 Switch Register Set Access Control Register */ +#define REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT 8 /* bit 8..15 - switch page number */ +#define REG_PPM_REG16_MDIO_ENABLE 0x01 /* bit 0 - set MDC/MDIO access enable */ + +/*Pseudo PHY MII register 17 Switch Register Set Read/Write Control Register */ +#define REG_PPM_REG17_REG_NUMBER_SHIFT 8 /* bit 8..15 - switch register number */ +#define REG_PPM_REG17_OP_DONE 0x00 /* bit 0..1 - no operation */ +#define REG_PPM_REG17_OP_WRITE 0x01 /* bit 0..1 - write operation */ +#define REG_PPM_REG17_OP_READ 0x02 /* bit 0..1 - read operation */ + +#endif /* _BCMMII_H_ */ |