aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch
diff options
context:
space:
mode:
authorJames <>2015-09-26 12:29:31 +0100
committerJames <>2015-09-26 12:29:31 +0100
commit626d9efa74685720020e816f3a917b7591d3cf7a (patch)
treed22eef73ae82287b30a1140decb4fc806d39d621 /target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch
downloadtrunk-47048-626d9efa74685720020e816f3a917b7591d3cf7a.tar.gz
trunk-47048-626d9efa74685720020e816f3a917b7591d3cf7a.tar.bz2
trunk-47048-626d9efa74685720020e816f3a917b7591d3cf7a.zip
trunk-47048
Diffstat (limited to 'target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch')
-rw-r--r--target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch66
1 files changed, 66 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch b/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch
new file mode 100644
index 0000000..1d50710
--- /dev/null
+++ b/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch
@@ -0,0 +1,66 @@
+From efc0f99cebcab21dbabcc634b9dbb963bbbbcab8 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:23:36 +0100
+Subject: [PATCH 07/57] MIPS: ralink: add support for MT7620n
+
+This is the small version of MT7620a.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
+ arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
+ 2 files changed, 14 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -25,11 +25,8 @@
+ #define SYSC_REG_CPLL_CONFIG0 0x54
+ #define SYSC_REG_CPLL_CONFIG1 0x58
+
+-#define MT7620N_CHIP_NAME0 0x33365452
+-#define MT7620N_CHIP_NAME1 0x20203235
+-
+-#define MT7620A_CHIP_NAME0 0x3637544d
+-#define MT7620A_CHIP_NAME1 0x20203032
++#define MT7620_CHIP_NAME0 0x3637544d
++#define MT7620_CHIP_NAME1 0x20203032
+
+ #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -357,22 +357,27 @@ void prom_soc_init(struct ralink_soc_inf
+ u32 cfg0;
+ u32 pmu0;
+ u32 pmu1;
++ u32 bga;
+
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
++ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
+
+- if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
+- name = "MT7620N";
+- soc_info->compatible = "ralink,mt7620n-soc";
+- } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
++ if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
++ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++
++ if (bga) {
+ name = "MT7620A";
+ soc_info->compatible = "ralink,mt7620a-soc";
+ } else {
+- panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1);
++ name = "MT7620N";
++ soc_info->compatible = "ralink,mt7620n-soc";
++#ifdef CONFIG_PCI
++ panic("mt7620n is only supported for non pci kernels");
++#endif
+ }
+
+- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
+-
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+ "Ralink %s ver:%u eco:%u",
+ name,