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-rw-r--r--target/linux/imx6/patches-3.10/200-imx6_pcie.patch91
1 files changed, 91 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.10/200-imx6_pcie.patch b/target/linux/imx6/patches-3.10/200-imx6_pcie.patch
new file mode 100644
index 0000000000..1f84d5eb72
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/200-imx6_pcie.patch
@@ -0,0 +1,91 @@
+--- a/arch/arm/boot/dts/imx6q.dtsi
++++ b/arch/arm/boot/dts/imx6q.dtsi
+@@ -328,6 +328,15 @@
+ };
+ };
+
++ pcie: pcie@01ffc000 {
++ #crtc-cells = <1>;
++ compatible = "fsl,imx6q-pcie", "fsl,pcie";
++ reg = <0x01ffc000 0x4000>;
++ clocks = <&clks 144>, <&clks 189>;
++ clock-names = "pcie_axi", "pcie_ref_125m";
++ status = "disabled";
++ };
++
+ ipu2: ipu@02800000 {
+ #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+--- a/arch/arm/mach-imx/Kconfig
++++ b/arch/arm/mach-imx/Kconfig
+@@ -790,6 +790,8 @@ config SOC_IMX6Q
+ bool "i.MX6 Quad/DualLite support"
+ select ARCH_HAS_CPUFREQ
+ select ARCH_HAS_OPP
++ select ARCH_HAS_IMX_PCIE
++ select ARCH_SUPPORTS_MSI
+ select ARM_CPU_SUSPEND if PM
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369 if SMP
+@@ -816,6 +818,10 @@ config SOC_IMX6Q
+ help
+ This enables support for Freescale i.MX6 Quad processor.
+
++config IMX_PCIE
++ bool "PCI Express support"
++ select PCI
++
+ endif
+
+ source "arch/arm/mach-imx/devices/Kconfig"
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -98,6 +98,8 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
++obj-$(CONFIG_IMX_PCIE) += pcie.o
++obj-$(CONFIG_PCI_MSI) += msi.o
+
+ ifeq ($(CONFIG_PM),y)
+ obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -547,6 +547,12 @@ int __init mx6q_clocks_init(void)
+ clk_register_clkdev(clk[ahb], "ahb", NULL);
+ clk_register_clkdev(clk[cko1], "cko1", NULL);
+ clk_register_clkdev(clk[arm], NULL, "cpu0");
++ clk_register_clkdev(clk[pcie_axi_sel], "pcie_axi_sel", NULL);
++ clk_register_clkdev(clk[axi], "axi", NULL);
++ clk_register_clkdev(clk[pll6_enet], "pll6_enet", NULL);
++ clk_register_clkdev(clk[pcie_ref], "pcie_ref", NULL);
++ clk_register_clkdev(clk[pcie_ref_125m], "pcie_ref_125m", NULL);
++ clk_register_clkdev(clk[pcie_axi], "pcie_axi", NULL);
+
+ if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
+ clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+--- a/arch/arm/mach-imx/mxc.h
++++ b/arch/arm/mach-imx/mxc.h
+@@ -151,6 +151,10 @@ extern unsigned int __mxc_cpu_type;
+ # define cpu_is_mx53() (0)
+ #endif
+
++#ifdef CONFIG_SOC_IMX6Q
++# define mxc_cpu_type __mxc_cpu_type
++#endif
++
+ #ifndef __ASSEMBLY__
+ static inline bool cpu_is_imx6dl(void)
+ {
+--- a/arch/arm/include/asm/io.h
++++ b/arch/arm/include/asm/io.h
+@@ -178,6 +178,9 @@ extern int pci_ioremap_io(unsigned int o
+ */
+ #ifdef CONFIG_NEED_MACH_IO_H
+ #include <mach/io.h>
++#elif defined(CONFIG_SOC_IMX6Q) && defined(CONFIG_IMX_PCIE)
++#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
++#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
+ #elif defined(CONFIG_PCI)
+ #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
+ #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))