diff options
Diffstat (limited to 'target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci')
4 files changed, 0 insertions, 1647 deletions
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt deleted file mode 100644 index 7b6fe369c5..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt +++ /dev/null @@ -1,4 +0,0 @@ -Global HAL Version: FEROCEON_HAL_3_1_7
-Unit HAL Version: 3.1.2
-Description: This component includes an implementation of the unit HAL drivers
-
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c deleted file mode 100644 index 4a087343de..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c +++ /dev/null @@ -1,1047 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ -#include "pci/mvPci.h" - -#include "ctrlEnv/mvCtrlEnvLib.h" - -/* defines */ -#ifdef MV_DEBUG - #define DB(x) x -#else - #define DB(x) -#endif - - - -MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) -{ - if (MV_PCI_MOD_HOST == pciIfmod) - { - - mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); - mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); - - /* Local device master Enable */ - mvPciMasterEnable(pciIf, MV_TRUE); - - /* Local device slave Enable */ - mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), - mvPciLocalDevNumGet(pciIf), MV_TRUE); - } - /* enable CPU-2-PCI ordering */ - MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); -} - -/******************************************************************************* -* mvPciCommandSet - Set PCI comman register value. -* -* DESCRIPTION: -* This function sets a given PCI interface with its command register -* value. -* -* INPUT: -* pciIf - PCI interface number. -* command - 32bit value to be written to comamnd register. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) -{ - MV_U32 locBusNum, locDevNum, regVal; - - locBusNum = mvPciLocalBusNumGet(pciIf); - locDevNum = mvPciLocalDevNumGet(pciIf); - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); - return MV_BAD_PARAM; - } - - /* Set command register */ - MV_REG_WRITE(PCI_CMD_REG(pciIf), command); - - /* Upodate device max outstanding split tarnsaction */ - if ((command & PCR_CPU_TO_PCI_ORDER_EN) && - (command & PCR_PCI_TO_CPU_ORDER_EN)) - { - /* Read PCI-X command register */ - regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); - - /* clear bits 22:20 */ - regVal &= 0xff8fffff; - - /* set reset value */ - regVal |= (0x3 << 20); - - /* Write back the value */ - mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); - } - - return MV_OK; - - -} - - -/******************************************************************************* -* mvPciModeGet - Get PCI interface mode. -* -* DESCRIPTION: -* This function returns the given PCI interface mode. -* -* INPUT: -* pciIf - PCI interface number. -* -* OUTPUT: -* pPciMode - Pointer to PCI mode structure. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -{ - MV_U32 pciMode; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); - return MV_BAD_PARAM; - } - if (NULL == pPciMode) - { - mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); - return MV_BAD_PARAM; - } - - /* Read pci mode register */ - pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); - - switch (pciMode & PMR_PCI_MODE_MASK) - { - case PMR_PCI_MODE_CONV: - pPciMode->pciType = MV_PCI_CONV; - - if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) - { - pPciMode->pciSpeed = 66000000; /* 66MHZ */ - } - else - { - pPciMode->pciSpeed = 33000000; /* 33MHZ */ - } - - break; - - case PMR_PCI_MODE_PCIX_66MHZ: - pPciMode->pciType = MV_PCIX; - pPciMode->pciSpeed = 66000000; /* 66MHZ */ - break; - - case PMR_PCI_MODE_PCIX_100MHZ: - pPciMode->pciType = MV_PCIX; - pPciMode->pciSpeed = 100000000; /* 100MHZ */ - break; - - case PMR_PCI_MODE_PCIX_133MHZ: - pPciMode->pciType = MV_PCIX; - pPciMode->pciSpeed = 133000000; /* 133MHZ */ - break; - - default: - { - mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); - return MV_ERROR; - } - } - - switch (pciMode & PMR_PCI_64_MASK) - { - case PMR_PCI_64_64BIT: - pPciMode->pciWidth = MV_PCI_64; - break; - - case PMR_PCI_64_32BIT: - pPciMode->pciWidth = MV_PCI_32; - break; - - default: - { - mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); - return MV_ERROR; - } - } - - return MV_OK; -} - -/******************************************************************************* -* mvPciRetrySet - Set PCI retry counters -* -* DESCRIPTION: -* This function specifies the number of times the PCI controller -* retries a transaction before it quits. -* Applies to the PCI Master when acting as a requester. -* Applies to the PCI slave when acting as a completer (PCI-X mode). -* A 0x00 value means a "retry forever". -* -* INPUT: -* pciIf - PCI interface number. -* counter - Number of times PCI controller retry. Use counter value -* up to PRR_RETRY_CNTR_MAX. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -{ - MV_U32 pciRetry; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); - return MV_BAD_PARAM; - } - - if (counter >= PRR_RETRY_CNTR_MAX) - { - mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); - return MV_BAD_PARAM; - - } - - /* Reading PCI retry register */ - pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); - - pciRetry &= ~PRR_RETRY_CNTR_MASK; - - pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); - - /* write new value */ - MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); - - return MV_OK; -} - - -/******************************************************************************* -* mvPciDiscardTimerSet - Set PCI discard timer -* -* DESCRIPTION: -* This function set PCI discard timer. -* In conventional PCI mode: -* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -* read buffers (non-completed delayed read) before invalidate the buffer. -* Set to '0' to disable the timer. The PCI slave waits for delayed -* read completion forever. -* In PCI-X mode: -* Specifies the number of PCLK cycles the PCI master waits for split -* completion transaction, before it invalidates the pre-allocated read -* buffer. -* Set to '0' to disable the timer. The PCI master waits for split -* completion forever. -* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -* unless using the "wait for ever" setting 0x0. -* NOTE: Must not be updated while there are pending read requests. -* -* INPUT: -* pciIf - PCI interface number. -* pClkCycles - Number of PCI clock cycles. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -{ - MV_U32 pciDiscardTimer; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", - pciIf); - return MV_BAD_PARAM; - } - - if (pClkCycles >= PDTR_TIMER_MIN) - { - mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", - pClkCycles); - return MV_BAD_PARAM; - - } - - /* Read PCI Discard Timer */ - pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); - - pciDiscardTimer &= ~PDTR_TIMER_MASK; - - pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); - - /* Write new value */ - MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); - - return MV_OK; - -} - -/* PCI Arbiter routines */ - -/******************************************************************************* -* mvPciArbEnable - PCI arbiter enable/disable -* -* DESCRIPTION: -* This fuction enable/disables a given PCI interface arbiter. -* NOTE: Arbiter setting can not be changed while in work. It should only -* be set once. -* INPUT: -* pciIf - PCI interface number. -* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -{ - MV_U32 regVal; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); - return MV_ERROR; - } - - /* Set PCI Arbiter Control register according to default configuration */ - regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); - - /* Make sure arbiter disabled before changing its values */ - MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); - - regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; - - regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ - - if (MV_TRUE == enable) - { - regVal |= PACR_ARB_ENABLE; - } - else - { - regVal &= ~PACR_ARB_ENABLE; - } - - /* Write to register */ - MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); - - return MV_OK; -} - - -/******************************************************************************* -* mvPciArbParkDis - Disable arbiter parking on agent -* -* DESCRIPTION: -* This function disables the PCI arbiter from parking on the given agent -* list. -* -* INPUT: -* pciIf - PCI interface number. -* pciAgentMask - When a bit in the mask is set to '1', parking on -* the associated PCI master is disabled. Mask bit -* refers to bit 0 - 6. For example disable parking on PCI -* agent 3 set pciAgentMask 0x4 (bit 3 is set). -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -{ - MV_U32 pciArbiterCtrl; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); - return MV_ERROR; - } - - /* Reading Arbiter Control register */ - pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); - - /* Arbiter must be disabled before changing parking */ - MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); - - /* do the change */ - pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; - pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); - - /* writing new value ( if th earbiter was enabled before the change */ - /* here it will be reenabled */ - MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); - - return MV_OK; -} - - -/******************************************************************************* -* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -* -* DESCRIPTION: -* This function sets the maximum number of cycles that the arbiter -* waits for a PCI master to respond to its grant assertion. If a -* PCI agent fails to respond within this time, the PCI arbiter aborts -* the transaction and performs a new arbitration cycle. -* NOTE: Value must be greater than '1' for conventional PCI and -* greater than '5' for PCI-X. -* -* INPUT: -* pciIf - PCI interface number. -* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -* master detection is disabled. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -{ - MV_U32 pciArbiterCtrl; - MV_U32 pciMode; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", - pciIf); - return MV_BAD_PARAM; - } - - /* Checking PCI mode and if pClkCycles is legal value */ - pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); - pciMode &= PMR_PCI_MODE_MASK; - - if (PMR_PCI_MODE_CONV == pciMode) - { - if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) - return MV_ERROR; - } - else - { - if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) - return MV_ERROR; - } - - pClkCycles <<= PACR_BROKEN_VAL_OFFS; - - /* Reading Arbiter Control register */ - pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); - pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; - pciArbiterCtrl |= pClkCycles; - - /* Arbiter must be disabled before changing broken detection */ - MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); - - /* writing new value ( if th earbiter was enabled before the change */ - /* here it will be reenabled */ - - MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); - - return MV_OK; -} - -/* PCI configuration space read write */ - -/******************************************************************************* -* mvPciConfigRead - Read from configuration space -* -* DESCRIPTION: -* This function performs a 32 bit read from PCI configuration space. -* It supports both type 0 and type 1 of Configuration Transactions -* (local and over bridge). In order to read from local bus segment, use -* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -* will result configuration transaction of type 1 (over bridge). -* -* INPUT: -* pciIf - PCI interface number. -* bus - PCI segment bus number. -* dev - PCI device number. -* func - Function number. -* regOffs - Register offset. -* -* OUTPUT: -* None. -* -* RETURN: -* 32bit register data, 0xffffffff on error -* -*******************************************************************************/ -MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, - MV_U32 regOff) -{ - MV_U32 pciData = 0; - - /* Parameter checking */ - if (PCI_DEFAULT_IF != pciIf) - { - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); - return 0xFFFFFFFF; - } - } - - if (dev >= MAX_PCI_DEVICES) - { - DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); - return 0xFFFFFFFF; - } - - if (func >= MAX_PCI_FUNCS) - { - DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); - return 0xFFFFFFFF; - } - - if (bus >= MAX_PCI_BUSSES) - { - DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); - return MV_ERROR; - } - - - /* Creating PCI address to be passed */ - pciData |= (bus << PCAR_BUS_NUM_OFFS); - pciData |= (dev << PCAR_DEVICE_NUM_OFFS); - pciData |= (func << PCAR_FUNC_NUM_OFFS); - pciData |= (regOff & PCAR_REG_NUM_MASK); - - pciData |= PCAR_CONFIG_EN; - - /* Write the address to the PCI configuration address register */ - MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); - - /* In order to let the PCI controller absorbed the address of the read */ - /* transaction we perform a validity check that the address was written */ - if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) - { - return MV_ERROR; - } - /* Read the Data returned in the PCI Data register */ - pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); - - return pciData; -} - -/******************************************************************************* -* mvPciConfigWrite - Write to configuration space -* -* DESCRIPTION: -* This function performs a 32 bit write to PCI configuration space. -* It supports both type 0 and type 1 of Configuration Transactions -* (local and over bridge). In order to write to local bus segment, use -* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -* will result configuration transaction of type 1 (over bridge). -* -* INPUT: -* pciIf - PCI interface number. -* bus - PCI segment bus number. -* dev - PCI device number. -* func - Function number. -* regOffs - Register offset. -* data - 32bit data. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, - MV_U32 func, MV_U32 regOff, MV_U32 data) -{ - MV_U32 pciData = 0; - - /* Parameter checking */ - if (PCI_DEFAULT_IF != pciIf) - { - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", - pciIf); - return 0xFFFFFFFF; - } - } - - if (dev >= MAX_PCI_DEVICES) - { - mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); - return MV_BAD_PARAM; - } - - if (func >= MAX_PCI_FUNCS) - { - mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); - return MV_ERROR; - } - - if (bus >= MAX_PCI_BUSSES) - { - mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); - return MV_ERROR; - } - - /* Creating PCI address to be passed */ - pciData |= (bus << PCAR_BUS_NUM_OFFS); - pciData |= (dev << PCAR_DEVICE_NUM_OFFS); - pciData |= (func << PCAR_FUNC_NUM_OFFS); - pciData |= (regOff & PCAR_REG_NUM_MASK); - - pciData |= PCAR_CONFIG_EN; - - /* Write the address to the PCI configuration address register */ - MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); - - /* In order to let the PCI controller absorbed the address of the read */ - /* transaction we perform a validity check that the address was written */ - if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) - { - return MV_ERROR; - } - - /* Write the Data passed to the PCI Data register */ - MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); - - return MV_OK; -} - -/******************************************************************************* -* mvPciMasterEnable - Enable/disale PCI interface master transactions. -* -* DESCRIPTION: -* This function performs read modified write to PCI command status -* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -* master is allowed to gain ownership on the bus, otherwise it is -* incapable to do so. -* -* INPUT: -* pciIf - PCI interface number. -* enable - Enable/disable parameter. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -{ - MV_U32 pciCommandStatus; - MV_U32 RegOffs; - MV_U32 localBus; - MV_U32 localDev; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); - return MV_ERROR; - } - - localBus = mvPciLocalBusNumGet(pciIf); - localDev = mvPciLocalDevNumGet(pciIf); - - RegOffs = PCI_STATUS_AND_COMMAND; - - pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); - - if (MV_TRUE == enable) - { - pciCommandStatus |= PSCR_MASTER_EN; - } - else - { - pciCommandStatus &= ~PSCR_MASTER_EN; - } - - mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); - - return MV_OK; -} - - -/******************************************************************************* -* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -* -* DESCRIPTION: -* This function performs read modified write to PCI command status -* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -* the PCI slave is allowed to respond to PCI IO space access (bit 0) -* and PCI memory space access (bit 1). -* -* INPUT: -* pciIf - PCI interface number. -* dev - PCI device number. -* enable - Enable/disable parameter. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -{ - MV_U32 pciCommandStatus; - MV_U32 RegOffs; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); - return MV_BAD_PARAM; - } - if (dev >= MAX_PCI_DEVICES) - { - mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); - return MV_BAD_PARAM; - - } - - RegOffs = PCI_STATUS_AND_COMMAND; - - pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); - - if (MV_TRUE == enable) - { - pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); - } - else - { - pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); - } - - mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); - - return MV_OK; -} - -/******************************************************************************* -* mvPciLocalBusNumSet - Set PCI interface local bus number. -* -* DESCRIPTION: -* This function sets given PCI interface its local bus number. -* Note: In case the PCI interface is PCI-X, the information is read-only. -* -* INPUT: -* pciIf - PCI interface number. -* busNum - Bus number. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_NOT_ALLOWED in case PCI interface is PCI-X. -* MV_BAD_PARAM on bad parameters , -* otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -{ - MV_U32 pciP2PConfig; - MV_PCI_MODE pciMode; - MV_U32 localBus; - MV_U32 localDev; - - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); - return MV_BAD_PARAM; - } - if (busNum >= MAX_PCI_BUSSES) - { - mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); - return MV_ERROR; - - } - - localBus = mvPciLocalBusNumGet(pciIf); - localDev = mvPciLocalDevNumGet(pciIf); - - - /* PCI interface mode */ - mvPciModeGet(pciIf, &pciMode); - - /* if PCI type is PCI-X then it is not allowed to change the dev number */ - if (MV_PCIX == pciMode.pciType) - { - pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); - - pciP2PConfig &= ~PXS_BN_MASK; - - pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; - - mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); - - } - else - { - pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); - - pciP2PConfig &= ~PPCR_BUS_NUM_MASK; - - pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; - - MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); - - } - - - return MV_OK; -} - - -/******************************************************************************* -* mvPciLocalBusNumGet - Get PCI interface local bus number. -* -* DESCRIPTION: -* This function gets the local bus number of a given PCI interface. -* -* INPUT: -* pciIf - PCI interface number. -* -* OUTPUT: -* None. -* -* RETURN: -* Local bus number.0xffffffff on Error -* -*******************************************************************************/ -MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -{ - MV_U32 pciP2PConfig; - - /* Parameter checking */ - if (PCI_DEFAULT_IF != pciIf) - { - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", - pciIf); - return 0xFFFFFFFF; - } - } - - pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); - pciP2PConfig &= PPCR_BUS_NUM_MASK; - return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -} - - -/******************************************************************************* -* mvPciLocalDevNumSet - Set PCI interface local device number. -* -* DESCRIPTION: -* This function sets given PCI interface its local device number. -* Note: In case the PCI interface is PCI-X, the information is read-only. -* -* INPUT: -* pciIf - PCI interface number. -* devNum - Device number. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -* otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -{ - MV_U32 pciP2PConfig; - MV_PCI_MODE pciMode; - MV_U32 localBus; - MV_U32 localDev; - - /* Parameter checking */ - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); - return MV_BAD_PARAM; - } - if (devNum >= MAX_PCI_DEVICES) - { - mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", - devNum); - return MV_BAD_PARAM; - - } - - localBus = mvPciLocalBusNumGet(pciIf); - localDev = mvPciLocalDevNumGet(pciIf); - - /* PCI interface mode */ - mvPciModeGet(pciIf, &pciMode); - - /* if PCI type is PCIX then it is not allowed to change the dev number */ - if (MV_PCIX == pciMode.pciType) - { - pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); - - pciP2PConfig &= ~PXS_DN_MASK; - - pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; - - mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); - } - else - { - pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); - - pciP2PConfig &= ~PPCR_DEV_NUM_MASK; - - pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; - - MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); - } - - return MV_OK; -} - -/******************************************************************************* -* mvPciLocalDevNumGet - Get PCI interface local device number. -* -* DESCRIPTION: -* This function gets the local device number of a given PCI interface. -* -* INPUT: -* pciIf - PCI interface number. -* -* OUTPUT: -* None. -* -* RETURN: -* Local device number. 0xffffffff on Error -* -*******************************************************************************/ -MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -{ - MV_U32 pciP2PConfig; - - /* Parameter checking */ - - if (PCI_DEFAULT_IF != pciIf) - { - if (pciIf >= mvCtrlPciMaxIfGet()) - { - mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", - pciIf); - return 0xFFFFFFFF; - } - } - - pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); - - pciP2PConfig &= PPCR_DEV_NUM_MASK; - - return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -} - - - - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h deleted file mode 100644 index 474633627e..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h +++ /dev/null @@ -1,185 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -#ifndef __INCPCIH -#define __INCPCIH - -#include "mvCommon.h" -#include "mvOs.h" -#include "ctrlEnv/mvCtrlEnvSpec.h" -#include "pci/mvPciRegs.h" - - -/* NOTE not supported in this driver: - - Built In Self Test (BIST) - Vital Product Data (VPD) - Message Signaled Interrupt (MSI) - Power Management - Compact PCI Hot Swap - Header retarget - -Registers not supported: -1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -*/ - -/* defines */ -/* The number of supported PCI interfaces depend on Marvell controller */ -/* device number. This device number ID is located on the PCI unit */ -/* configuration header. This creates a loop where calling PCI */ -/* configuration read/write routine results a call to get PCI configuration */ -/* information etc. This macro defines a default PCI interface. This PCI */ -/* interface is sure to exist. */ -#define PCI_DEFAULT_IF 0 - - -/* typedefs */ -/* The Marvell controller supports both conventional PCI and PCI-X. */ -/* This enumeration describes the PCI type. */ -typedef enum _mvPciType -{ - MV_PCI_CONV, /* Conventional PCI */ - MV_PCIX /* PCI-X */ -}MV_PCI_TYPE; - -typedef enum _mvPciMod -{ - MV_PCI_MOD_HOST, - MV_PCI_MOD_DEVICE -}MV_PCI_MOD; - - -/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -/* This enumerator describes PCI width */ -typedef enum _mvPciWidth -{ - MV_PCI_32, /* PCI width 32bit */ - MV_PCI_64 /* PCI width 64bit */ -}MV_PCI_WIDTH; - -/* This structure describes the PCI unit configured type, speed and width. */ -typedef struct _mvPciMode -{ - MV_PCI_TYPE pciType; /* PCI type */ - MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ - MV_PCI_WIDTH pciWidth; /* PCI bus width */ -}MV_PCI_MODE; - -/* mvPciInit - Initialize PCI interfaces*/ -MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); - -/* mvPciCommandSet - Set PCI comman register value.*/ -MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); - -/* mvPciModeGet - Get PCI interface mode.*/ -MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); - -/* mvPciRetrySet - Set PCI retry counters*/ -MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); - -/* mvPciDiscardTimerSet - Set PCI discard timer*/ -MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); - -/* mvPciArbEnable - PCI arbiter enable/disable*/ -MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); - -/* mvPciArbParkDis - Disable arbiter parking on agent */ -MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); - -/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); - -/* mvPciConfigRead - Read from configuration space */ -MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, - MV_U32 func,MV_U32 regOff); - -/* mvPciConfigWrite - Write to configuration space */ -MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, - MV_U32 func, MV_U32 regOff, MV_U32 data); - -/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); - -/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); - -/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); - -/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); - -/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); - -/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); - - -#endif /* #ifndef __INCPCIH */ - - - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h deleted file mode 100644 index 89d0ef12d7..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h +++ /dev/null @@ -1,411 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCPCIREGSH -#define __INCPCIREGSH - - -#include "pci-if/mvPciIfRegs.h" -/* defines */ -#define MAX_PCI_DEVICES 32 -#define MAX_PCI_FUNCS 8 -#define MAX_PCI_BUSSES 128 - -/* enumerators */ - -/* This enumerator described the possible PCI slave targets. */ -/* PCI slave targets are designated memory/IO address spaces that the */ -/* PCI slave targets can access. They are also refered as "targets" */ -/* this enumeratoe order is determined by the content of : - PCI_BASE_ADDR_ENABLE_REG */ - - -/* registers offsetes defines */ - - - -/*************************/ -/* PCI control registers */ -/*************************/ -/* maen : should add new registers */ -#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ - (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ - (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ - (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) - -#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) - -/* PCI Dll Control (PDC)*/ -#define PDC_DLL_EN BIT0 - - -/* PCI Command Register (PCR) */ -#define PCR_MASTER_BYTE_SWAP_EN BIT0 -#define PCR_MASTER_WR_COMBINE_EN BIT4 -#define PCR_MASTER_RD_COMBINE_EN BIT5 -#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -#define PCR_MASTER_WORD_SWAP_EN BIT10 -#define PCR_SLAVE_WORD_SWAP_EN BIT11 -#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -#define PCR_MASTER_DAC_EN BIT17 -#define PCR_MASTER_M64_ALLIGN BIT18 -#define PCR_ERRORS_PROPAGATION_EN BIT19 -#define PCR_SLAVE_SWAP_ENABLE BIT20 -#define PCR_MASTER_SWAP_ENABLE BIT21 -#define PCR_MASTER_INT_SWAP_EN BIT22 -#define PCR_LOOP_BACK_ENABLE BIT23 -#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -#define PCR_SLAVE_INTREG_BYTE_SWAP \ - (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -#define PCR_SLAVE_INTREG_NO_SWAP \ - (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -#define PCR_SLAVE_INTREG_BYTE_WORD \ - (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -#define PCR_SLAVE_INTREG_WORD_SWAP \ - (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -#define PCR_RESET_REASSERTION_EN BIT26 -#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -#define PCR_PCI_TO_CPU_ORDER_EN BIT30 - -/* PCI Mode Register (PMR) */ -#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) - -#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) - -#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) - -#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ - -#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) - - -/* PCI Retry Register (PRR) */ -#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -#define PRR_RETRY_CNTR_MAX 0xff -#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) - - -/* PCI Discard Timer Register (PDTR) */ -#define PDTR_TIMER_OFFS 0 /* Timer */ -#define PDTR_TIMER_MAX 0xffff -#define PDTR_TIMER_MIN 0x7F -#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) - - -/* PCI Arbiter Control Register (PACR) */ -#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ - -#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -#define PACR_BROKEN_VAL_CONV_MIN 0x2 -#define PACR_BROKEN_VAL_PCIX_MIN 0x6 - -#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -#define PACR_PARK_DIS_MAX_AGENT 0x3f -#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<<PACR_PARK_DIS_OFFS) -#define PACR_PARK_DIS(agent) ((1 << (agent)) << PACR_PARK_DIS_OFFS) - -#define PACR_ARB_ENABLE BIT31 /* Enable Internal Arbiter */ - - -/* PCI P2P Configuration Register (PPCR) */ -#define PPCR_2ND_BUS_L_OFFS 0 /* 2nd PCI Interface Bus Range Lower */ -#define PPCR_2ND_BUS_L_MASK (0xff << PPCR_2ND_BUS_L_OFFS) - -#define PPCR_2ND_BUS_H_OFFS 8 /* 2nd PCI Interface Bus Range Upper */ -#define PPCR_2ND_BUS_H_MASK (0xff << PPCR_2ND_BUS_H_OFFS) - -#define PPCR_BUS_NUM_OFFS 16 /* The PCI interface's Bus number */ -#define PPCR_BUS_NUM_MASK (0xff << PPCR_BUS_NUM_OFFS) - -#define PPCR_DEV_NUM_OFFS 24 /* The PCI interface’s Device number */ -#define PPCR_DEV_NUM_MASK (0xff << PPCR_DEV_NUM_OFFS) - - -/* PCI Access Control Base Low Register (PACBLR) */ -#define PACBLR_EN BIT0 /* Access control window enable */ - -#define PACBLR_ACCPROT BIT4 /* Access Protect */ -#define PACBLR_WRPROT BIT5 /* Write Protect */ - -#define PACBLR_PCISWAP_OFFS 6 /* PCI slave Data Swap Control */ -#define PACBLR_PCISWAP_MASK (0x3 << PACBLR_PCISWAP_OFFS) -#define PACBLR_PCISWAP_BYTE (0x0 << PACBLR_PCISWAP_OFFS) -#define PACBLR_PCISWAP_NO_SWAP (0x1 << PACBLR_PCISWAP_OFFS) -#define PACBLR_PCISWAP_BYTE_WORD (0x2 << PACBLR_PCISWAP_OFFS) -#define PACBLR_PCISWAP_WORD (0x3 << PACBLR_PCISWAP_OFFS) - -#define PACBLR_RDMBURST_OFFS 8 /* Read Max Burst */ -#define PACBLR_RDMBURST_MASK (0x3 << PACBLR_RDMBURST_OFFS) -#define PACBLR_RDMBURST_32BYTE (0x0 << PACBLR_RDMBURST_OFFS) -#define PACBLR_RDMBURST_64BYTE (0x1 << PACBLR_RDMBURST_OFFS) -#define PACBLR_RDMBURST_128BYTE (0x2 << PACBLR_RDMBURST_OFFS) - -#define PACBLR_RDSIZE_OFFS 10 /* Typical PCI read transaction Size. */ -#define PACBLR_RDSIZE_MASK (0x3 << PACBLR_RDSIZE_OFFS) -#define PACBLR_RDSIZE_32BYTE (0x0 << PACBLR_RDSIZE_OFFS) -#define PACBLR_RDSIZE_64BYTE (0x1 << PACBLR_RDSIZE_OFFS) -#define PACBLR_RDSIZE_128BYTE (0x2 << PACBLR_RDSIZE_OFFS) -#define PACBLR_RDSIZE_256BYTE (0x3 << PACBLR_RDSIZE_OFFS) - -#define PACBLR_BASE_L_OFFS 12 /* Corresponds to address bits [31:12] */ -#define PACBLR_BASE_L_MASK (0xfffff << PACBLR_BASE_L_OFFS) -#define PACBLR_BASE_L_ALIGNMENT (1 << PACBLR_BASE_L_OFFS) -#define PACBLR_BASE_ALIGN_UP(base) \ - ((base+PACBLR_BASE_L_ALIGNMENT)&PACBLR_BASE_L_MASK) -#define PACBLR_BASE_ALIGN_DOWN(base) (base & PACBLR_BASE_L_MASK) - - -/* PCI Access Control Base High Register (PACBHR) */ -#define PACBHR_BASE_H_OFFS 0 /* Corresponds to address bits [63:32] */ -#define PACBHR_CTRL_BASE_H_MASK (0xffffffff << PACBHR_BASE_H_OFFS) - -/* PCI Access Control Size Register (PACSR) */ -#define PACSR_WRMBURST_OFFS 8 /* Write Max Burst */ -#define PACSR_WRMBURST_MASK (0x3 << PACSR_WRMBURST_OFFS) -#define PACSR_WRMBURST_32BYTE (0x0 << PACSR_WRMBURST_OFFS) -#define PACSR_WRMBURST_64BYTE (0x1 << PACSR_WRMBURST_OFFS) -#define PACSR_WRMBURST_128BYTE (0x2 << PACSR_WRMBURST_OFFS) - -#define PACSR_PCI_ORDERING BIT11 /* PCI Ordering required */ - -#define PACSR_SIZE_OFFS 12 /* PCI access window size */ -#define PACSR_SIZE_MASK (0xfffff << PACSR_SIZE_OFFS) -#define PACSR_SIZE_ALIGNMENT (1 << PACSR_SIZE_OFFS) -#define PACSR_SIZE_ALIGN_UP(size) \ - ((size+PACSR_SIZE_ALIGNMENT)&PACSR_SIZE_MASK) -#define PACSR_SIZE_ALIGN_DOWN(size) (size & PACSR_SIZE_MASK) - - -/***************************************/ -/* PCI Configuration Access Registers */ -/***************************************/ - -#define PCI_CONFIG_ADDR_REG(pciIf) (0x30C78 - ((pciIf) * 0x80) ) -#define PCI_CONFIG_DATA_REG(pciIf) (0x30C7C - ((pciIf) * 0x80) ) -#define PCI_INT_ACK_REG(pciIf) (0x30C34 + ((pciIf) * 0x80) ) - -/* PCI Configuration Address Register (PCAR) */ -#define PCAR_REG_NUM_OFFS 2 -#define PCAR_REG_NUM_MASK (0x3F << PCAR_REG_NUM_OFFS) - -#define PCAR_FUNC_NUM_OFFS 8 -#define PCAR_FUNC_NUM_MASK (0x7 << PCAR_FUNC_NUM_OFFS) - -#define PCAR_DEVICE_NUM_OFFS 11 -#define PCAR_DEVICE_NUM_MASK (0x1F << PCAR_DEVICE_NUM_OFFS) - -#define PCAR_BUS_NUM_OFFS 16 -#define PCAR_BUS_NUM_MASK (0xFF << PCAR_BUS_NUM_OFFS) - -#define PCAR_CONFIG_EN BIT31 - - -/***************************************/ -/* PCI Configuration registers */ -/***************************************/ - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -/* Marvell Specific */ -#define PCI_SCS0_BASE_ADDR_LOW 0x010 -#define PCI_SCS0_BASE_ADDR_HIGH 0x014 -#define PCI_SCS1_BASE_ADDR_LOW 0x018 -#define PCI_SCS1_BASE_ADDR_HIGH 0x01C -#define PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_L 0x020 -#define PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_H 0x024 - -/* capability list */ -#define PCI_POWER_MNG_CAPABILITY 0x040 -#define PCI_POWER_MNG_STATUS_CONTROL 0x044 -#define PCI_VPD_ADDRESS_REG 0x048 -#define PCI_VPD_DATA_REG 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDR 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCIX_COMMAND 0x060 -#define PCIX_STATUS 0x064 -#define PCI_COMPACT_PCI_HOT_SWAP 0x068 - - -/*********************************************/ -/* PCI Configuration, Function 1, Registers */ -/*********************************************/ - -#define PCI_SCS2_BASE_ADDR_LOW 0x10 -#define PCI_SCS2_BASE_ADDR_HIGH 0x14 -#define PCI_SCS3_BASE_ADDR_LOW 0x18 -#define PCI_SCS3_BASE_ADDR_HIGH 0x1c - - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define PCI_DEVCS0_BASE_ADDR_LOW 0x10 -#define PCI_DEVCS0_BASE_ADDR_HIGH 0x14 -#define PCI_DEVCS1_BASE_ADDR_LOW 0x18 -#define PCI_DEVCS1_BASE_ADDR_HIGH 0x1c -#define PCI_DEVCS2_BASE_ADDR_LOW 0x20 -#define PCI_DEVCS2_BASE_ADDR_HIGH 0x24 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define PCI_BOOTCS_BASE_ADDR_LOW 0x18 -#define PCI_BOOTCS_BASE_ADDR_HIGH 0x1c - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x10 -#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x14 -#define PCI_P2P_IO_BASE_ADDR 0x20 -#define PCI_INTER_REGS_IO_MAPPED_BASE_ADDR 0x24 - -/* PCIX_STATUS register fields (PXS) */ - -#define PXS_FN_OFFS 0 /* Description Number */ -#define PXS_FN_MASK (0x7 << PXS_FN_OFFS) - -#define PXS_DN_OFFS 3 /* Device Number */ -#define PXS_DN_MASK (0x1f << PXS_DN_OFFS) - -#define PXS_BN_OFFS 8 /* Bus Number */ -#define PXS_BN_MASK (0xff << PXS_BN_OFFS) - - -/* PCI Error Report Register Map */ -#define PCI_SERRN_MASK_REG(pciIf) (0x30c28 + (pciIf * 0x80)) -#define PCI_CAUSE_REG(pciIf) (0x31d58 + (pciIf * 0x80)) -#define PCI_MASK_REG(pciIf) (0x31d5C + (pciIf * 0x80)) -#define PCI_ERROR_ADDR_LOW_REG(pciIf) (0x31d40 + (pciIf * 0x80)) -#define PCI_ERROR_ADDR_HIGH_REG(pciIf) (0x31d44 + (pciIf * 0x80)) -#define PCI_ERROR_ATTRIBUTE_REG(pciIf) (0x31d48 + (pciIf * 0x80)) -#define PCI_ERROR_COMMAND_REG(pciIf) (0x31d50 + (pciIf * 0x80)) - -/* PCI Interrupt Cause Register (PICR) */ -#define PICR_ERR_SEL_OFFS 27 -#define PICR_ERR_SEL_MASK (0x1f << PICR_ERR_SEL_OFFS) - -/* PCI Error Command Register (PECR) */ -#define PECR_ERR_CMD_OFFS 0 -#define PECR_ERR_CMD_MASK (0xf << PECR_ERR_CMD_OFFS) -#define PECR_DAC BIT4 - - -/* defaults */ -/* Set bits means value is about to change according to new value */ -#define PCI_COMMAND_DEFAULT_MASK 0xffffdff1 -#define PCI_COMMAND_DEFAULT \ - (PCR_MASTER_WR_TRIG_WHOLE | \ - PCR_MASTER_RD_TRIG_WHOLE | \ - PCR_MASTER_MEM_RD_LINE_EN | \ - PCR_MASTER_MEM_RD_MULT_EN | \ - PCR_NS_ACCORDING_RCV_TRANS | \ - PCR_MASTER_PCIX_REQ64N_EN | \ - PCR_MASTER_DAC_EN | \ - PCR_MASTER_M64_ALLIGN | \ - PCR_ERRORS_PROPAGATION_EN) - - -#define PCI_ARBITER_CTRL_DEFAULT_MASK 0x801fc07a -#define PCI_ARBITER_CTRL_DEFAULT \ - (PACR_BROKEN_VAL_PCIX_MIN << PACR_BROKEN_VAL_OFFS) - - -#endif /* #ifndef __INCPCIREGSH */ - |