diff options
Diffstat (limited to 'target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2')
10 files changed, 0 insertions, 5970 deletions
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt deleted file mode 100644 index 38a9264400..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvCompVer.txt +++ /dev/null @@ -1,4 +0,0 @@ -Global HAL Version: FEROCEON_HAL_3_1_7
-Unit HAL Version: 3.1.4
-Description: This component includes an implementation of the unit HAL drivers
-
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c deleted file mode 100644 index a214c95cd1..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c +++ /dev/null @@ -1,1855 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -/* includes */ -#include "ddr2/mvDramIf.h" -#include "ctrlEnv/sys/mvCpuIf.h" - -#include "ddr2/mvDramIfStaticInit.h" - -/* #define MV_DEBUG */ -#ifdef MV_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -/* DRAM bank presence encoding */ -#define BANK_PRESENT_CS0 0x1 -#define BANK_PRESENT_CS0_CS1 0x3 -#define BANK_PRESENT_CS0_CS2 0x5 -#define BANK_PRESENT_CS0_CS1_CS2 0x7 -#define BANK_PRESENT_CS0_CS2_CS3 0xd -#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf - -/* locals */ -#ifndef MV_STATIC_DRAM_ON_BOARD -static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTmode ); -static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -static MV_U32 sdramModeRegCalc(MV_U32 minCas); -static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1); -static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk); -static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl); -static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk); -static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas); -static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas); -#endif -MV_32 DRAM_CS_Order[MV_DRAM_MAX_CS] = {N_A - -#ifdef MV_INCLUDE_SDRAM_CS1 - ,N_A -#endif -#ifdef MV_INCLUDE_SDRAM_CS2 - ,N_A -#endif -#ifdef MV_INCLUDE_SDRAM_CS3 - ,N_A -#endif - }; -/* Get DRAM size of CS num */ -MV_U32 mvDramCsSizeGet(MV_U32 csNum) -{ - MV_DRAM_BANK_INFO bankInfo; - MV_U32 size, deviceW, dimmW; -#ifdef MV78XX0 - MV_U32 temp; -#endif - - if(MV_OK == mvDramBankInfoGet(csNum, &bankInfo)) - { - if (0 == bankInfo.size) - return 0; - - /* Note that the Dimm width might be different then the device DRAM width */ -#ifdef MV78XX0 - temp = MV_REG_READ(SDRAM_CONFIG_REG); - deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -#else - deviceW = 16 /* KW family */; -#endif - dimmW = bankInfo.dataWidth - (bankInfo.dataWidth % 16); - size = ((bankInfo.size << 20) / (dimmW/deviceW)); - return size; - } - else - return 0; -} -/******************************************************************************* -* mvDramIfDetect - Prepare DRAM interface configuration values. -* -* DESCRIPTION: -* This function implements the full DRAM detection and timing -* configuration for best system performance. -* Since this routine runs from a ROM device (Boot Flash), its stack -* resides on RAM, that might be the system DRAM. Changing DRAM -* configuration values while keeping vital data in DRAM is risky. That -* is why the function does not preform the configuration setting but -* prepare those in predefined 32bit registers (in this case IDMA -* registers are used) for other routine to perform the settings. -* The function will call for board DRAM SPD information for each DRAM -* chip select. The function will then analyze those SPD parameters of -* all DRAM banks in order to decide on DRAM configuration compatible -* for all DRAM banks. -* The function will set the CPU DRAM address decode registers. -* Note: This routine prepares values that will overide configuration of -* mvDramBasicAsmInit(). -* -* INPUT: -* forcedCl - Forced CAL Latency. If equal to zero, do not force. -* eccDisable - Force down the ECC. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable) -{ - MV_32 MV_DRAM_CS_order[MV_DRAM_MAX_CS] = { - SDRAM_CS0 -#ifdef MV_INCLUDE_SDRAM_CS1 - ,SDRAM_CS1 -#endif -#ifdef MV_INCLUDE_SDRAM_CS2 - ,SDRAM_CS2 -#endif -#ifdef MV_INCLUDE_SDRAM_CS3 - ,SDRAM_CS3 -#endif - }; - MV_U32 busClk, deviceW, dimmW; - MV_U32 numOfAllDevices = 0; - MV_STATUS TTMode; -#ifndef MV_STATIC_DRAM_ON_BOARD - MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; - MV_U32 size, base = 0, i, j, temp, busClkPs; - MV_U8 minCas; - MV_CPU_DEC_WIN dramDecWin; - dramDecWin.addrWin.baseHigh = 0; -#endif - - busClk = mvBoardSysClkGet(); - - if (0 == busClk) - { - mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); - return MV_ERROR; - } - -#ifndef MV_STATIC_DRAM_ON_BOARD - - busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ - /* we will use bank 0 as the representative of the all the DRAM banks, */ - /* since bank 0 must exist. */ - for(i = 0; i < MV_DRAM_MAX_CS; i++) - { - /* if Bank exist */ - if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) - { - DB(mvOsPrintf("Dram: Find bank %d\n", i)); - /* check it isn't SDRAM */ - if(bankInfo[i].memoryType != MEM_TYPE_DDR2) - { - mvOsOutput("Dram: ERR. SDRAM type not supported !!!\n"); - return MV_ERROR; - } - - /* All banks must support the Mclk freqency */ - if(bankInfo[i].minCycleTimeAtMaxCasLatPs > busClkPs) - { - mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); - return MV_ERROR; - } - - /* All banks must support registry in order to activate it */ - if(bankInfo[i].registeredAddrAndControlInputs != - bankInfo[0].registeredAddrAndControlInputs) - { - mvOsOutput("Dram: ERR. different Registered settings !!!\n"); - return MV_ERROR; - } - - /* All banks must support same ECC mode */ - if(bankInfo[i].errorCheckType != - bankInfo[0].errorCheckType) - { - mvOsOutput("Dram: ERR. different ECC settings !!!\n"); - return MV_ERROR; - } - - } - else - { - if( i == 0 ) /* bank 0 doesn't exist */ - { - mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); - return MV_ERROR; - } - else - { - DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); - bankInfo[i].size = 0; /* Mark this bank as non exist */ - } - } - } - -#ifdef MV_INCLUDE_SDRAM_CS2 - if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) - { - MV_DRAM_CS_order[0] = SDRAM_CS2; - MV_DRAM_CS_order[1] = SDRAM_CS3; - MV_DRAM_CS_order[2] = SDRAM_CS0; - MV_DRAM_CS_order[3] = SDRAM_CS1; - DRAM_CS_Order[0] = SDRAM_CS2; - DRAM_CS_Order[1] = SDRAM_CS3; - DRAM_CS_Order[2] = SDRAM_CS0; - DRAM_CS_Order[3] = SDRAM_CS1; - - } - else -#endif - { - MV_DRAM_CS_order[0] = SDRAM_CS0; - MV_DRAM_CS_order[1] = SDRAM_CS1; - DRAM_CS_Order[0] = SDRAM_CS0; - DRAM_CS_Order[1] = SDRAM_CS1; -#ifdef MV_INCLUDE_SDRAM_CS2 - MV_DRAM_CS_order[2] = SDRAM_CS2; - MV_DRAM_CS_order[3] = SDRAM_CS3; - DRAM_CS_Order[2] = SDRAM_CS2; - DRAM_CS_Order[3] = SDRAM_CS3; -#endif - } - - for(j = 0; j < MV_DRAM_MAX_CS; j++) - { - i = MV_DRAM_CS_order[j]; - - if (0 == bankInfo[i].size) - continue; - - /* Init the CPU window decode */ - /* Note that the Dimm width might be different then the device DRAM width */ -#ifdef MV78XX0 - temp = MV_REG_READ(SDRAM_CONFIG_REG); - deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -#else - deviceW = 16 /* KW family */; -#endif - dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); - size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); - - /* We can not change DRAM window settings while excecuting */ - /* code from it. That is why we skip the DRAM CS[0], saving */ - /* it to the ROM configuration routine */ - - numOfAllDevices += bankInfo[i].numberOfDevices; - if (i == MV_DRAM_CS_order[0]) - { - MV_U32 sizeToReg; - /* Translate the given window size to register format */ - sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); - /* Size parameter validity check. */ - if (-1 == sizeToReg) - { - mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" - ,i); - return MV_BAD_PARAM; - } - - DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) - sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); - sizeToReg |= SCSR_WIN_EN; - MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); - } - else - { - dramDecWin.addrWin.baseLow = base; - dramDecWin.addrWin.size = size; - dramDecWin.enable = MV_TRUE; - DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); - - /* Check if the DRAM size is more then 3GByte */ - if (base < 0xC0000000) - { - DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); - if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) - { - mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); - return MV_ERROR; - } - } - } - - base += size; - - /* update the suportedCasLatencies mask */ - bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; - } - - /* calculate minimum CAS */ - minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); - if (0 == minCas) - { - mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", - (busClk / 1000000)); - - minCas = DDR2_CL_4; /* Continue with this CAS */ - mvOsOutput("Set default CAS latency 4\n"); - } - - /* calc SDRAM_CONFIG_REG and save it to temp register */ - temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); - return MV_ERROR; - } - - /* check if ECC is enabled by the user */ - if(eccDisable) - { - /* turn off ECC*/ - temp &= ~BIT18; - } - DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG1, temp); - - /* calc SDRAM_MODE_REG and save it to temp register */ - temp = sdramModeRegCalc(minCas); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG2, temp); - - /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ - temp = sdramExtModeRegCalc(&bankInfo[0], busClk); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG10, temp); - - /* calc D_UNIT_CONTROL_LOW and save it to temp register */ - TTMode = MV_FALSE; - DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) - if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) - { - if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || - (numOfAllDevices > 18) ) - { - mvOsOutput("Enable 2T "); - TTMode = MV_TRUE; - } - } - - temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG3, temp); - - /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ - temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) - /* check if ECC is enabled by the user */ - if(eccDisable) - { - /* turn off sample stage if no ecc */ - temp &= ~SDRAM__D2P_EN;; - } - MV_REG_WRITE(DRAM_BUF_REG13, temp); - - /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ - temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG4, temp); - - /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ - temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG5, temp); - - /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ - temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG6, temp); - - sdramDDr2OdtConfig(bankInfo); - - /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ - temp = sdramDdr2TimeLoRegCalc(minCas); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG11, temp); - - /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ - temp = sdramDdr2TimeHiRegCalc(minCas); - if(-1 == temp) - { - mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); - return MV_ERROR; - } - DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) - MV_REG_WRITE(DRAM_BUF_REG12, temp); -#endif - - /* Note that DDR SDRAM Address/Control and Data pad calibration */ - /* settings is done in mvSdramIfConfig.s */ - - return MV_OK; -} - - -/******************************************************************************* -* mvDramIfBankBaseGet - Get DRAM interface bank base. -* -* DESCRIPTION: -* This function returns the 32 bit base address of a given DRAM bank. -* -* INPUT: -* bankNum - Bank number. -* -* OUTPUT: -* None. -* -* RETURN: -* DRAM bank size. If bank is disabled or paramter is invalid, the -* function returns -1. -* -*******************************************************************************/ -MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -{ - DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", - bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); - return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -} - -/******************************************************************************* -* mvDramIfBankSizeGet - Get DRAM interface bank size. -* -* DESCRIPTION: -* This function returns the size of a given DRAM bank. -* -* INPUT: -* bankNum - Bank number. -* -* OUTPUT: -* None. -* -* RETURN: -* DRAM bank size. If bank is disabled the function return '0'. In case -* or paramter is invalid, the function returns -1. -* -*******************************************************************************/ -MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -{ - DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", - bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); - return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -} - - -/******************************************************************************* -* mvDramIfSizeGet - Get DRAM interface total size. -* -* DESCRIPTION: -* This function get the DRAM total size. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* DRAM total size. In case or paramter is invalid, the function -* returns -1. -* -*******************************************************************************/ -MV_U32 mvDramIfSizeGet(MV_VOID) -{ - MV_U32 size = 0, i; - - for(i = 0; i < MV_DRAM_MAX_CS; i++) - size += mvDramIfBankSizeGet(i); - - DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); - return size; -} - -/******************************************************************************* -* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -* -* DESCRIPTION: -* The ECC single bit error threshold is the number of single bit -* errors to happen before the Dunit generates an interrupt. -* This function set single bit ECC threshold. -* -* INPUT: -* threshold - threshold. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -* -*******************************************************************************/ -MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -{ - MV_U32 regVal; - - if (threshold > SECR_THRECC_MAX) - { - return MV_BAD_PARAM; - } - - regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); - regVal &= ~SECR_THRECC_MASK; - regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); - MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); - - return MV_OK; -} - -#ifndef MV_STATIC_DRAM_ON_BOARD -/******************************************************************************* -* minCasCalc - Calculate the Minimum CAS latency which can be used. -* -* DESCRIPTION: -* Calculate the minimum CAS latency that can be used, base on the DRAM -* parameters and the SDRAM bus Clock freq. -* -* INPUT: -* busClk - the DRAM bus Clock. -* pBankInfo - bank info parameters. -* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -* -* OUTPUT: -* None -* -* RETURN: -* The minimum CAS Latency. The function returns 0 if max CAS latency -* supported by banks is incompatible with system bus clock frequancy. -* -*******************************************************************************/ - -static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -{ - MV_U32 count = 1, j; - MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ - MV_U32 startBit, stopBit; - MV_U32 minCas0 = 0, minCas2 = 0; - - - /* DDR 2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * - Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * - Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * - *********************************************************/ - - - /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ - if (forcedCl) - { - mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); - - if (forcedCl == 30) - pBankInfo->suportedCasLatencies = 0x08; - else if (forcedCl == 40) - pBankInfo->suportedCasLatencies = 0x10; - else if (forcedCl == 50) - pBankInfo->suportedCasLatencies = 0x20; - else if (forcedCl == 60) - pBankInfo->suportedCasLatencies = 0x40; - else - { - mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", - (forcedCl / 10), (forcedCl % 10)); - pBankInfo->suportedCasLatencies = 0x10; - } - - return pBankInfo->suportedCasLatencies; - } - - /* go over the supported cas mask from Max Cas down and check if the */ - /* SysClk stands in its time requirments. */ - - DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", - pBankInfo->suportedCasLatencies,busClkPs )); - count = 1; - for(j = 7; j > 0; j--) - { - if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) - { - /* Reset the bits for CL incompatible for the sysClk */ - switch (count) - { - case 1: - if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - case 2: - if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - case 3: - if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - default: - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - break; - } - } - } - - DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", - pBankInfo->suportedCasLatencies )); - - count = 1; - DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", - pBankInfo2->suportedCasLatencies,busClkPs )); - for(j = 7; j > 0; j--) - { - if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) - { - /* Reset the bits for CL incompatible for the sysClk */ - switch (count) - { - case 1: - if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) - pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - case 2: - if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) - pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - case 3: - if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) - pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - default: - pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); - break; - } - } - } - - DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", - pBankInfo2->suportedCasLatencies )); - - startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ - stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ - - for(j = startBit; j <= stopBit ; j++) - { - if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) - { - DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); - minCas0 = (BIT0 << j); - break; - } - } - - for(j = startBit; j <= stopBit ; j++) - { - if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) - { - DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); - minCas2 = (BIT0 << j); - break; - } - } - - if (minCas2 > minCas0) - return minCas2; - else - return minCas0; - - return 0; -} - -/******************************************************************************* -* sdramConfigRegCalc - Calculate sdram config register -* -* DESCRIPTION: Calculate sdram config register optimized value based -* on the bank info parameters. -* -* INPUT: -* busClk - the DRAM bus Clock. -* pBankInfo - sdram bank parameters -* -* OUTPUT: -* None -* -* RETURN: -* sdram config reg value. -* -*******************************************************************************/ -static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -{ - MV_U32 sdramConfig = 0; - MV_U32 refreshPeriod; - - busClk /= 1000000; /* we work with busClk in MHz */ - - sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); - - /* figure out the memory refresh internal */ - switch (pBankInfo->refreshInterval & 0xf) - { - case 0x0: /* refresh period is 15.625 usec */ - refreshPeriod = 15625; - break; - case 0x1: /* refresh period is 3.9 usec */ - refreshPeriod = 3900; - break; - case 0x2: /* refresh period is 7.8 usec */ - refreshPeriod = 7800; - break; - case 0x3: /* refresh period is 31.3 usec */ - refreshPeriod = 31300; - break; - case 0x4: /* refresh period is 62.5 usec */ - refreshPeriod = 62500; - break; - case 0x5: /* refresh period is 125 usec */ - refreshPeriod = 125000; - break; - default: /* refresh period undefined */ - mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); - return -1; - } - - /* Now the refreshPeriod is in register format value */ - refreshPeriod = (busClk * refreshPeriod) / 1000; - - DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", - refreshPeriod)); - - /* make sure the refresh value is only 14 bits */ - if(refreshPeriod > SDRAM_REFRESH_MAX) - { - refreshPeriod = SDRAM_REFRESH_MAX; - DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", - refreshPeriod)); - } - - /* Clear the refresh field */ - sdramConfig &= ~SDRAM_REFRESH_MASK; - - /* Set new value to refresh field */ - sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); - - /* registered DRAM ? */ - if ( pBankInfo->registeredAddrAndControlInputs ) - { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdramConfig |= SDRAM_REGISTERED; - DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) - } - - /* ECC and IERR support */ - sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ - sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ - - if ( pBankInfo->errorCheckType ) - { - sdramConfig |= SDRAM_ECC_EN; - sdramConfig |= SDRAM_IERR_REPORTE; - DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); - } - else - { - sdramConfig |= SDRAM_ECC_DIS; - sdramConfig |= SDRAM_IERR_IGNORE; - DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); - } - /* Set static default settings */ - sdramConfig |= SDRAM_CONFIG_DV; - - DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", - sdramConfig)); - - return sdramConfig; -} - -/******************************************************************************* -* sdramModeRegCalc - Calculate sdram mode register -* -* DESCRIPTION: Calculate sdram mode register optimized value based -* on the bank info parameters and the minCas. -* -* INPUT: -* minCas - minimum CAS supported. -* -* OUTPUT: -* None -* -* RETURN: -* sdram mode reg value. -* -*******************************************************************************/ -static MV_U32 sdramModeRegCalc(MV_U32 minCas) -{ - MV_U32 sdramMode; - - sdramMode = MV_REG_READ(SDRAM_MODE_REG); - - /* Clear CAS Latency field */ - sdramMode &= ~SDRAM_CL_MASK; - - DB(mvOsPrintf("DRAM CAS Latency ");) - - switch (minCas) - { - case DDR2_CL_3: - sdramMode |= SDRAM_DDR2_CL_3; - DB(mvOsPrintf("3.\n");) - break; - case DDR2_CL_4: - sdramMode |= SDRAM_DDR2_CL_4; - DB(mvOsPrintf("4.\n");) - break; - case DDR2_CL_5: - sdramMode |= SDRAM_DDR2_CL_5; - DB(mvOsPrintf("5.\n");) - break; - case DDR2_CL_6: - sdramMode |= SDRAM_DDR2_CL_6; - DB(mvOsPrintf("6.\n");) - break; - default: - mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); - return -1; - } - - DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); - - return sdramMode; -} -/******************************************************************************* -* sdramExtModeRegCalc - Calculate sdram Extended mode register -* -* DESCRIPTION: -* Return sdram Extended mode register value based -* on the bank info parameters and bank presence. -* -* INPUT: -* pBankInfo - sdram bank parameters -* busClk - DRAM frequency -* -* OUTPUT: -* None -* -* RETURN: -* sdram Extended mode reg value. -* -*******************************************************************************/ -static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -{ - MV_U32 populateBanks = 0; - int bankNum; - - /* Represent the populate banks in binary form */ - for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - if (0 != pBankInfo[bankNum].size) - { - populateBanks |= (1 << bankNum); - } - } - - switch(populateBanks) - { - case(BANK_PRESENT_CS0): - case(BANK_PRESENT_CS0_CS1): - return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; - - case(BANK_PRESENT_CS0_CS2): - case(BANK_PRESENT_CS0_CS1_CS2): - case(BANK_PRESENT_CS0_CS2_CS3): - case(BANK_PRESENT_CS0_CS2_CS3_CS4): - if (busClk >= MV_BOARD_SYSCLK_267MHZ) - return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; - else - return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; - - default: - mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); - return -1; - } - return 0; -} - -/******************************************************************************* -* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -* -* DESCRIPTION: Calculate sdram dunit control low register optimized value based -* on the bank info parameters and the minCas. -* -* INPUT: -* pBankInfo - sdram bank parameters -* minCas - minimum CAS supported. -* -* OUTPUT: -* None -* -* RETURN: -* sdram dunit control low reg value. -* -*******************************************************************************/ -static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -{ - MV_U32 dunitCtrlLow, cl; - MV_U32 sbOutR[4]={3,5,7,9} ; - MV_U32 sbOutU[4]={1,3,5,7} ; - - dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); - - DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); - - /* Clear StBurstOutDel field */ - dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; - - /* Clear StBurstInDel field */ - dunitCtrlLow &= ~SDRAM_SB_IN_MASK; - - /* Clear CtrlPos field */ - dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; - - /* Clear 2T field */ - dunitCtrlLow &= ~SDRAM_2T_MASK; - if (TTMode == MV_TRUE) - { - dunitCtrlLow |= SDRAM_2T_MODE; - } - - /* For proper sample of read data set the Dunit Control register's */ - /* stBurstInDel bits [27:24] */ - /* 200MHz - 267MHz None reg = CL + 1 */ - /* 200MHz - 267MHz reg = CL + 2 */ - /* > 267MHz None reg = CL + 2 */ - /* > 267MHz reg = CL + 3 */ - - /* For proper sample of read data set the Dunit Control register's */ - /* stBurstOutDel bits [23:20] */ - /********-********-********-********- - * CL=3 | CL=4 | CL=5 | CL=6 | - *********-********-********-********- - Not Reg. * 0001 | 0011 | 0101 | 0111 | - *********-********-********-********- - Registered * 0011 | 0101 | 0111 | 1001 | - *********-********-********-********/ - - /* Set Dunit Control low default value */ - dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; - - switch (minCas) - { - case DDR2_CL_3: cl = 3; break; - case DDR2_CL_4: cl = 4; break; - case DDR2_CL_5: cl = 5; break; - case DDR2_CL_6: cl = 6; break; - default: - mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); - return -1; - } - - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - { - dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; - } - else - { - dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; - } - - DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); - - if (busClk <= MV_BOARD_SYSCLK_267MHZ) - { - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - cl = cl + 2; - else - cl = cl + 1; - } - else - { - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - cl = cl + 3; - else - cl = cl + 2; - } - - DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); - dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; - - DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); - - return dunitCtrlLow; -} - -/******************************************************************************* -* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -* -* DESCRIPTION: Calculate sdram dunit control high register optimized value based -* on the bus clock. -* -* INPUT: -* busClk - DRAM frequency. -* -* OUTPUT: -* None -* -* RETURN: -* sdram dunit control high reg value. -* -*******************************************************************************/ -static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -{ - MV_U32 dunitCtrlHigh; - dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); - if(busClk > MV_BOARD_SYSCLK_300MHZ) - dunitCtrlHigh |= SDRAM__P2D_EN; - else - dunitCtrlHigh &= ~SDRAM__P2D_EN; - - if(busClk > MV_BOARD_SYSCLK_267MHZ) - dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); - - /* If ECC support we turn on D2P sample */ - dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ - if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) - dunitCtrlHigh |= SDRAM__D2P_EN; - - return dunitCtrlHigh; -} - -/******************************************************************************* -* sdramAddrCtrlRegCalc - Calculate sdram address control register -* -* DESCRIPTION: Calculate sdram address control register optimized value based -* on the bank info parameters and the minCas. -* -* INPUT: -* pBankInfo - sdram bank parameters -* -* OUTPUT: -* None -* -* RETURN: -* sdram address control reg value. -* -*******************************************************************************/ -static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -{ - MV_U32 addrCtrl = 0; - - if (pBankInfoDIMM1->size) - { - switch (pBankInfoDIMM1->sdramWidth) - { - case 4: /* memory is x4 */ - mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); - return -1; - break; - case 8: /* memory is x8 */ - addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); - DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); - break; - case 16: - addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); - DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); - break; - default: /* memory width unsupported */ - mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); - return -1; - } - } - - switch (pBankInfo->sdramWidth) - { - case 4: /* memory is x4 */ - mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); - return -1; - break; - case 8: /* memory is x8 */ - addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); - DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); - break; - case 16: - addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); - DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); - break; - default: /* memory width unsupported */ - mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); - return -1; - } - - /* Note that density is in MB units */ - switch (pBankInfo->deviceDensity) - { - case 256: /* 256 Mbit */ - DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); - addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); - break; - case 512: /* 512 Mbit */ - DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); - addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); - break; - case 1024: /* 1 Gbit */ - DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); - addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); - break; - case 2048: /* 2 Gbit */ - DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); - addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); - break; - default: - mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", - pBankInfo->deviceDensity); - return -1; - } - - if (pBankInfoDIMM1->size) - { - switch (pBankInfoDIMM1->deviceDensity) - { - case 256: /* 256 Mbit */ - DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); - addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); - break; - case 512: /* 512 Mbit */ - DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); - addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); - break; - case 1024: /* 1 Gbit */ - DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); - addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); - break; - case 2048: /* 2 Gbit */ - DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); - addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); - break; - default: - mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", - pBankInfoDIMM1->deviceDensity); - return -1; - } - } - /* SDRAM address control */ - DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); - - return addrCtrl; -} - -/******************************************************************************* -* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -* -* DESCRIPTION: -* This function calculates sdram timing control low register -* optimized value based on the bank info parameters and the minCas. -* -* INPUT: -* pBankInfo - sdram bank parameters -* minCas - minimum CAS supported. -* busClk - Bus clock -* -* OUTPUT: -* None -* -* RETURN: -* sdram timing control low reg value. -* -*******************************************************************************/ -static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -{ - MV_U32 tRp = 0; - MV_U32 tRrd = 0; - MV_U32 tRcd = 0; - MV_U32 tRas = 0; - MV_U32 tWr = 0; - MV_U32 tWtr = 0; - MV_U32 tRtp = 0; - MV_U32 timeCtrlLow = 0; - - MV_U32 bankNum; - - busClk = busClk / 1000000; /* In MHz */ - - /* Scan all DRAM banks to find maximum timing values */ - for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); - tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); - tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); - tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); - } - - /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ - /* by shifting the data two bits right. */ - tRp = tRp >> 2; /* For example 0x50 -> 20ns */ - tRrd = tRrd >> 2; - tRcd = tRcd >> 2; - - /* Extract clock cycles from time parameter. We need to round up */ - tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); - DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); - tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); - /* JEDEC min reqeirments tRrd = 2 */ - if (tRrd < 2) - tRrd = 2; - DB(mvOsPrintf("tRrd = %d ", tRrd)); - tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); - DB(mvOsPrintf("tRcd = %d ", tRcd)); - tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); - DB(mvOsPrintf("tRas = %d ", tRas)); - - /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ - /* Scan all DRAM banks to find maximum timing values */ - for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); - tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); - tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); - } - - /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ - /* part by shifting the data two bits right. */ - tWr = tWr >> 2; /* For example 0x50 -> 20ns */ - tWtr = tWtr >> 2; - tRtp = tRtp >> 2; - /* Extract clock cycles from time parameter. We need to round up */ - tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); - DB(mvOsPrintf("tWr = %d ", tWr)); - tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); - /* JEDEC min reqeirments tWtr = 2 */ - if (tWtr < 2) - tWtr = 2; - DB(mvOsPrintf("tWtr = %d ", tWtr)); - tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); - /* JEDEC min reqeirments tRtp = 2 */ - if (tRtp < 2) - tRtp = 2; - DB(mvOsPrintf("tRtp = %d ", tRtp)); - - /* Note: value of 0 in register means one cycle, 1 means two and so on */ - timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | - ((tRrd - 1) << SDRAM_TRRD_OFFS) | - ((tRcd - 1) << SDRAM_TRCD_OFFS) | - (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| - ((tWr - 1) << SDRAM_TWR_OFFS) | - ((tWtr - 1) << SDRAM_TWTR_OFFS) | - ((tRtp - 1) << SDRAM_TRTP_OFFS)); - - /* Check extended tRas bit */ - if ((tRas - 1) & BIT4) - timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); - - return timeCtrlLow; -} - -/******************************************************************************* -* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -* -* DESCRIPTION: -* This function calculates sdram timing control high register -* optimized value based on the bank info parameters and the bus clock. -* -* INPUT: -* pBankInfo - sdram bank parameters -* busClk - Bus clock -* -* OUTPUT: -* None -* -* RETURN: -* sdram timing control high reg value. -* -*******************************************************************************/ -static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -{ - MV_U32 tRfc; - MV_U32 timingHigh; - MV_U32 timeNs = 0; - MV_U32 bankNum; - - busClk = busClk / 1000000; /* In MHz */ - - /* Set DDR timing high register static configuration bits */ - timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); - - /* Set DDR timing high register default value */ - timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; - - /* Clear tRfc field */ - timingHigh &= ~SDRAM_TRFC_MASK; - - /* Scan all DRAM banks to find maximum timing values */ - for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); - DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", - pBankInfo[bankNum].minRefreshToActiveCmd)); - } - if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) - { - timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; - } - - tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); - /* Note: value of 0 in register means one cycle, 1 means two and so on */ - DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); - timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); - DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); - - /* SDRAM timing high */ - DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); - - return timingHigh; -} -/******************************************************************************* -* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -* -* DESCRIPTION: -* This function config DDR2 On Die Termination (ODT) registers. -* -* INPUT: -* pBankInfo - bank info parameters. -* -* OUTPUT: -* None -* -* RETURN: -* None -*******************************************************************************/ -static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -{ - MV_U32 populateBanks = 0; - MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; - int bankNum; - - /* Represent the populate banks in binary form */ - for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - if (0 != pBankInfo[bankNum].size) - { - populateBanks |= (1 << bankNum); - } - } - - switch(populateBanks) - { - case(BANK_PRESENT_CS0): - case(BANK_PRESENT_CS0_CS1): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; - break; - case(BANK_PRESENT_CS0_CS2): - case(BANK_PRESENT_CS0_CS1_CS2): - case(BANK_PRESENT_CS0_CS2_CS3): - case(BANK_PRESENT_CS0_CS2_CS3_CS4): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; - break; - default: - DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); - return; - } - /* DDR2 SDRAM ODT ctrl low */ - DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); - MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); - - /* DDR2 SDRAM ODT ctrl high */ - DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); - MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); - - /* DDR2 DUNIT ODT ctrl */ - if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || - (mvCtrlModelGet() == MV_76100_DEV_ID) || - (mvCtrlModelGet() == MV_78100_DEV_ID) || - (mvCtrlModelGet() == MV_78200_DEV_ID) ) - dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ - - DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); - MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); - return; -} -/******************************************************************************* -* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -* -* DESCRIPTION: -* This function config DDR2 DRAM Timing low registers. -* -* INPUT: -* minCas - minimum CAS supported. -* -* OUTPUT: -* None -* -* RETURN: -* DDR2 sdram timing low reg value. -*******************************************************************************/ -static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -{ - MV_U8 cl = -1; - MV_U32 ddr2TimeLoReg; - - /* read and clear the feilds we are going to set */ - ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); - ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | - SD2TLR_TODT_OFF_RD_MASK | - SD2TLR_TODT_ON_CTRL_RD_MASK | - SD2TLR_TODT_OFF_CTRL_RD_MASK); - - if( minCas == DDR2_CL_3 ) - { - cl = 3; - } - else if( minCas == DDR2_CL_4 ) - { - cl = 4; - } - else if( minCas == DDR2_CL_5 ) - { - cl = 5; - } - else if( minCas == DDR2_CL_6 ) - { - cl = 6; - } - else - { - DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", - minCas)); - cl = 4; - } - - ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); - ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); - ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); - ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); - - /* DDR2 SDRAM timing low */ - DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); - - return ddr2TimeLoReg; -} - -/******************************************************************************* -* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -* -* DESCRIPTION: -* This function config DDR2 DRAM Timing high registers. -* -* INPUT: -* minCas - minimum CAS supported. -* -* OUTPUT: -* None -* -* RETURN: -* DDR2 sdram timing high reg value. -*******************************************************************************/ -static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -{ - MV_U8 cl = -1; - MV_U32 ddr2TimeHiReg; - - /* read and clear the feilds we are going to set */ - ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); - ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | - SD2THR_TODT_OFF_WR_MASK | - SD2THR_TODT_ON_CTRL_WR_MASK | - SD2THR_TODT_OFF_CTRL_WR_MASK); - - if( minCas == DDR2_CL_3 ) - { - cl = 3; - } - else if( minCas == DDR2_CL_4 ) - { - cl = 4; - } - else if( minCas == DDR2_CL_5 ) - { - cl = 5; - } - else if( minCas == DDR2_CL_6 ) - { - cl = 6; - } - else - { - mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", - minCas); - cl = 4; - } - - ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); - ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); - ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); - ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); - - /* DDR2 SDRAM timin high */ - DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); - - return ddr2TimeHiReg; -} -#endif - -/******************************************************************************* -* mvDramIfCalGet - Get CAS Latency -* -* DESCRIPTION: -* This function get the CAS Latency. -* -* INPUT: -* None -* -* OUTPUT: -* None -* -* RETURN: -* CAS latency times 10 (to avoid using floating point). -* -*******************************************************************************/ -MV_U32 mvDramIfCalGet(void) -{ - MV_U32 sdramCasLat, casLatMask; - - casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); - - switch (casLatMask) - { - case SDRAM_DDR2_CL_3: - sdramCasLat = 30; - break; - case SDRAM_DDR2_CL_4: - sdramCasLat = 40; - break; - case SDRAM_DDR2_CL_5: - sdramCasLat = 50; - break; - case SDRAM_DDR2_CL_6: - sdramCasLat = 60; - break; - default: - mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); - return -1; - } - - return sdramCasLat; -} - - -/******************************************************************************* -* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -* -* DESCRIPTION: -* add support in power management. -* -* -* INPUT: -* None -* -* OUTPUT: -* None -* -* RETURN: -* None -* -*******************************************************************************/ - -MV_VOID mvDramIfSelfRefreshSet() -{ - MV_U32 operReg; - - operReg = MV_REG_READ(SDRAM_OPERATION_REG); - MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); - /* Read until register is reset to 0 */ - while(MV_REG_READ(SDRAM_OPERATION_REG)); -} -/******************************************************************************* -* mvDramIfDimGetSPDversion - return DIMM SPD version. -* -* DESCRIPTION: -* This function prints the DRAM controller information. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -{ - MV_DIMM_INFO dimmInfo; - if (bankNum >= MV_DRAM_MAX_CS ) - { - DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); - return ; - } - memset(&dimmInfo,0,sizeof(dimmInfo)); - if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) - { - DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); - return ; - } - *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; - *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -} -/******************************************************************************* -* mvDramIfShow - Show DRAM controller information. -* -* DESCRIPTION: -* This function prints the DRAM controller information. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -void mvDramIfShow(void) -{ - int i, sdramCasLat, sdramCsSize; - MV_U32 Major=0, Minor=0; - - mvOsOutput("DRAM Controller info:\n"); - - mvOsOutput("Total DRAM "); - mvSizePrint(mvDramIfSizeGet()); - mvOsOutput("\n"); - - for(i = 0; i < MV_DRAM_MAX_CS; i++) - { - sdramCsSize = mvDramIfBankSizeGet(i); - if (sdramCsSize) - { - if (0 == (i & 1)) - { - mvDramIfDimGetSPDversion(&Major, &Minor,i); - mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); - } - mvOsOutput("\tDRAM CS[%d] ", i); - mvSizePrint(sdramCsSize); - mvOsOutput("\n"); - } - } - sdramCasLat = mvDramIfCalGet(); - - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) - { - mvOsOutput("ECC enabled, "); - } - else - { - mvOsOutput("ECC Disabled, "); - } - - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) - { - mvOsOutput("Registered DIMM\n"); - } - else - { - mvOsOutput("Non registered DIMM\n"); - } - - mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -} -/******************************************************************************* -* mvDramIfGetFirstCS - find the DRAM bank on the lower address -* -* -* DESCRIPTION: -* This function return the fisrt CS on address 0 -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* SDRAM_CS0 or SDRAM_CS2 -* -*******************************************************************************/ -MV_U32 mvDramIfGetFirstCS(void) -{ - MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; - - if (DRAM_CS_Order[0] == N_A) - { - mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -#ifdef MV_INCLUDE_SDRAM_CS2 - mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -#endif - -#ifdef MV_INCLUDE_SDRAM_CS2 - if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) - { - DRAM_CS_Order[0] = SDRAM_CS2; - DRAM_CS_Order[1] = SDRAM_CS3; - DRAM_CS_Order[2] = SDRAM_CS0; - DRAM_CS_Order[3] = SDRAM_CS1; - - return SDRAM_CS2; - } -#endif - DRAM_CS_Order[0] = SDRAM_CS0; - DRAM_CS_Order[1] = SDRAM_CS1; -#ifdef MV_INCLUDE_SDRAM_CS2 - DRAM_CS_Order[2] = SDRAM_CS2; - DRAM_CS_Order[3] = SDRAM_CS3; -#endif - return SDRAM_CS0; - } - return DRAM_CS_Order[0]; -} -/******************************************************************************* -* mvDramIfGetCSorder - -* -* -* DESCRIPTION: -* This function return the fisrt CS on address 0 -* -* INPUT: -* CS number. -* -* OUTPUT: -* CS order. -* -* RETURN: -* SDRAM_CS0 or SDRAM_CS2 -* -* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -*******************************************************************************/ -MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -{ - return DRAM_CS_Order[csOrder]; -} - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h deleted file mode 100644 index 23f2e540c0..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h +++ /dev/null @@ -1,172 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -#ifndef __INCmvDramIfh -#define __INCmvDramIfh - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* includes */ -#include "ddr2/mvDramIfRegs.h" -#include "ddr2/mvDramIfConfig.h" -#include "ctrlEnv/mvCtrlEnvLib.h" - -/* defines */ -/* DRAM Timing parameters */ -#define SDRAM_TWR 15 /* ns tWr */ -#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ - -#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -#define ECC_DISABLE 1 /* Force ECC to Disable */ -#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -/* typedefs */ - -/* enumeration for memory types */ -typedef enum _mvMemoryType -{ - MEM_TYPE_SDRAM, - MEM_TYPE_DDR1, - MEM_TYPE_DDR2 -}MV_MEMORY_TYPE; - -/* enumeration for DDR2 supported CAS Latencies */ -typedef enum _mvDimmDdr2Cas -{ - DDR2_CL_3 = 0x08, - DDR2_CL_4 = 0x10, - DDR2_CL_5 = 0x20, - DDR2_CL_6 = 0x40, - DDR2_CL_FAULT -} MV_DIMM_DDR2_CAS; - - -typedef struct _mvDramBankInfo -{ - MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ - - /* DIMM dimensions */ - MV_U32 numOfRowAddr; - MV_U32 numOfColAddr; - MV_U32 dataWidth; - MV_U32 errorCheckType; /* ECC , PARITY..*/ - MV_U32 sdramWidth; /* 4,8,16 or 32 */ - MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ - MV_U32 burstLengthSupported; - MV_U32 numOfBanksOnEachDevice; - MV_U32 suportedCasLatencies; - MV_U32 refreshInterval; - - /* DIMM timing parameters */ - MV_U32 minCycleTimeAtMaxCasLatPs; - MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; - MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; - MV_U32 minRowPrechargeTime; - MV_U32 minRowActiveToRowActive; - MV_U32 minRasToCasDelay; - MV_U32 minRasPulseWidth; - MV_U32 minWriteRecoveryTime; /* DDR2 only */ - MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ - MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ - MV_U32 minRefreshToActiveCmd; /* DDR2 only */ - - /* Parameters calculated from the extracted DIMM information */ - MV_U32 size; - MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ - MV_U32 numberOfDevices; - - /* DIMM attributes (MV_TRUE for yes) */ - MV_BOOL registeredAddrAndControlInputs; - MV_BOOL registeredDQMBinputs; - -}MV_DRAM_BANK_INFO; - -#include "ddr2/spd/mvSpd.h" - -/* mvDramIf.h API list */ -MV_VOID mvDramIfBasicAsmInit(MV_VOID); -MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -MV_VOID _mvDramIfConfig(int entryNum); - -MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -MV_U32 mvDramIfSizeGet(MV_VOID); -MV_U32 mvDramIfCalGet(void); -MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -MV_VOID mvDramIfSelfRefreshSet(void); -void mvDramIfShow(void); -MV_U32 mvDramIfGetFirstCS(void); -MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -MV_U32 mvDramCsSizeGet(MV_U32 csNum); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S deleted file mode 100644 index 76723816d5..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S +++ /dev/null @@ -1,986 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#define _ASMLANGUAGE -#define MV_ASMLANGUAGE -#include "mvSysHwConfig.h" -#include "mvOsAsm.h" -#include "boardEnv/mvBoardEnvSpec.h" -#include "ctrlEnv/sys/mvCpuIfRegs.h" -#include "mvDramIfConfig.h" -#include "mvDramIfRegs.h" -#include "pex/mvPexRegs.h" -#include "ctrlEnv/mvCtrlEnvSpec.h" -#include "ctrlEnv/mvCtrlEnvAsm.h" -#include "mvCommon.h" - -/* defines */ - -#if defined(MV_STATIC_DRAM_ON_BOARD) -.globl dramBoot1 -dramBoot1: - .word 0 - -/****************************************************************************** -* -* -* -* -*******************************************************************************/ -#if defined(DB_MV78XX0) || defined(DB_MV88F632X) -/* DDR2 boards 512MB 333MHz */ -#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ -#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ -#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ -#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ - -#elif defined(RD_MV78XX0_AMC) -/* On board DDR2 512MB 400MHz CL5 */ -#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ -#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ -#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ - -#elif defined(RD_MV78XX0_H3C) -/* DDR2 boards 512MB 333MHz */ -#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ -#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ -#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ - -#elif defined(RD_MV78XX0_PCAC) -/* DDR2 boards 256MB 200MHz */ -#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ -#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ -#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ -#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ - -#else -/* DDR2 MV88F6281 boards 256MB 400MHz */ -#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ -#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ -#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ -#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ -#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ -#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ -#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -#endif /* MV78XX0 */ - - .globl _mvDramIfStaticInit -_mvDramIfStaticInit: - - mov r11, LR /* Save link register */ - mov r10, r2 - -#ifdef MV78XX0 - MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) - orr r6, r6, #BIT4 /* Enable 2T mode */ - bic r6, r6, #BIT6 /* clear ctrlPos */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -#endif - - /*DDR SDRAM Initialization Control */ - ldr r6, =DSICR_INIT_EN - MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) - and r6, r6, #DSICR_INIT_EN - cmp r6, #0 - bne 2b - - /* If we boot from NAND jump to DRAM address */ - mov r5, #1 - ldr r6, =dramBoot1 - str r5, [r6] /* We started executing from DRAM */ - - ldr r6, dramBoot1 - cmp r6, #0 - bne 1f - - /* set all dram windows to 0 */ - mov r6, #0 - MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) - MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) - MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) - MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) - ldr r6, = STATIC_SDRAM0_BANK0_SIZE - MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) - - - /* set all dram configuration in temp registers */ - ldr r6, = STATIC_SDRAM0_BANK0_SIZE - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) - ldr r6, = STATIC_SDRAM_CONFIG - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) - ldr r6, = STATIC_SDRAM_MODE - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) - ldr r6, = STATIC_DUNIT_CTRL_LOW - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) - ldr r6, = STATIC_SDRAM_ADDR_CTRL - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) - ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) - ldr r6, = STATIC_SDRAM_TIME_CTRL_HI - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) - ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) - ldr r6, = STATIC_SDRAM_ODT_CTRL_HI - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) - ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) - ldr r6, = STATIC_SDRAM_EXT_MODE - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) - ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) - ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) -#ifndef MV_NAND_BOOT - ldr r6, = STATIC_DUNIT_CTRL_HI - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) -#endif - - ldr sp,=0 - bl _mvDramIfConfig - ldr r0, =0 -#ifdef MV78XX0 - bl _mvDramIfEccMemInit -#endif -1: - mov r2, r10 - mov PC, r11 /* r11 is saved link register */ - -#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ - -.globl dramBoot1 -dramBoot1: - .word 0 - -/******************************************************************************* -* mvDramIfBasicInit - Basic initialization of DRAM interface -* -* DESCRIPTION: -* The function will initialize the DRAM for basic usage. The function -* will use the TWSI assembly API to extract DIMM parameters according -* to which DRAM interface will be initialized. -* The function referes to the following DRAM parameters: -* 1) DIMM is registered or not. -* 2) DIMM width detection. -* 3) DIMM density. -* -* INPUT: -* r3 - required size for initial DRAM. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -* Note: -* r4 holds I2C EEPROM address -* r5 holds SDRAM register base address -* r7 holds returned values -* r8 holds SDRAM various configuration registers value. -* r11 holds return function address. -*******************************************************************************/ -/* Setting the offsets of the I2C registers */ -#define DIMM_TYPE_OFFSET 2 -#define NUM_OF_ROWS_OFFSET 3 -#define NUM_OF_COLS_OFFSET 4 -#define NUM_OF_RANKS 5 -#define DIMM_CONFIG_TYPE 11 -#define SDRAM_WIDTH_OFFSET 13 -#define NUM_OF_BANKS_OFFSET 17 -#define SUPPORTED_CL_OFFSET 18 -#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ -#define SDRAM_MODULES_ATTR_OFFSET 21 -#define RANK_SIZE_OFFSET 31 - -#define DRAM_DEV_DENSITY_128M 128 -#define DRAM_DEV_DENSITY_256M 256 -#define DRAM_DEV_DENSITY_512M 512 -#define DRAM_DEV_DENSITY_1G 1024 -#define DRAM_DEV_DENSITY_2G 2048 - -#define DRAM_RANK_DENSITY_128M 0x20 -#define DRAM_RANK_DENSITY_256M 0x40 -#define DRAM_RANK_DENSITY_512M 0x80 -#define DRAM_RANK_DENSITY_1G 0x1 -#define DRAM_RANK_DENSITY_2G 0x2 - - .globl _mvDramIfBasicInit - .extern _i2cInit -_mvDramIfBasicInit: - - mov r11, LR /* Save link register */ - - /* Set Dunit high control register */ - MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) - orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ - orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ -#ifdef MV78XX0 - orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ - orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ - orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ -#endif - MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) - -#ifdef MV78XX0 - MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) - orr r6, r6, #BIT4 /* Enable 2T mode */ - bic r6, r6, #BIT6 /* clear ctrlPos */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -#endif - - /*DDR SDRAM Initialization Control */ - ldr r6, =DSICR_INIT_EN - MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) - and r6, r6, #DSICR_INIT_EN - cmp r6, #0 - bne 2b - - mov r5, #1 - ldr r8, =dramBoot1 - str r5, [r8] /* We started executing from DRAM */ - - /* If we boot from NAND jump to DRAM address */ - ldr r8, dramBoot1 - cmp r8, #0 - movne pc, r11 - - bl _i2cInit /* Initialize TWSI master */ - - /* Check if we have more then 1 dimm */ - ldr r6, =0 - MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) -#ifdef MV78XX0 - bl _is_Second_Dimm_Exist - beq single_dimm - ldr r6, =1 - MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) -single_dimm: - bl _i2cInit /* Initialize TWSI master */ -#endif - - /* Get default SDRAM Config values */ - MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) - - /* Get registered/non registered info from DIMM */ - bl _is_Registered - beq nonRegistered - -setRegistered: - orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ -nonRegistered: -#ifdef MV78XX0 - /* Get ECC/non ECC info from DIMM */ - bl _is_Ecc - beq setConfigReg - -setEcc: - orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ -#endif -setConfigReg: - MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) - - /* Set maximum CL supported by DIMM */ - bl _get_CAL - - /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ - clz r6, r7 - rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ - -casDdr2: - ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ - ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ - ldr r8, =0x32 /* Assuming MAX CL = 3 */ - cmp r6, #3 /* If CL = 3 break */ - beq casDdr2Cont - - ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ - ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ - ldr r8, =0x42 /* Assuming MAX CL = 4 */ - cmp r6, #4 /* If CL = 4 break */ - beq casDdr2Cont - - ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ - ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ - ldr r8, =0x52 /* Assuming MAX CL = 5 */ - cmp r6, #5 /* If CL = 5 break */ - beq casDdr2Cont - - ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ - ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ - ldr r8, =0x62 /* Assuming MAX CL = 6 */ - cmp r6, #6 /* If CL = 5 break */ - beq casDdr2Cont - - /* This is an error. return */ - b exit_ddrAutoConfig /* This is an error !! */ -casDdr2Cont: - - /* Get default SDRAM Mode values */ - MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) - bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ - orr r6, r6, r8 - MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) - - /* Set Dunit control register according to max CL detected */ - MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) - tst r6, #SDRAM_REGISTERED - beq setDunitReg - mov r7, r3 - -setDunitReg: -#ifdef MV78XX0 - /* Set SDRAM Extended Mode register for double DIMM */ - /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ - - MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) - ldr r5, =MSAR_SYSCLCK_MASK - and r4, r4, r5 - ldr r5, =MSAR_SYSCLCK_333 - cmp r4, r5 - ble Clock333 - add r7, r7, #0x10 -Clock333: -#endif - - MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) - bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ - orr r6, r6, #BIT4 /* Enable 2T mode */ - bic r6, r6, #BIT6 /* clear ctrlPos */ - orr r6, r6, r7, LSL #20 - MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) - - /* Set Dunit high control register */ - MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) - orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ - orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ -#ifdef MV78XX0 - orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ - orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ - orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ -#endif - MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) - - /* DIMM density configuration*/ - /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ -Density: - /* Get bank 0 and 1 density */ - ldr r6, =0 - bl _getDensity - - mov r8, r7 - mov r8, r8, LSR #20 /* Move density 20 bits to the right */ - /* For example 0x10000000 --> 0x1000 */ - - mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) - cmp r8, #DRAM_DEV_DENSITY_256M - beq get_bank_2_density - - mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) - cmp r8, #DRAM_DEV_DENSITY_512M - beq get_bank_2_density - - mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) - cmp r8, #DRAM_DEV_DENSITY_1G - beq get_bank_2_density - - mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) - cmp r8, #DRAM_DEV_DENSITY_2G - beq get_bank_2_density - - /* This is an error. return */ - b exit_ddrAutoConfig - -get_bank_2_density: - /* Check for second dimm */ - MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) - cmp r6, #1 - bne get_width - - /* Get bank 2 and 3 density */ - ldr r6, =2 - bl _getDensity - - mov r8, r7 - mov r8, r8, LSR #20 /* Move density 20 bits to the right */ - /* For example 0x10000000 --> 0x1000 */ - - orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) - cmp r8, #DRAM_DEV_DENSITY_256M - beq get_width - - and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) - orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) - cmp r8, #DRAM_DEV_DENSITY_512M - beq get_width - - and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) - orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) - cmp r8, #DRAM_DEV_DENSITY_1G - beq get_width - - and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) - orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) - cmp r8, #DRAM_DEV_DENSITY_2G - beq get_width - - /* This is an error. return */ - b exit_ddrAutoConfig - - /* Get SDRAM width */ -get_width: - /* Get bank 0 and 1 width */ - ldr r6, =0 - bl _get_width - - cmp r7, #8 /* x8 devices */ - beq get_bank_2_width - - orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ - cmp r7, #16 - beq get_bank_2_width - - /* This is an error. return */ - b exit_ddrAutoConfig - -get_bank_2_width: - /* Check for second dimm */ - MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) - cmp r6, #1 - bne densCont - - /* Get bank 2 and 3 width */ - ldr r6, =2 - bl _get_width - - cmp r7, #8 /* x8 devices */ - beq densCont - - orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ - cmp r7, #16 - beq densCont - - /* This is an error. return */ - b exit_ddrAutoConfig - -densCont: - MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) - - /* Set SDRAM timing control low register */ - ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT - /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) - - /* Set SDRAM timing control high register */ - ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT - - MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) - ldr r5, =MSAR_SYSCLCK_MASK - and r4, r4, r5 - ldr r5, =MSAR_SYSCLCK_333 - cmp r4, r5 - blt timingHighClock333 - orr r6, r6, #BIT9 - -timingHighClock333: - /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) - - /* Check for second dimm */ - MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) - cmp r6, #1 - bne single_dimm_odt - - /* Set SDRAM ODT control low register for double DIMM*/ - ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) - - /* Set DUNIT ODT control register for double DIMM */ - ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) - -#ifdef MV78XX0 - /* Set SDRAM Extended Mode register for double DIMM */ - /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ - - MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) - ldr r5, =MSAR_SYSCLCK_MASK - and r4, r4, r5 - ldr r5, =MSAR_SYSCLCK_267 - cmp r4, r5 - beq slow_dram_clock_rtt - ldr r5, =MSAR_SYSCLCK_300 - cmp r4, r5 - beq slow_dram_clock_rtt - ldr r5, =MSAR_SYSCLCK_333 - cmp r4, r5 - beq fast_dram_clock_rtt - ldr r5, =MSAR_SYSCLCK_400 - cmp r4, r5 - beq fast_dram_clock_rtt - - b slow_dram_clock_rtt - -fast_dram_clock_rtt: - ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) - b odt_config_end -#endif -slow_dram_clock_rtt: - ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) - b odt_config_end - -single_dimm_odt: - /* Set SDRAM ODT control low register */ - ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) - - /* Set DUNIT ODT control register */ - ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) - - /* Set SDRAM Extended Mode register */ - ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) - -odt_config_end: - /* SDRAM ODT control high register is left as default */ - MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) - - /*Read CL and set the DDR2 registers accordingly */ - MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) - and r6, r6, #SDRAM_CL_MASK - mov r4, r6 - orr r4, r4, r6, LSL #4 - orr r4, r4, r6, LSL #8 - orr r4, r4, r6, LSL #12 - mov r5, #0x30000 - add r4, r4, r5 - sub r4, r4, #0x30 - /* Set SDRAM Ddr2 Timing Low register */ - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) - - /* Set SDRAM Ddr2 Timing High register */ - mov r4, r4, LSR #4 - MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) - -timeParamDone: - /* Close all windows */ - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) - and r6, r6,#~SCSR_SIZE_MASK - and r6, r6,#~1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) - and r6, r6,#~SCSR_SIZE_MASK - and r6, r6,#~1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) - and r6, r6,#~SCSR_SIZE_MASK - and r6, r6,#~1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) - and r6, r6,#~SCSR_SIZE_MASK - and r6, r6,#~1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) - - /* Set sdram bank 0 size and enable it */ - ldr r6, =0 - bl _mvDramIfGetDimmSizeFromSpd -#ifdef MV78XX0 - /* Check DRAM width */ - MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) - ldr r5, =SDRAM_DWIDTH_MASK - and r4, r4, r5 - ldr r5, =SDRAM_DWIDTH_64BIT - cmp r4, r5 - beq dram_64bit_width - /* Utilize only 32bit width */ - mov r8, r8, LSR #1 -#else - /* Utilize only 16bit width */ - mov r8, r8, LSR #2 -#endif -dram_64bit_width: - /* Update first dimm size return value R8 */ - MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) - ldr r6, =~SCSR_SIZE_MASK - and r5, r5, r6 - orr r5, r5, r8 - MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) - - /* Clear bank 2 size */ - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) - and r6, r6,#~SCSR_SIZE_MASK - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) - - /* Check for second dimm */ - MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) - cmp r6, #1 - bne defualt_order - - /* Set sdram bank 2 size */ - ldr r6, =2 - bl _mvDramIfGetDimmSizeFromSpd -#ifdef MV78XX0 - /* Check DRAM width */ - MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) - ldr r5, =SDRAM_DWIDTH_MASK - and r4, r4, r5 - ldr r5, =SDRAM_DWIDTH_64BIT - cmp r4, r5 - beq dram_64bit_width2 - /* Utilize only 32bit width */ - mov r8, r8, LSR #1 -#else - /* Utilize only 16bit width */ - mov r8, r8, LSR #2 -#endif -dram_64bit_width2: - /* Update first dimm size return value R8 */ - MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) - ldr r6, =~SCSR_SIZE_MASK - and r5, r5, r6 - orr r5, r5, r8 - MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) - - /* Close windows 1 and 3 */ - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) - and r6, r6,#~1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) - and r6, r6,#~1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) - - /* Check dimm size for setting dram bank order */ - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) - MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) - and r6, r6,#SCSR_SIZE_MASK - and r4, r4,#SCSR_SIZE_MASK - cmp r6, r4 - bge defualt_order - - /* Bank 2 is biger then bank 0 */ - ldr r6,=0 - MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) - - /* Open win 2 */ - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) - orr r6, r6,#1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) - - ldr sp,=0 - bl _mvDramIfConfig -#ifdef MV78XX0 - /* Init ECC on CS 2 */ - ldr r0, =2 - bl _mvDramIfEccMemInit -#endif - mov PC, r11 /* r11 is saved link register */ - -defualt_order: - - /* Open win 0 */ - MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) - orr r6, r6,#1 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) - - ldr sp,=0 - bl _mvDramIfConfig -#ifdef MV78XX0 - /* Init ECC on CS 0 */ - ldr r0, =0 - bl _mvDramIfEccMemInit -#endif -exit_ddrAutoConfig: - mov PC, r11 /* r11 is saved link register */ - - -/***************************************************************************************/ -/* r4 holds I2C EEPROM address - * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value - * r8 holds SDRAM various configuration registers value. - * r13 holds Link register - */ -/**************************/ -_getDensity: - mov r13, LR /* Save link register */ - - /* Read SPD rank size from DIMM0 */ - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - - cmp r6, #0 - beq 1f - - /* Read SPD rank size from DIMM1 */ - mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ - -1: - mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ - bl _i2cRead - mov r8, r7 /* r8 save number of rows */ - - mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ - bl _i2cRead - add r8, r8, r7 /* r8 = number of rows + number of col */ - - mov r7, #0x1 - mov r8, r7, LSL r8 /* r8 = (1 << r8) */ - - mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ - bl _i2cRead - mul r8, r7, r8 - - mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ - bl _i2cRead - mul r7, r8, r7 - - mov PC, r13 - -/**************************/ -_get_width: - mov r13, LR /* Save link register */ - - /* Read SPD rank size from DIMM0 */ - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - - cmp r6, #0 - beq 1f - - /* Read SPD rank size from DIMM1 */ - mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ - -1: - /* Get SDRAM width (SPD offset 13) */ - mov r7, #SDRAM_WIDTH_OFFSET - bl _i2cRead /* result in r7 */ - - mov PC, r13 - -/**************************/ -_get_CAL: - mov r13, LR /* Save link register */ - - /* Set maximum CL supported by DIMM */ - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ - bl _i2cRead - - mov PC, r13 - -/**************************/ -/* R8 - sdram configuration register. - * Return value in flag if no-registered then Z-flag is set - */ -_is_Registered: - mov r13, LR /* Save link register */ -#if defined(MV645xx) - /* Get registered/non registered info from DIMM */ - tst r8, #SDRAM_DTYPE_DDR2 - bne regDdr2 - -regDdr1: - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #SDRAM_MODULES_ATTR_OFFSET - bl _i2cRead /* result in r7 */ - - tst r7, #0x2 - b exit -#endif -regDdr2: - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #DIMM_TYPE_INFO_OFFSET - bl _i2cRead /* result in r7 */ - - tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ - /* or Mini-RDIMM (0x10) */ -exit: - mov PC, r13 - - -/**************************/ -/* Return value in flag if no-Ecc then Z-flag is set */ -_is_Ecc: - mov r13, LR /* Save link register */ - - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #DIMM_CONFIG_TYPE - bl _i2cRead /* result in r7 */ - - tst r7, #0x2 /* bit 1 -> Data ECC */ - mov PC, r13 - -/**************************/ -/* Return value in flag if no second DIMM then Z-flag is set */ -_is_Second_Dimm_Exist: - mov r13, LR /* Save link register */ - - mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ - mov r7, #DIMM_TYPE_OFFSET - bl _i2cRead /* result in r7 */ - - tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ - mov PC, r13 - -/******************************************************************************* -* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size -* -* DESCRIPTION: -* The function will read the bank 0 dram size(SPD version 1.0 and above ) -* -* INPUT: -* r6 - dram bank number. -* -* OUTPUT: -* none -*/ -_mvDramIfGetDimmSizeFromSpd: - - mov r13, LR /* Save link register */ - - /* Read SPD rank size from DIMM0 */ - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - - cmp r6, #0 - beq 1f - - /* Read SPD rank size from DIMM1 */ - mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ - -1: - mov r7, #RANK_SIZE_OFFSET /* offset 31 */ - bl _i2cRead - -pass_read: - ldr r8, =(0x7 << SCSR_SIZE_OFFS) - cmp r7, #DRAM_RANK_DENSITY_128M - beq endDimmSize - - ldr r8, =(0xf << SCSR_SIZE_OFFS) - cmp r7, #DRAM_RANK_DENSITY_256M - beq endDimmSize - - ldr r8, =(0x1f << SCSR_SIZE_OFFS) - cmp r7, #DRAM_RANK_DENSITY_512M - beq endDimmSize - - ldr r8, =(0x3f << SCSR_SIZE_OFFS) - cmp r7, #DRAM_RANK_DENSITY_1G - beq endDimmSize - - ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ -endDimmSize: - mov PC, r13 -#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S deleted file mode 100644 index 88527e58cc..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S +++ /dev/null @@ -1,528 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -/******************************************************************************* -* mvDramIfBasicAsm.s -* -* DESCRIPTION: -* Memory full detection and best timing configuration is done in -* C code. C runtime environment requires a stack. This module API -* initialize DRAM interface chip select 0 for basic functionality for -* the use of stack. -* The module API assumes DRAM information is stored in I2C EEPROM reside -* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM -* internal data structure is assumed to be orgenzied in common DRAM -* vendor SPD structure. -* NOTE: DFCDL values are assumed to be already initialized prior to -* this module API activity. -* -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -/* includes */ -#define _ASMLANGUAGE -#define MV_ASMLANGUAGE -#include "mvOsAsm.h" -#include "mvSysHwConfig.h" -#include "mvDramIfRegs.h" -#include "mvDramIfConfig.h" -#include "ctrlEnv/sys/mvCpuIfRegs.h" -#include "pex/mvPexRegs.h" -#include "ctrlEnv/mvCtrlEnvSpec.h" -#include "mvCommon.h" - -/* defines */ - -/* locals */ -.data -.globl _mvDramIfConfig -.text -.globl _mvDramIfMemInit - -/******************************************************************************* -* _mvDramIfConfig - Basic DRAM interface initialization. -* -* DESCRIPTION: -* The function will initialize the following DRAM parameters using the -* values prepared by mvDramIfDetect routine. Values are located -* in predefined registers. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ - -_mvDramIfConfig: - - /* Save register on stack */ - cmp sp, #0 - beq no_stack_s -save_on_stack: - stmdb sp!, {r1, r2, r3, r4} -no_stack_s: - - /* Dunit FTDLL Configuration Register */ - /* 0) Write to SDRAM FTDLL coniguration register */ - ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; - ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) - str r4, [r1] - ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; - ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) - str r4, [r1] - ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; - ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) - str r4, [r1] - - /* 1) Write to SDRAM coniguration register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) - str r4, [r1] - - /* 2) Write Dunit control low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) - str r4, [r1] - - /* 2) Write Dunit control high register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) - str r4, [r1] - - /* 3) Write SDRAM address control register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) - str r4, [r1] -#if defined(MV_STATIC_DRAM_ON_BOARD) - /* 4) Write SDRAM bank 0 size register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) - str r4, [r1] -#endif - - /* 5) Write SDRAM open pages control register */ - ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) - ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV - str r4, [r1] - - /* 6) Write SDRAM timing Low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) - str r4, [r1] - - /* 7) Write SDRAM timing High register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) - str r4, [r1] - - /* Config DDR2 On Die Termination (ODT) registers */ - /* Write SDRAM DDR2 ODT control low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) - str r4, [r1] - - /* Write SDRAM DDR2 ODT control high register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) - str r4, [r1] - - /* Write SDRAM DDR2 Dunit ODT control register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) - str r4, [r1] - - /* Write DDR2 SDRAM timing Low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) - str r4, [r1] - - /* Write DDR2 SDRAM timing High register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) - str r4, [r1] - - /* 8) Write SDRAM mode register */ - /* The CPU must not attempt to change the SDRAM Mode register setting */ - /* prior to DRAM controller completion of the DRAM initialization */ - /* sequence. To guarantee this restriction, it is recommended that */ - /* the CPU sets the SDRAM Operation register to NOP command, performs */ - /* read polling until the register is back in Normal operation value, */ - /* and then sets SDRAM Mode register to its new value. */ - - /* 8.1 write 'nop' to SDRAM operation */ - mov r4, #0x5 /* 'NOP' command */ - MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) - - /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll1: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll1 - - /* 8.3 Now its safe to write new value to SDRAM Mode register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) - str r4, [r1] - - /* 8.4 Make the Dunit write the DRAM its new mode */ - mov r4, #0x3 /* Mode Register Set command */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) - - /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll2: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll2 - - /* Now its safe to write new value to SDRAM Extended Mode regist */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) - str r4, [r1] - - /* 9) Write SDRAM Extended mode register This operation should be */ - /* done for each memory bank */ - /* write 'nop' to SDRAM operation */ - mov r4, #0x5 /* 'NOP' command */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll3: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll3 - /* Go over each of the Banks */ - ldr r3, =0 /* r3 = DRAM bank Num */ - -extModeLoop: - /* Set the SDRAM Operation Control to each of the DRAM banks */ - mov r4, r3 /* Do not swap the bank counter value */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) - - /* Make the Dunit write the DRAM its new mode */ - mov r4, #0x4 /* Extended Mode Register Set command */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll4: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll4 - - add r3, r3, #1 - cmp r3, #4 /* 4 = Number of banks */ - bne extModeLoop - -extModeEnd: -cmp sp, #0 - beq no_stack_l - mov r1, LR /* Save link register */ -#if defined(MV78XX0) - bl _mvDramIfMemInit -#endif - mov LR,r1 /* restore link register */ -load_from_stack: - /* Restore registers */ - ldmia sp!, {r1, r2, r3, r4} -no_stack_l: - - mov pc, lr - - -/******************************************************************************* -* _mvDramIfEccMemInit - Basic DRAM ECC initialization. -* -* DESCRIPTION: -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ -#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ -#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ -/* XOR engine register offsets macros */ -#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) -#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) -#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) -#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) -#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) -#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) -#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) -#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) -#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) - -/* XOR Engine Address Decoding Register Map */ -#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) - -.globl _mvDramIfEccMemInit -/******************************************************************************* -* _mvDramIfEccMemInit - mem init for dram cs -* -* DESCRIPTION: -* This function will clean the cs by ussing the XOR mem init. -* -* INPUT: -* r0 - dram bank number. -* -* OUTPUT: -* none -*/ -_mvDramIfEccMemInit: - - /* Save register on stack */ - cmp sp, #0 - beq no_stack_s1 -save_on_stack1: - stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} -no_stack_s1: - - ldr r1, = 0 - - /* Disable all XOR address decode windows to avoid possible overlap */ - MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) - - /* Init r5 to first XOR_SIZE_MASK_REG */ - mov r5, r0, LSL #3 - add r5, r5,#0x1500 - add r5, r5,#0x04 - add r5, r5,#(INTER_REGS_BASE) - ldr r6, [r5] - HTOLL(r6,r5) - MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) - - mov r5, r0, LSL #3 - add r5, r5,#0x1500 - add r5, r5,#(INTER_REGS_BASE) - ldr r6, [r5] - /* Update destination & size */ - MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) - HTOLL(r6,r5) - /* Init r6 to first XOR_BASE_ADDR_REG */ - ldr r4, = 0xf - ldr r5, = 0x1 - mov r5, r5, LSL r0 - bic r4, r4, r5 - mov r4, r4, LSL #8 - - orr r6, r6, r4 - MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) - - ldr r6, = 0xff0001 - MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) - - /* Configure XOR engine for memory init function. */ - MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) - and r6, r6, #~0x7 /* Clear operation mode field */ - orr r6, r6, #0x4 /* Set operation to memory init */ - MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) - - /* Set initVal in the XOR Engine Initial Value Registers */ - ldr r6, = 0xfeedfeed - MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) - ldr r6, = 0xfeedfeed - MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) - - /* Set block size using DRAM bank size */ - - mov r5, r0, LSL #3 - add r5, r5,#0x1500 - add r5, r5,#0x04 - add r5, r5,#(INTER_REGS_BASE) - - ldr r6, [r5] - HTOLL(r6,r5) - and r6, r6, #SCSR_SIZE_MASK - mov r5, r6, LSR #SCSR_SIZE_OFFS - add r5, r5, #1 - mov r6, r5, LSL #SCSR_SIZE_OFFS - MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) - - /* Clean interrupt cause*/ - MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) - - /* Clean error interrupt cause*/ - MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) - MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) - - /* Start transfer */ - MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) - orr r6, r6, #0x1 /* Preform start command */ - MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) - - /* Wait for engine to finish */ -waitForComplete: - MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) - and r6, r6, #2 - cmp r6, #0 - beq waitForComplete - - /* Clear all error report registers */ - MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) - MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) - - MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) - - cmp sp, #0 - beq no_stack_l1 -load_from_stack1: - ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} -no_stack_l1: - mov pc, lr - - -/******************************************************************************* -* mvDramIfMemInit - Use XOR to clear all memory. -* -* DESCRIPTION: -* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -#if defined(MV78XX0) - -_mvDramIfMemInit: - stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} - mov r6, LR /* Save link register */ - /* Check if dram bank 0 has to be init for ECC */ - MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) - and r3, r0, #SCSR_WIN_EN - cmp r3, #0 - beq no_bank_0 - MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) - cmp r0, #0 - beq no_bank_0 - mov r0,#0 - bl _mvDramIfEccMemInit - -no_bank_0: - /* Check if dram bank 1 has to be init for ECC */ - MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) - and r0, r0, #SCSR_WIN_EN - cmp r0, #0 - beq no_bank_1 - mov r0,#1 - bl _mvDramIfEccMemInit -no_bank_1: - /* Check if dram bank 2 has to be init for ECC */ - MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) - and r0, r0, #SCSR_WIN_EN - cmp r0, #0 - beq no_bank_2 - MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) - cmp r0, #0 - beq no_bank_2 - mov r0,#2 - bl _mvDramIfEccMemInit - -no_bank_2: - /* Check if dram bank 3 has to be init for ECC */ - MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) - and r0, r0, #SCSR_WIN_EN - cmp r0, #0 - beq no_bank_3 - mov r0,#3 - bl _mvDramIfEccMemInit -no_bank_3: - mov LR ,r6 /* restore link register */ - ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} - mov pc, lr -#endif - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h deleted file mode 100644 index 6141c46a08..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h +++ /dev/null @@ -1,157 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -#ifndef __INCmvDramIfConfigh -#define __INCmvDramIfConfigh - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* includes */ - -/* defines */ - -/* registers defaults values */ - -#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) - -#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ - (SDRAM_SRCLK_KEPT | \ - SDRAM_CLK1DRV_NORMAL | \ - (BIT28 | BIT29)) - -#define SDRAM_ADDR_CTRL_DV 2 - -#define SDRAM_TIMING_CTRL_LOW_REG_DV \ - ((0x2 << SDRAM_TRCD_OFFS) | \ - (0x2 << SDRAM_TRP_OFFS) | \ - (0x1 << SDRAM_TWR_OFFS) | \ - (0x0 << SDRAM_TWTR_OFFS) | \ - (0x5 << SDRAM_TRAS_OFFS) | \ - (0x1 << SDRAM_TRRD_OFFS)) - -/* Note: value of 0 in register means one cycle, 1 means two and so on */ -#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ - ((0x0 << SDRAM_TR2R_OFFS) | \ - (0x0 << SDRAM_TR2W_W2R_OFFS) | \ - (0x1 << SDRAM_TW2W_OFFS)) - -#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN - -/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ - -#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -#ifdef MV78XX0 -#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -#else -#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -#endif - -#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -#ifdef MV78XX0 -#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -#else -#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -#endif - -/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ - (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) - -#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ - (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) - -/* DDR SDRAM Mode Register default value */ -#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -/* DDR SDRAM Timing parameter default values */ -#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) - -#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) - -#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h deleted file mode 100644 index 369eda692b..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h +++ /dev/null @@ -1,423 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCmvDramIfRegsh -#define __INCmvDramIfRegsh - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* DDR SDRAM Controller Address Decode Registers */ - /* SDRAM CSn Base Address Register (SCBAR) */ -#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -#define SCBAR_BASE_OFFS 16 -#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -#define SCBAR_BASE_ALIGNMENT 0x10000 - -/* SDRAM CSn Size Register (SCSR) */ -#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -#define SCSR_SIZE_OFFS 24 -#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -#define SCSR_SIZE_ALIGNMENT 0x1000000 -#define SCSR_WIN_EN BIT0 - -/* configuration register */ -#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -#define SDRAM_REFRESH_OFFS 0 -#define SDRAM_REFRESH_MAX 0x3FFF -#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -#define SDRAM_DWIDTH_OFFS 15 -#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -#define SDRAM_REGISTERED (1 << 17) -#define SDRAM_ECC_OFFS 18 -#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -#define SDRAM_IERR_OFFS 19 -#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -#define SDRAM_SRMODE_OFFS 24 -#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) - -/* dunit control low register */ -#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -#define SDRAM_2T_OFFS 4 -#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) - -#define SDRAM_SRCLK_OFFS 5 -#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -#define SDRAM_CTRL_POS_OFFS 6 -#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -#define SDRAM_CLK1DRV_OFFS 12 -#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -#define SDRAM_CLK2DRV_OFFS 13 -#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -#define SDRAM_SB_OUT_DEL_OFFS 20 -#define SDRAM_SB_OUT_DEL_MAX 0xf -#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<<SDRAM_SB_OUT_DEL_OFFS) -#define SDRAM_SB_IN_DEL_OFFS 24 -#define SDRAM_SB_IN_DEL_MAX 0xf -#define SDRAM_SB_IN_MASK (SDRAM_SB_IN_DEL_MAX<<SDRAM_SB_IN_DEL_OFFS) - -/* dunit control hight register */ -#define SDRAM_DUNIT_CTRL_HI_REG (DRAM_BASE + 0x1424) -#define SDRAM__D2P_OFFS 7 -#define SDRAM__D2P_EN (1 << SDRAM__D2P_OFFS) -#define SDRAM__P2D_OFFS 8 -#define SDRAM__P2D_EN (1 << SDRAM__P2D_OFFS) -#define SDRAM__ADD_HALF_FCC_OFFS 9 -#define SDRAM__ADD_HALF_FCC_EN (1 << SDRAM__ADD_HALF_FCC_OFFS) -#define SDRAM__PUP_ZERO_SKEW_OFFS 10 -#define SDRAM__PUP_ZERO_SKEW_EN (1 << SDRAM__PUP_ZERO_SKEW_OFFS) -#define SDRAM__WR_MESH_DELAY_OFFS 11 -#define SDRAM__WR_MESH_DELAY_EN (1 << SDRAM__WR_MESH_DELAY_OFFS) - -/* sdram timing control low register */ -#define SDRAM_TIMING_CTRL_LOW_REG (DRAM_BASE + 0x1408) -#define SDRAM_TRCD_OFFS 4 -#define SDRAM_TRCD_MASK (0xF << SDRAM_TRCD_OFFS) -#define SDRAM_TRP_OFFS 8 -#define SDRAM_TRP_MASK (0xF << SDRAM_TRP_OFFS) -#define SDRAM_TWR_OFFS 12 -#define SDRAM_TWR_MASK (0xF << SDRAM_TWR_OFFS) -#define SDRAM_TWTR_OFFS 16 -#define SDRAM_TWTR_MASK (0xF << SDRAM_TWTR_OFFS) -#define SDRAM_TRAS_OFFS 0 -#define SDRAM_TRAS_MASK (0xF << SDRAM_TRAS_OFFS) -#define SDRAM_EXT_TRAS_OFFS 20 -#define SDRAM_EXT_TRAS_MASK (0x1 << SDRAM_EXT_TRAS_OFFS) -#define SDRAM_TRRD_OFFS 24 -#define SDRAM_TRRD_MASK (0xF << SDRAM_TRRD_OFFS) -#define SDRAM_TRTP_OFFS 28 -#define SDRAM_TRTP_MASK (0xF << SDRAM_TRTP_OFFS) -#define SDRAM_TRTP_DDR1 (0x1 << SDRAM_TRTP_OFFS) - -/* sdram timing control high register */ -#define SDRAM_TIMING_CTRL_HIGH_REG (DRAM_BASE + 0x140c) -#define SDRAM_TRFC_OFFS 0 -#define SDRAM_TRFC_MASK (0x3F << SDRAM_TRFC_OFFS) -#define SDRAM_TR2R_OFFS 7 -#define SDRAM_TR2R_MASK (0x3 << SDRAM_TR2R_OFFS) -#define SDRAM_TR2W_W2R_OFFS 9 -#define SDRAM_TR2W_W2R_MASK (0x3 << SDRAM_TR2W_W2R_OFFS) -#define SDRAM_TW2W_OFFS 11 -#define SDRAM_TW2W_MASK (0x3 << SDRAM_TW2W_OFFS) - -/* sdram DDR2 timing low register (SD2TLR) */ -#define SDRAM_DDR2_TIMING_LO_REG (DRAM_BASE + 0x1428) -#define SD2TLR_TODT_ON_RD_OFFS 4 -#define SD2TLR_TODT_ON_RD_MASK (0xF << SD2TLR_TODT_ON_RD_OFFS) -#define SD2TLR_TODT_OFF_RD_OFFS 8 -#define SD2TLR_TODT_OFF_RD_MASK (0xF << SD2TLR_TODT_OFF_RD_OFFS) -#define SD2TLR_TODT_ON_CTRL_RD_OFFS 12 -#define SD2TLR_TODT_ON_CTRL_RD_MASK (0xF << SD2TLR_TODT_ON_CTRL_RD_OFFS) -#define SD2TLR_TODT_OFF_CTRL_RD_OFFS 16 -#define SD2TLR_TODT_OFF_CTRL_RD_MASK (0xF << SD2TLR_TODT_OFF_CTRL_RD_OFFS) - -/* sdram DDR2 timing high register (SD2TLR) */ -#define SDRAM_DDR2_TIMING_HI_REG (DRAM_BASE + 0x147C) -#define SD2THR_TODT_ON_WR_OFFS 0 -#define SD2THR_TODT_ON_WR_MASK (0xF << SD2THR_TODT_ON_WR_OFFS) -#define SD2THR_TODT_OFF_WR_OFFS 4 -#define SD2THR_TODT_OFF_WR_MASK (0xF << SD2THR_TODT_OFF_WR_OFFS) -#define SD2THR_TODT_ON_CTRL_WR_OFFS 8 -#define SD2THR_TODT_ON_CTRL_WR_MASK (0xF << SD2THR_TODT_ON_CTRL_WR_OFFS) -#define SD2THR_TODT_OFF_CTRL_WR_OFFS 12 -#define SD2THR_TODT_OFF_CTRL_WR_MASK (0xF << SD2THR_TODT_OFF_CTRL_WR_OFFS) - -/* address control register */ -#define SDRAM_ADDR_CTRL_REG (DRAM_BASE + 0x1410) -#define SDRAM_ADDRSEL_OFFS(cs) (4 * (cs)) -#define SDRAM_ADDRSEL_MASK(cs) (0x3 << SDRAM_ADDRSEL_OFFS(cs)) -#define SDRAM_ADDRSEL_X8(cs) (0x0 << SDRAM_ADDRSEL_OFFS(cs)) -#define SDRAM_ADDRSEL_X16(cs) (0x1 << SDRAM_ADDRSEL_OFFS(cs)) -#define SDRAM_DSIZE_OFFS(cs) (2 + 4 * (cs)) -#define SDRAM_DSIZE_MASK(cs) (0x3 << SDRAM_DSIZE_OFFS(cs)) -#define SDRAM_DSIZE_256Mb(cs) (0x1 << SDRAM_DSIZE_OFFS(cs)) -#define SDRAM_DSIZE_512Mb(cs) (0x2 << SDRAM_DSIZE_OFFS(cs)) -#define SDRAM_DSIZE_1Gb(cs) (0x3 << SDRAM_DSIZE_OFFS(cs)) -#define SDRAM_DSIZE_2Gb(cs) (0x0 << SDRAM_DSIZE_OFFS(cs)) - -/* SDRAM Open Pages Control registers */ -#define SDRAM_OPEN_PAGE_CTRL_REG (DRAM_BASE + 0x1414) -#define SDRAM_OPEN_PAGE_EN (0 << 0) -#define SDRAM_OPEN_PAGE_DIS (1 << 0) - -/* sdram opertion register */ -#define SDRAM_OPERATION_REG (DRAM_BASE + 0x1418) -#define SDRAM_CMD_OFFS 0 -#define SDRAM_CMD_MASK (0xF << SDRAM_CMD_OFFS) -#define SDRAM_CMD_NORMAL (0x0 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_REFRESH_ALL (0x2 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_REG_SET_CMD (0x3 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_EXT_MODE_SET (0x4 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_NOP (0x5 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_SLF_RFRSH (0x7 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_EMRS2_CMD (0x8 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_EMRS3_CMD (0x9 << SDRAM_CMD_OFFS) - -/* sdram mode register */ -#define SDRAM_MODE_REG (DRAM_BASE + 0x141c) -#define SDRAM_BURST_LEN_OFFS 0 -#define SDRAM_BURST_LEN_MASK (0x7 << SDRAM_BURST_LEN_OFFS) -#define SDRAM_BURST_LEN_4 (0x2 << SDRAM_BURST_LEN_OFFS) -#define SDRAM_CL_OFFS 4 -#define SDRAM_CL_MASK (0x7 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_3 (0x3 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_4 (0x4 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_5 (0x5 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_6 (0x6 << SDRAM_CL_OFFS) - -#define SDRAM_TM_OFFS 7 -#define SDRAM_TM_MASK (1 << SDRAM_TM_OFFS) -#define SDRAM_TM_NORMAL (0 << SDRAM_TM_OFFS) -#define SDRAM_TM_TEST_MODE (1 << SDRAM_TM_OFFS) -#define SDRAM_DLL_OFFS 8 -#define SDRAM_DLL_MASK (1 << SDRAM_DLL_OFFS) -#define SDRAM_DLL_NORMAL (0 << SDRAM_DLL_OFFS) -#define SDRAM_DLL_RESET (1 << SDRAM_DLL_OFFS) -#define SDRAM_WR_OFFS 9 -#define SDRAM_WR_MAX 7 -#define SDRAM_WR_MASK (SDRAM_WR_MAX << SDRAM_WR_OFFS) -#define SDRAM_WR_2_CYC (1 << SDRAM_WR_OFFS) -#define SDRAM_WR_3_CYC (2 << SDRAM_WR_OFFS) -#define SDRAM_WR_4_CYC (3 << SDRAM_WR_OFFS) -#define SDRAM_WR_5_CYC (4 << SDRAM_WR_OFFS) -#define SDRAM_WR_6_CYC (5 << SDRAM_WR_OFFS) -#define SDRAM_PD_OFFS 12 -#define SDRAM_PD_MASK (1 << SDRAM_PD_OFFS) -#define SDRAM_PD_FAST_EXIT (0 << SDRAM_PD_OFFS) -#define SDRAM_PD_SLOW_EXIT (1 << SDRAM_PD_OFFS) - -/* DDR SDRAM Extended Mode register (DSEMR) */ -#define SDRAM_EXTENDED_MODE_REG (DRAM_BASE + 0x1420) -#define DSEMR_DLL_ENABLE 0 -#define DSEMR_DLL_DISABLE 1 -#define DSEMR_DS_OFFS 1 -#define DSEMR_DS_MASK (1 << DSEMR_DS_OFFS) -#define DSEMR_DS_NORMAL (0 << DSEMR_DS_OFFS) -#define DSEMR_DS_REDUCED (1 << DSEMR_DS_OFFS) -#define DSEMR_QOFF_OUTPUT_BUFF_EN (0 << 12) -#define DSEMR_RTT0_OFFS 2 -#define DSEMR_RTT1_OFFS 6 -#define DSEMR_RTT_ODT_DISABLE ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS)) -#define DSEMR_RTT_ODT_75_OHM ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS)) -#define DSEMR_RTT_ODT_150_OHM ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS)) -#define DSEMR_RTT_ODT_50_OHM ((1 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS)) -#define DSEMR_DQS_OFFS 10 -#define DSEMR_DQS_MASK (1 << DSEMR_DQS_OFFS) -#define DSEMR_DQS_DIFFERENTIAL (0 << DSEMR_DQS_OFFS) -#define DSEMR_DQS_SINGLE_ENDED (1 << DSEMR_DQS_OFFS) -#define DSEMR_RDQS_ENABLE (1 << 11) -#define DSEMR_QOFF_OUTPUT_BUFF_EN (0 << 12) -#define DSEMR_QOFF_OUTPUT_BUFF_DIS (1 << 12) - -/* DDR SDRAM Operation Control Register */ -#define SDRAM_OPERATION_CTRL_REG (DRAM_BASE + 0x142c) - -/* Dunit FTDLL Configuration Register */ -#define SDRAM_FTDLL_CONFIG_LEFT_REG (DRAM_BASE + 0x1484) -#define SDRAM_FTDLL_CONFIG_RIGHT_REG (DRAM_BASE + 0x161C) -#define SDRAM_FTDLL_CONFIG_UP_REG (DRAM_BASE + 0x1620) - -/* Pads Calibration register */ -#define SDRAM_ADDR_CTRL_PADS_CAL_REG (DRAM_BASE + 0x14c0) -#define SDRAM_DATA_PADS_CAL_REG (DRAM_BASE + 0x14c4) -#define SDRAM_DRVN_OFFS 0 -#define SDRAM_DRVN_MASK (0x3F << SDRAM_DRVN_OFFS) -#define SDRAM_DRVP_OFFS 6 -#define SDRAM_DRVP_MASK (0x3F << SDRAM_DRVP_OFFS) -#define SDRAM_PRE_DRIVER_STRENGTH_OFFS 12 -#define SDRAM_PRE_DRIVER_STRENGTH_MASK (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -#define SDRAM_TUNE_EN BIT16 -#define SDRAM_LOCKN_OFFS 17 -#define SDRAM_LOCKN_MAKS (0x3F << SDRAM_LOCKN_OFFS) -#define SDRAM_LOCKP_OFFS 23 -#define SDRAM_LOCKP_MAKS (0x3F << SDRAM_LOCKP_OFFS) -#define SDRAM_WR_EN (1 << 31) - -/* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */ -#define DDR2_SDRAM_ODT_CTRL_LOW_REG (DRAM_BASE + 0x1494) -#define DSOCLR_ODT_RD_OFFS(odtNum) (odtNum * 4) -#define DSOCLR_ODT_RD_MASK(odtNum) (0xf << DSOCLR_ODT_RD_OFFS(odtNum)) -#define DSOCLR_ODT_RD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum)) -#define DSOCLR_ODT_WR_OFFS(odtNum) (16 + (odtNum * 4)) -#define DSOCLR_ODT_WR_MASK(odtNum) (0xf << DSOCLR_ODT_WR_OFFS(odtNum)) -#define DSOCLR_ODT_WR(odtNum, bank) ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum)) - -/* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */ -#define DDR2_SDRAM_ODT_CTRL_HIGH_REG (DRAM_BASE + 0x1498) -/* Optional control values to DSOCHR_ODT_EN macro */ -#define DDR2_ODT_CTRL_DUNIT 0 -#define DDR2_ODT_CTRL_NEVER 1 -#define DDR2_ODT_CTRL_ALWAYS 3 -#define DSOCHR_ODT_EN_OFFS(odtNum) (odtNum * 2) -#define DSOCHR_ODT_EN_MASK(odtNum) (0x3 << DSOCHR_ODT_EN_OFFS(odtNum)) -#define DSOCHR_ODT_EN(odtNum, ctrl) (ctrl << DSOCHR_ODT_EN_OFFS(odtNum)) - -/* DDR2 Dunit ODT Control Register (DDOCR)*/ -#define DDR2_DUNIT_ODT_CONTROL_REG (DRAM_BASE + 0x149c) -#define DDOCR_ODT_RD_OFFS 0 -#define DDOCR_ODT_RD_MASK (0xf << DDOCR_ODT_RD_OFFS) -#define DDOCR_ODT_RD(bank) ((1 << bank) << DDOCR_ODT_RD_OFFS) -#define DDOCR_ODT_WR_OFFS 4 -#define DDOCR_ODT_WR_MASK (0xf << DDOCR_ODT_WR_OFFS) -#define DDOCR_ODT_WR(bank) ((1 << bank) << DDOCR_ODT_WR_OFFS) -#define DSOCR_ODT_EN_OFFS 8 -#define DSOCR_ODT_EN_MASK (0x3 << DSOCR_ODT_EN_OFFS) -/* For ctrl parameters see DDR2 SDRAM ODT Control (High) Register (0x1498) above. */ -#define DSOCR_ODT_EN(ctrl) (ctrl << DSOCR_ODT_EN_OFFS) -#define DSOCR_ODT_SEL_DISABLE 0 -#define DSOCR_ODT_SEL_75_OHM 2 -#define DSOCR_ODT_SEL_150_OHM 1 -#define DSOCR_ODT_SEL_50_OHM 3 -#define DSOCR_DQ_ODT_SEL_OFFS 10 -#define DSOCR_DQ_ODT_SEL_MASK (0x3 << DSOCR_DQ_ODT_SEL_OFFS) -#define DSOCR_DQ_ODT_SEL(odtSel) (odtSel << DSOCR_DQ_ODT_SEL_OFFS) -#define DSOCR_ST_ODT_SEL_OFFS 12 -#define DSOCR_ST_ODT_SEL_MASK (0x3 << DSOCR_ST_ODT_SEL_OFFS) -#define DSOCR_ST_ODT_SEL(odtSel) (odtSel << DSOCR_ST_ODT_SEL_OFFS) -#define DSOCR_ST_ODT_EN (1 << 14) - -/* DDR SDRAM Initialization Control Register (DSICR) */ -#define DDR_SDRAM_INIT_CTRL_REG (DRAM_BASE + 0x1480) -#define DSICR_INIT_EN (1 << 0) -#define DSICR_T200_SET (1 << 8) - -/* sdram extended mode2 register (SEM2R) */ -#define SDRAM_EXTENDED_MODE2_REG (DRAM_BASE + 0x148C) -#define SEM2R_EMRS2_DDR2_OFFS 0 -#define SEM2R_EMRS2_DDR2_MASK (0x7FFF << SEM2R_EMRS2_DDR2_OFFS) - -/* sdram extended mode3 register (SEM3R) */ -#define SDRAM_EXTENDED_MODE3_REG (DRAM_BASE + 0x1490) -#define SEM3R_EMRS3_DDR2_OFFS 0 -#define SEM3R_EMRS3_DDR2_MASK (0x7FFF << SEM3R_EMRS3_DDR2_OFFS) - -/* sdram error registers */ -#define SDRAM_ERROR_CAUSE_REG (DRAM_BASE + 0x14d0) -#define SDRAM_ERROR_MASK_REG (DRAM_BASE + 0x14d4) -#define SDRAM_ERROR_DATA_LOW_REG (DRAM_BASE + 0x1444) -#define SDRAM_ERROR_DATA_HIGH_REG (DRAM_BASE + 0x1440) -#define SDRAM_ERROR_ADDR_REG (DRAM_BASE + 0x1450) -#define SDRAM_ERROR_ECC_REG (DRAM_BASE + 0x1448) -#define SDRAM_CALC_ECC_REG (DRAM_BASE + 0x144c) -#define SDRAM_ECC_CONTROL_REG (DRAM_BASE + 0x1454) -#define SDRAM_SINGLE_BIT_ERR_CNTR_REG (DRAM_BASE + 0x1458) -#define SDRAM_DOUBLE_BIT_ERR_CNTR_REG (DRAM_BASE + 0x145c) - -/* SDRAM Error Cause Register (SECR) */ -#define SECR_SINGLE_BIT_ERR BIT0 -#define SECR_DOUBLE_BIT_ERR BIT1 -#define SECR_DATA_PATH_PARITY_ERR BIT2 -/* SDRAM Error Address Register (SEAR) */ -#define SEAR_ERR_TYPE_OFFS 0 -#define SEAR_ERR_TYPE_MASK (1 << SEAR_ERR_TYPE_OFFS) -#define SEAR_ERR_TYPE_SINGLE 0 -#define SEAR_ERR_TYPE_DOUBLE (1 << SEAR_ERR_TYPE_OFFS) -#define SEAR_ERR_CS_OFFS 1 -#define SEAR_ERR_CS_MASK (3 << SEAR_ERR_CS_OFFS) -#define SEAR_ERR_CS(csNum) (csNum << SEAR_ERR_CS_OFFS) -#define SEAR_ERR_ADDR_OFFS 3 -#define SEAR_ERR_ADDR_MASK (0x1FFFFFFF << SEAR_ERR_ADDR_OFFS) - -/* SDRAM ECC Control Register (SECR) */ -#define SECR_FORCEECC_OFFS 0 -#define SECR_FORCEECC_MASK (0xFF << SECR_FORCEECC_OFFS) -#define SECR_FORCEEN_OFFS 8 -#define SECR_FORCEEN_MASK (1 << SECR_FORCEEN_OFFS) -#define SECR_ECC_CALC_MASK (0 << SECR_FORCEEN_OFFS) -#define SECR_ECC_USER_MASK (1 << SECR_FORCEEN_OFFS) -#define SECR_PERRPROP_EN BIT9 -#define SECR_CNTMODE_OFFS 10 -#define SECR_CNTMODE_MASK (1 << SECR_CNTMODE_OFFS) -#define SECR_ALL_IN_CS0 (0 << SECR_CNTMODE_OFFS) -#define SECR_NORMAL_COUNTER (1 << SECR_CNTMODE_OFFS) -#define SECR_THRECC_OFFS 16 -#define SECR_THRECC_MAX 0xFF -#define SECR_THRECC_MASK (SECR_THRECC_MAX << SECR_THRECC_OFFS) -#define SECR_THRECC(threshold) (threshold << SECR_THRECC_OFFS) - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __INCmvDramIfRegsh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h deleted file mode 100644 index f3bf83b4ea..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h +++ /dev/null @@ -1,179 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -#ifndef __INCmvDramIfStaticInith -#define __INCmvDramIfStaticInith - -#ifdef MV_STATIC_DRAM_ON_BOARD -#define STATIC_DRAM_BANK_1 -#undef STATIC_DRAM_BANK_2 -#undef STATIC_DRAM_BANK_3 -#undef STATIC_DRAM_BANK_4 - - -#ifdef MV_DIMM_TS256MLQ72V5U -#define STATIC_DRAM_BANK_2 -#define STATIC_DRAM_BANK_3 -#undef STATIC_DRAM_BANK_4 - -#define STATIC_SDRAM_CONFIG_REG 0x4724481A /* offset 0x1400 - DMA reg-0xf1000814 */ -#define STATIC_SDRAM_DUNIT_CTRL_REG 0x37707450 /* offset 0x1404 - DMA reg-0xf100081c */ -#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11A13330 /* offset 0x1408 - DMA reg-0xf1000824 */ -#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000601 /* offset 0x140c - DMA reg-0xf1000828 */ -#define STATIC_SDRAM_ADDR_CTRL_REG 0x00001CB2 /* offset 0x1410 - DMA reg-0xf1000820 */ -#define STATIC_SDRAM_MODE_REG 0x00000642 /* offset 0x141c - DMA reg-0xf1000818 */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000740F /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000404 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00074410 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00007441 /* 0x147C */ - -#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x3FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */ -#define STATIC_SDRAM_RANK1_SIZE_DIMM0 0x3FFF /* size bank1 dimm0 */ -#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x3FFF /* size bank0 dimm1 */ -#define STATIC_SDRAM_RANK1_SIZE_DIMM1 0x0 /* size bank1 dimm1 */ - -#endif /* TS256MLQ72V5U */ - - -#ifdef MV_MT9VDDT3272AG -/* one DIMM 256M */ -#define STATIC_SDRAM_CONFIG_REG 0x5820040d /* offset 0x1400 - DMA reg-0xf1000814 */ -#define STATIC_SDRAM_DUNIT_CTRL_REG 0xC4000540 /* offset 0x1404 - DMA reg-0xf100081c */ -#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01602220 /* offset 0x1408 - DMA reg-0xf1000824 */ -#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x0000000b /* offset 0x140c - DMA reg-0xf1000828 */ -#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */ -#define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */ -#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0fff /* size bank0 dimm0 - DMA reg-0xf1000810 */ -#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0 /* size bank0 dimm1 */ - -#endif /* MV_MT9VDDT3272AG */ - - - -#ifdef MV_D27RB12P -/* -Two DIMM 512M + ECC enabled, Registered DIMM CAS Latency 2.5 -*/ - -#define STATIC_SDRAM_CONFIG_REG 0x6826081E /* offset 0x1400 - DMA reg-0xf1000814 */ -#define STATIC_SDRAM_DUNIT_CTRL_REG 0xC5000540 /* offset 0x1404 - DMA reg-0xf100081c */ -#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01501220 /* offset 0x1408 - DMA reg-0xf1000824 */ -#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000009 /* offset 0x140c - DMA reg-0xf1000828 */ -#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */ -#define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */ -#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */ -#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0FFF /* size bank0 dimm1 */ - -#define STATIC_DRAM_BANK_2 - -#define STATIC_DRAM_BANK_3 -#define STATIC_DRAM_BANK_4 - -#endif /* mv_D27RB12P */ - -#ifdef RD_MV645XX - -#define STATIC_MEM_TYPE MEM_TYPE_DDR2 -#define STATIC_DIMM_INFO_BANK0_SIZE 256 -/* DDR2 boards 256 MB*/ - -#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000fff /* size bank0 dimm0 - DMA reg-0xf1000810 */ -#define STATIC_SDRAM_CONFIG_REG 0x07190618 -#define STATIC_SDRAM_MODE_REG 0x00000432 -#define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440 -#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022 -#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220 -#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504 -#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f -#define STATIC_SDRAM_EXT_MODE 0x00000440 -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300 -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330 -#endif /* RD_MV645XX */ - -#if MV_DIMM_M3783354CZ3_CE6 - -#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000FFF /* 0x2010 size bank0 dimm0 - DMA reg-0xf1000810 */ -#define STATIC_SDRAM_CONFIG_REG 0x07190618 /* 0x1400 */ -#define STATIC_SDRAM_MODE_REG 0x00000432 /* 0x141c */ -#define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440 /* 0x1404 */ -#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022 /* 0x1410 */ -#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220 /* 0x1408 */ -#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504 /* 0x140c */ -#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f /* 0x149c */ -#define STATIC_SDRAM_EXT_MODE 0x00000440 /* 0x1420 */ -#define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300 /* 0x1428 */ -#define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330 /* 0x147C */ - -#endif /* MV_DIMM_M3783354CZ3_CE6 */ - -#endif /* MV_STATIC_DRAM_ON_BOARD */ -#endif /* __INCmvDramIfStaticInith */ - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c deleted file mode 100644 index 7a26f90597..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c +++ /dev/null @@ -1,1474 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include "ddr2/spd/mvSpd.h" -#include "boardEnv/mvBoardEnvLib.h" - -/* #define MV_DEBUG */ -#ifdef MV_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, - MV_DRAM_BANK_INFO *pBankInfo); -static MV_U32 cas2ps(MV_U8 spd_byte); -/******************************************************************************* -* mvDramBankGet - Get the DRAM bank paramters. -* -* DESCRIPTION: -* This function retrieves DRAM bank parameters as described in -* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -* from it. Otherwise, if the DRAM is soldered on board, the function -* should insert its bank information into MV_DRAM_BANK_INFO struct. -* -* INPUT: -* bankNum - Board DRAM bank number. -* -* OUTPUT: -* pBankInfo - DRAM bank information struct. -* -* RETURN: -* MV_FAIL - Bank parameters could not be read. -* -*******************************************************************************/ -MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -{ - MV_DIMM_INFO dimmInfo; - - DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); - /* zero pBankInfo structure */ - - if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) - { - DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); - return MV_BAD_PARAM; - } - memset(pBankInfo, 0, sizeof(*pBankInfo)); - - if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) - { - DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); - return MV_FAIL; - } - if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) - { - DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); - return MV_FAIL; - } - /* convert Dimm info to Bank info */ - cpyDimm2BankInfo(&dimmInfo, pBankInfo); - return MV_OK; -} - -/******************************************************************************* -* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -* -* DESCRIPTION: -* Convert a Dimm info struct into a bank info struct. -* -* INPUT: -* pDimmInfo - DIMM information structure. -* -* OUTPUT: -* pBankInfo - DRAM bank information struct. -* -* RETURN: -* None. -* -*******************************************************************************/ -static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, - MV_DRAM_BANK_INFO *pBankInfo) -{ - pBankInfo->memoryType = pDimmInfo->memoryType; - - /* DIMM dimensions */ - pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; - pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; - pBankInfo->dataWidth = pDimmInfo->dataWidth; - pBankInfo->errorCheckType = pDimmInfo->errorCheckType; - pBankInfo->sdramWidth = pDimmInfo->sdramWidth; - pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; - pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; - pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; - pBankInfo->refreshInterval = pDimmInfo->refreshInterval; - - /* DIMM timing parameters */ - pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; - pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = - pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; - pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = - pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; - - pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; - pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; - pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; - pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; - pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; - pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; - pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; - pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; - - /* Parameters calculated from the extracted DIMM information */ - pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; - pBankInfo->deviceDensity = pDimmInfo->deviceDensity; - pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / - pDimmInfo->numOfModuleBanks; - - /* DIMM attributes (MV_TRUE for yes) */ - - if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || - (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) - { - if (pDimmInfo->dimmAttributes & BIT1) - pBankInfo->registeredAddrAndControlInputs = MV_TRUE; - else - pBankInfo->registeredAddrAndControlInputs = MV_FALSE; - } - else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ - { - if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) - pBankInfo->registeredAddrAndControlInputs = MV_TRUE; - else - pBankInfo->registeredAddrAndControlInputs = MV_FALSE; - } - - return; -} -/******************************************************************************* -* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -* -* DESCRIPTION: -* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -* -*******************************************************************************/ -MV_STATUS dimmSpdCpy(MV_VOID) -{ - MV_U32 i; - MV_U32 spdChecksum; - - MV_TWSI_SLAVE twsiSlave; - MV_U8 data[SPD_SIZE]; - - /* zero dimmInfo structure */ - memset(data, 0, SPD_SIZE); - - /* read the dimm eeprom */ - DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); - twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; - twsiSlave.slaveAddr.type = ADDR7_BIT; - twsiSlave.validOffset = MV_TRUE; - twsiSlave.offset = 0; - twsiSlave.moreThen256 = MV_FALSE; - - if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) - { - DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); - return MV_FAIL; - } - DB(puts("DRAM: Reading dimm info succeded.\n")); - - /* calculate SPD checksum */ - spdChecksum = 0; - - for(i = 0 ; i <= 62 ; i++) - { - spdChecksum += data[i]; - } - - if ((spdChecksum & 0xff) != data[63]) - { - DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", - (MV_U32)(spdChecksum & 0xff), data[63])); - } - else - { - DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); - } - - /* copy the SPD content 1:1 into the DIMM 1 SPD */ - twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; - twsiSlave.slaveAddr.type = ADDR7_BIT; - twsiSlave.validOffset = MV_TRUE; - twsiSlave.offset = 0; - twsiSlave.moreThen256 = MV_FALSE; - - for(i = 0 ; i < SPD_SIZE ; i++) - { - twsiSlave.offset = i; - if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) - { - mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); - return MV_FAIL; - } - mvOsDelay(5); - } - - DB(puts("DRAM: Reading dimm info succeded.\n")); - return MV_OK; -} - -/******************************************************************************* -* dimmSpdGet - Get the SPD parameters. -* -* DESCRIPTION: -* Read the DIMM SPD parameters into given struct parameter. -* -* INPUT: -* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -* -* OUTPUT: -* pDimmInfo - DIMM information structure. -* -* RETURN: -* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -* -*******************************************************************************/ -MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -{ - MV_U32 i; - MV_U32 density = 1; - MV_U32 spdChecksum; - - MV_TWSI_SLAVE twsiSlave; - MV_U8 data[SPD_SIZE]; - - if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) - { - DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); - return MV_BAD_PARAM; - } - - /* zero dimmInfo structure */ - memset(data, 0, SPD_SIZE); - - /* read the dimm eeprom */ - DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); - twsiSlave.slaveAddr.address = (dimmNum == 0) ? - MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; - twsiSlave.slaveAddr.type = ADDR7_BIT; - twsiSlave.validOffset = MV_TRUE; - twsiSlave.offset = 0; - twsiSlave.moreThen256 = MV_FALSE; - - if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) - { - DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); - return MV_FAIL; - } - DB(puts("DRAM: Reading dimm info succeded.\n")); - - /* calculate SPD checksum */ - spdChecksum = 0; - - for(i = 0 ; i <= 62 ; i++) - { - spdChecksum += data[i]; - } - - if ((spdChecksum & 0xff) != data[63]) - { - DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", - (MV_U32)(spdChecksum & 0xff), data[63])); - } - else - { - DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); - } - - /* copy the SPD content 1:1 into the dimmInfo structure*/ - for(i = 0 ; i < SPD_SIZE ; i++) - { - pDimmInfo->spdRawData[i] = data[i]; - DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); - } - - DB(mvOsPrintf("DRAM SPD Information:\n")); - - /* Memory type (DDR / SDRAM) */ - switch (data[DIMM_MEM_TYPE]) - { - case (DIMM_MEM_TYPE_SDRAM): - pDimmInfo->memoryType = MEM_TYPE_SDRAM; - DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); - break; - case (DIMM_MEM_TYPE_DDR1): - pDimmInfo->memoryType = MEM_TYPE_DDR1; - DB(mvOsPrintf("DRAM Memeory type DDR1\n")); - break; - case (DIMM_MEM_TYPE_DDR2): - pDimmInfo->memoryType = MEM_TYPE_DDR2; - DB(mvOsPrintf("DRAM Memeory type DDR2\n")); - break; - default: - mvOsPrintf("ERROR: Undefined memory type!\n"); - return MV_ERROR; - } - - - /* Number Of Row Addresses */ - pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; - DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); - - /* Number Of Column Addresses */ - pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; - DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); - - /* Number Of Module Banks */ - pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; - DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", - pDimmInfo->numOfModuleBanks)); - - /* Number of module banks encoded differently for DDR2 */ - if (pDimmInfo->memoryType == MEM_TYPE_DDR2) - pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; - - /* Data Width */ - pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; - DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); - - /* Minimum Cycle Time At Max CasLatancy */ - pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); - - /* Error Check Type */ - pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; - DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", - pDimmInfo->errorCheckType)); - - /* Refresh Interval */ - pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; - DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", - pDimmInfo->refreshInterval)); - - /* Sdram Width */ - pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; - DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); - - /* Error Check Data Width */ - pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; - DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", - pDimmInfo->errorCheckDataWidth)); - - /* Burst Length Supported */ - /* SDRAM/DDR1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * - *********************************************************/ - /* DDR2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * - *********************************************************/ - - pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; - DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", - pDimmInfo->burstLengthSupported)); - - /* Number Of Banks On Each Device */ - pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; - DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", - pDimmInfo->numOfBanksOnEachDevice)); - - /* Suported Cas Latencies */ - - /* SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - - /* DDR 1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - *********************************************************/ - - /* DDR 2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * - *********************************************************/ - - pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; - DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", - pDimmInfo->suportedCasLatencies)); - - /* For DDR2 only, get the DIMM type information */ - if (pDimmInfo->memoryType == MEM_TYPE_DDR2) - { - pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; - DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", - pDimmInfo->dimmTypeInfo)); - } - - /* SDRAM Modules Attributes */ - pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; - DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", - pDimmInfo->dimmAttributes)); - - /* Minimum Cycle Time At Max CasLatancy Minus 1*/ - pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = - cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); - - /* Minimum Cycle Time At Max CasLatancy Minus 2*/ - pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = - cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); - - pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; - DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", - pDimmInfo->minRowPrechargeTime)); - pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; - DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", - pDimmInfo->minRowActiveToRowActive)); - pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; - DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", - pDimmInfo->minRasToCasDelay)); - pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; - DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", - pDimmInfo->minRasPulseWidth)); - - /* DIMM Bank Density */ - pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; - DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", - pDimmInfo->dimmBankDensity)); - - /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ - pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; - DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", - pDimmInfo->minWriteRecoveryTime)); - - /* Only DDR2 includes Internal Write To Read Command Delay field. */ - pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; - DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", - pDimmInfo->minWriteToReadCmdDelay)); - - /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ - pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; - DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", - pDimmInfo->minReadToPrechCmdDelay)); - - /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ - pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; - DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", - pDimmInfo->minRefreshToActiveCmd)); - - /* calculating the sdram density. Representing device density from */ - /* bit 20 to allow representation of 4GB and above. */ - /* For example, if density is 512Mbit 0x20000000, will be represent in */ - /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ - /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ - density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); - pDimmInfo->deviceDensity = density * - pDimmInfo->numOfBanksOnEachDevice * - pDimmInfo->sdramWidth; - DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); - - /* Number of devices includeing Error correction */ - pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * - pDimmInfo->numOfModuleBanks; - DB(mvOsPrintf("DRAM numberOfDevices %d\n", - pDimmInfo->numberOfDevices)); - - pDimmInfo->size = 0; - - /* Note that pDimmInfo->size is in MB units */ - if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) - { - if (pDimmInfo->dimmBankDensity & BIT0) - pDimmInfo->size += 1024; /* Equal to 1GB */ - else if (pDimmInfo->dimmBankDensity & BIT1) - pDimmInfo->size += 8; /* Equal to 8MB */ - else if (pDimmInfo->dimmBankDensity & BIT2) - pDimmInfo->size += 16; /* Equal to 16MB */ - else if (pDimmInfo->dimmBankDensity & BIT3) - pDimmInfo->size += 32; /* Equal to 32MB */ - else if (pDimmInfo->dimmBankDensity & BIT4) - pDimmInfo->size += 64; /* Equal to 64MB */ - else if (pDimmInfo->dimmBankDensity & BIT5) - pDimmInfo->size += 128; /* Equal to 128MB */ - else if (pDimmInfo->dimmBankDensity & BIT6) - pDimmInfo->size += 256; /* Equal to 256MB */ - else if (pDimmInfo->dimmBankDensity & BIT7) - pDimmInfo->size += 512; /* Equal to 512MB */ - } - else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) - { - if (pDimmInfo->dimmBankDensity & BIT0) - pDimmInfo->size += 1024; /* Equal to 1GB */ - else if (pDimmInfo->dimmBankDensity & BIT1) - pDimmInfo->size += 2048; /* Equal to 2GB */ - else if (pDimmInfo->dimmBankDensity & BIT2) - pDimmInfo->size += 16; /* Equal to 16MB */ - else if (pDimmInfo->dimmBankDensity & BIT3) - pDimmInfo->size += 32; /* Equal to 32MB */ - else if (pDimmInfo->dimmBankDensity & BIT4) - pDimmInfo->size += 64; /* Equal to 64MB */ - else if (pDimmInfo->dimmBankDensity & BIT5) - pDimmInfo->size += 128; /* Equal to 128MB */ - else if (pDimmInfo->dimmBankDensity & BIT6) - pDimmInfo->size += 256; /* Equal to 256MB */ - else if (pDimmInfo->dimmBankDensity & BIT7) - pDimmInfo->size += 512; /* Equal to 512MB */ - } - else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ - { - if (pDimmInfo->dimmBankDensity & BIT0) - pDimmInfo->size += 1024; /* Equal to 1GB */ - else if (pDimmInfo->dimmBankDensity & BIT1) - pDimmInfo->size += 2048; /* Equal to 2GB */ - else if (pDimmInfo->dimmBankDensity & BIT2) - pDimmInfo->size += 4096; /* Equal to 4GB */ - else if (pDimmInfo->dimmBankDensity & BIT3) - pDimmInfo->size += 8192; /* Equal to 8GB */ - else if (pDimmInfo->dimmBankDensity & BIT4) - pDimmInfo->size += 16384; /* Equal to 16GB */ - else if (pDimmInfo->dimmBankDensity & BIT5) - pDimmInfo->size += 128; /* Equal to 128MB */ - else if (pDimmInfo->dimmBankDensity & BIT6) - pDimmInfo->size += 256; /* Equal to 256MB */ - else if (pDimmInfo->dimmBankDensity & BIT7) - pDimmInfo->size += 512; /* Equal to 512MB */ - } - - pDimmInfo->size *= pDimmInfo->numOfModuleBanks; - - DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); - - return MV_OK; -} - -/******************************************************************************* -* dimmSpdPrint - Print the SPD parameters. -* -* DESCRIPTION: -* Print the Dimm SPD parameters. -* -* INPUT: -* pDimmInfo - DIMM information structure. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -MV_VOID dimmSpdPrint(MV_U32 dimmNum) -{ - MV_DIMM_INFO dimmInfo; - MV_U32 i, temp = 0; - MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; - MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; - MV_U32 busClkPs; - MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, - temp_buf[40], *spdRawData; - - busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ - - spdRawData = dimmInfo.spdRawData; - - if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) - { - mvOsOutput("ERROR: Could not read SPD information!\n"); - return; - } - - /* find Manufactura of Dimm Module */ - mvOsOutput("\nManufacturer's JEDEC ID Code: "); - for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) - { - mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); - } - mvOsOutput("\n"); - - /* Manufacturer's Specific Data */ - for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) - { - temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; - } - mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); - - /* Module Part Number */ - for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) - { - temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; - } - mvOsOutput("Module Part Number: %s\n", temp_buf); - - /* Module Serial Number */ - for(i = 0; i < sizeof(MV_U32); i++) - { - temp |= spdRawData[95+i] << 8*i; - } - mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, - (long)temp); - - /* find Manufac-Data of Dimm Module */ - mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", - ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), - ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); - /* find modul_revision of Dimm Module */ - mvOsOutput("Module Revision: %d.%d\n", - spdRawData[62]/10, spdRawData[62]%10); - - /* find manufac_place of Dimm Module */ - mvOsOutput("manufac_place: %d\n", spdRawData[72]); - - /* go over the first 35 I2C data bytes */ - for(i = 2 ; i <= 35 ; i++) - switch(i) - { - case 2: /* Memory type (DDR1/2 / SDRAM) */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - mvOsOutput("Dram Type is: SDRAM\n"); - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - mvOsOutput("Dram Type is: SDRAM DDR1\n"); - else if (dimmInfo.memoryType == MEM_TYPE_DDR2) - mvOsOutput("Dram Type is: SDRAM DDR2\n"); - else - mvOsOutput("Dram Type unknown\n"); - break; -/*----------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - mvOsOutput("Module Number of row addresses: %d\n", - dimmInfo.numOfRowAddr); - break; -/*----------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - mvOsOutput("Module Number of col addresses: %d\n", - dimmInfo.numOfColAddr); - break; -/*----------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - mvOsOutput("Number of Banks on Mod.: %d\n", - dimmInfo.numOfModuleBanks); - break; -/*----------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - mvOsOutput("Module Data Width: %d bit\n", - dimmInfo.dataWidth); - break; -/*----------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch(spdRawData[i]) - { - case 0x0: - mvOsOutput("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - mvOsOutput("Module is LVTTL\n"); - break; - case 0x2: - mvOsOutput("Module is HSTL_1_5V\n"); - break; - case 0x3: - mvOsOutput("Module is SSTL_3_3V\n"); - break; - case 0x4: - mvOsOutput("Module is SSTL_2_5V\n"); - break; - case 0x5: - if (dimmInfo.memoryType != MEM_TYPE_SDRAM) - { - mvOsOutput("Module is SSTL_1_8V\n"); - break; - } - default: - mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*----------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - rightOfPoint = (spdRawData[i] & 0x0f) * 10; - - /* DDR2 addition of right of point */ - if ((spdRawData[i] & 0x0f) == 0xA) - { - rightOfPoint = 25; - } - if ((spdRawData[i] & 0x0f) == 0xB) - { - rightOfPoint = 33; - } - if ((spdRawData[i] & 0x0f) == 0xC) - { - rightOfPoint = 66; - } - if ((spdRawData[i] & 0x0f) == 0xD) - { - rightOfPoint = 75; - } - mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - mvOsOutput("Clock To Data Out: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 11: /* Error Check Type */ - mvOsOutput("Error Check Type (0=NONE): %d\n", - dimmInfo.errorCheckType); - break; -/*----------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - mvOsOutput("Refresh Rate: %x\n", - dimmInfo.refreshInterval); - break; -/*----------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - mvOsOutput("Sdram Width: %d bits\n", - dimmInfo.sdramWidth); - break; -/*----------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - mvOsOutput("Error Check Data Width: %d bits\n", - dimmInfo.errorCheckDataWidth); - break; -/*----------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay is unsupported */ - if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || - (dimmInfo.memoryType == MEM_TYPE_DDR1)) - { - mvOsOutput("Minimum Clk Delay back to back: %d\n", - spdRawData[i]); - } - break; -/*----------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /* SDRAM/DDR1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * - *********************************************************/ - /* DDR2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * - *********************************************************/ - mvOsOutput("Burst Length Supported: "); - if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || - (dimmInfo.memoryType == MEM_TYPE_DDR1)) - { - if (dimmInfo.burstLengthSupported & BIT0) - mvOsOutput("1, "); - if (dimmInfo.burstLengthSupported & BIT1) - mvOsOutput("2, "); - } - if (dimmInfo.burstLengthSupported & BIT2) - mvOsOutput("4, "); - if (dimmInfo.burstLengthSupported & BIT3) - mvOsOutput("8, "); - - mvOsOutput(" Bit \n"); - break; -/*----------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - mvOsOutput("Number Of Banks On Each Chip: %d\n", - dimmInfo.numOfBanksOnEachDevice); - break; -/*----------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - - /* DDR 1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - *********************************************************/ - - /* DDR 2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * - *********************************************************/ - - mvOsOutput("Suported Cas Latencies: (CL) "); - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - for (k = 0; k <=7; k++) - { - if (dimmInfo.suportedCasLatencies & (1 << k)) - mvOsOutput("%d, ", k+1); - } - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if (dimmInfo.suportedCasLatencies & BIT0) - mvOsOutput("1, "); - if (dimmInfo.suportedCasLatencies & BIT1) - mvOsOutput("1.5, "); - if (dimmInfo.suportedCasLatencies & BIT2) - mvOsOutput("2, "); - if (dimmInfo.suportedCasLatencies & BIT3) - mvOsOutput("2.5, "); - if (dimmInfo.suportedCasLatencies & BIT4) - mvOsOutput("3, "); - if (dimmInfo.suportedCasLatencies & BIT5) - mvOsOutput("3.5, "); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR2) - { - if (dimmInfo.suportedCasLatencies & BIT2) - mvOsOutput("2, "); - if (dimmInfo.suportedCasLatencies & BIT3) - mvOsOutput("3, "); - if (dimmInfo.suportedCasLatencies & BIT4) - mvOsOutput("4, "); - if (dimmInfo.suportedCasLatencies & BIT5) - mvOsOutput("5, "); - } - else - mvOsOutput("?.?, "); - mvOsOutput("\n"); - break; -/*----------------------------------------------------------------------------*/ - - case 20: /* DDR2 DIMM type info */ - if (dimmInfo.memoryType == MEM_TYPE_DDR2) - { - if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) - mvOsOutput("Registered DIMM (RDIMM)\n"); - else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) - mvOsOutput("Unbuffered DIMM (UDIMM)\n"); - else - mvOsOutput("Unknown DIMM type.\n"); - } - - break; -/*----------------------------------------------------------------------------*/ - - case 21: /* SDRAM Modules Attributes */ - mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); - - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - if (dimmInfo.dimmAttributes & BIT0) - mvOsOutput(" Buffered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Buffered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT1) - mvOsOutput(" Registered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Registered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT2) - mvOsOutput(" On-Card PLL (clock): Yes \n"); - else - mvOsOutput(" On-Card PLL (clock): No \n"); - - if (dimmInfo.dimmAttributes & BIT3) - mvOsOutput(" Bufferd DQMB Input: Yes \n"); - else - mvOsOutput(" Bufferd DQMB Inputs: No \n"); - - if (dimmInfo.dimmAttributes & BIT4) - mvOsOutput(" Registered DQMB Inputs: Yes \n"); - else - mvOsOutput(" Registered DQMB Inputs: No \n"); - - if (dimmInfo.dimmAttributes & BIT5) - mvOsOutput(" Differential Clock Input: Yes \n"); - else - mvOsOutput(" Differential Clock Input: No \n"); - - if (dimmInfo.dimmAttributes & BIT6) - mvOsOutput(" redundant Row Addressing: Yes \n"); - else - mvOsOutput(" redundant Row Addressing: No \n"); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if (dimmInfo.dimmAttributes & BIT0) - mvOsOutput(" Buffered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Buffered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT1) - mvOsOutput(" Registered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Registered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT2) - mvOsOutput(" On-Card PLL (clock): Yes \n"); - else - mvOsOutput(" On-Card PLL (clock): No \n"); - - if (dimmInfo.dimmAttributes & BIT3) - mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); - else - mvOsOutput(" FET Switch On-Card Enabled: No \n"); - - if (dimmInfo.dimmAttributes & BIT4) - mvOsOutput(" FET Switch External Enabled: Yes \n"); - else - mvOsOutput(" FET Switch External Enabled: No \n"); - - if (dimmInfo.dimmAttributes & BIT5) - mvOsOutput(" Differential Clock Input: Yes \n"); - else - mvOsOutput(" Differential Clock Input: No \n"); - } - else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ - { - mvOsOutput(" Number of Active Registers on the DIMM: %d\n", - (dimmInfo.dimmAttributes & 0x3) + 1); - - mvOsOutput(" Number of PLLs on the DIMM: %d\n", - ((dimmInfo.dimmAttributes) >> 2) & 0x3); - - if (dimmInfo.dimmAttributes & BIT4) - mvOsOutput(" FET Switch External Enabled: Yes \n"); - else - mvOsOutput(" FET Switch External Enabled: No \n"); - - if (dimmInfo.dimmAttributes & BIT6) - mvOsOutput(" Analysis probe installed: Yes \n"); - else - mvOsOutput(" Analysis probe installed: No \n"); - } - - break; -/*----------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - if ( spdRawData[i] & BIT0 ) - mvOsOutput(" Early Ras Precharge: Yes \n"); - else - mvOsOutput(" Early Ras Precharge: No \n"); - - if ( spdRawData[i] & BIT1 ) - mvOsOutput(" AutoPreCharge: Yes \n"); - else - mvOsOutput(" AutoPreCharge: No \n"); - - if ( spdRawData[i] & BIT2 ) - mvOsOutput(" Precharge All: Yes \n"); - else - mvOsOutput(" Precharge All: No \n"); - - if ( spdRawData[i] & BIT3 ) - mvOsOutput(" Write 1/ReadBurst: Yes \n"); - else - mvOsOutput(" Write 1/ReadBurst: No \n"); - - if ( spdRawData[i] & BIT4 ) - mvOsOutput(" lower VCC tolerance: 5%%\n"); - else - mvOsOutput(" lower VCC tolerance: 10%%\n"); - - if ( spdRawData[i] & BIT5 ) - mvOsOutput(" upper VCC tolerance: 5%%\n"); - else - mvOsOutput(" upper VCC tolerance: 10%%\n"); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if ( spdRawData[i] & BIT0 ) - mvOsOutput(" Supports Weak Driver: Yes \n"); - else - mvOsOutput(" Supports Weak Driver: No \n"); - - if ( !(spdRawData[i] & BIT4) ) - mvOsOutput(" lower VCC tolerance: 0.2V\n"); - - if ( !(spdRawData[i] & BIT5) ) - mvOsOutput(" upper VCC tolerance: 0.2V\n"); - - if ( spdRawData[i] & BIT6 ) - mvOsOutput(" Concurrent Auto Preharge: Yes \n"); - else - mvOsOutput(" Concurrent Auto Preharge: No \n"); - - if ( spdRawData[i] & BIT7 ) - mvOsOutput(" Supports Fast AP: Yes \n"); - else - mvOsOutput(" Supports Fast AP: No \n"); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR2) - { - if ( spdRawData[i] & BIT0 ) - mvOsOutput(" Supports Weak Driver: Yes \n"); - else - mvOsOutput(" Supports Weak Driver: No \n"); - } - break; -/*----------------------------------------------------------------------------*/ - - case 23: - /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - rightOfPoint = (spdRawData[i] & 0x0f) * 10; - - /* DDR2 addition of right of point */ - if ((spdRawData[i] & 0x0f) == 0xA) - { - rightOfPoint = 25; - } - if ((spdRawData[i] & 0x0f) == 0xB) - { - rightOfPoint = 33; - } - if ((spdRawData[i] & 0x0f) == 0xC) - { - rightOfPoint = 66; - } - if ((spdRawData[i] & 0x0f) == 0xD) - { - rightOfPoint = 75; - } - - mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" - "(0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint ); - break; -/*----------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ - div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 25: - /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - leftOfPoint = (spdRawData[i] & 0xfc) >> 2; - rightOfPoint = (spdRawData[i] & 0x3) * 25; - } - else /* DDR1 or DDR2 */ - { - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - rightOfPoint = (spdRawData[i] & 0x0f) * 10; - - /* DDR2 addition of right of point */ - if ((spdRawData[i] & 0x0f) == 0xA) - { - rightOfPoint = 25; - } - if ((spdRawData[i] & 0x0f) == 0xB) - { - rightOfPoint = 33; - } - if ((spdRawData[i] & 0x0f) == 0xC) - { - rightOfPoint = 66; - } - if ((spdRawData[i] & 0x0f) == 0xD) - { - rightOfPoint = 75; - } - } - mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" - "(0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint ); - break; -/*----------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - leftOfPoint = (spdRawData[i] & 0xfc) >> 2; - rightOfPoint = (spdRawData[i] & 0x3) * 25; - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = 0; - rightOfPoint = time_tmp; - } - mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", - leftOfPoint, rightOfPoint ); - break; -/*----------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; - maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0xff : 0xfc; - maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0x00 : 0x03; - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; - temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ - trp_clocks = (temp + (busClkPs-1)) / busClkPs; - mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " - "in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; - maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0xff : 0xfc; - maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0x00 : 0x03; - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; - temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ - trrd_clocks = (temp + (busClkPs-1)) / busClkPs; - mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " - "%d.%d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; - maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0xff : 0xfc; - maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0x00 : 0x03; - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; - temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ - trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; - mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " - "in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; - mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " - "in Clk cycles %d\n", spdRawData[i], tras_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); - - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - if (dimmInfo.dimmBankDensity & BIT0) - mvOsOutput("1GB, "); - if (dimmInfo.dimmBankDensity & BIT1) - mvOsOutput("8MB, "); - if (dimmInfo.dimmBankDensity & BIT2) - mvOsOutput("16MB, "); - if (dimmInfo.dimmBankDensity & BIT3) - mvOsOutput("32MB, "); - if (dimmInfo.dimmBankDensity & BIT4) - mvOsOutput("64MB, "); - if (dimmInfo.dimmBankDensity & BIT5) - mvOsOutput("128MB, "); - if (dimmInfo.dimmBankDensity & BIT6) - mvOsOutput("256MB, "); - if (dimmInfo.dimmBankDensity & BIT7) - mvOsOutput("512MB, "); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if (dimmInfo.dimmBankDensity & BIT0) - mvOsOutput("1GB, "); - if (dimmInfo.dimmBankDensity & BIT1) - mvOsOutput("2GB, "); - if (dimmInfo.dimmBankDensity & BIT2) - mvOsOutput("16MB, "); - if (dimmInfo.dimmBankDensity & BIT3) - mvOsOutput("32MB, "); - if (dimmInfo.dimmBankDensity & BIT4) - mvOsOutput("64MB, "); - if (dimmInfo.dimmBankDensity & BIT5) - mvOsOutput("128MB, "); - if (dimmInfo.dimmBankDensity & BIT6) - mvOsOutput("256MB, "); - if (dimmInfo.dimmBankDensity & BIT7) - mvOsOutput("512MB, "); - } - else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ - { - if (dimmInfo.dimmBankDensity & BIT0) - mvOsOutput("1GB, "); - if (dimmInfo.dimmBankDensity & BIT1) - mvOsOutput("2GB, "); - if (dimmInfo.dimmBankDensity & BIT2) - mvOsOutput("4GB, "); - if (dimmInfo.dimmBankDensity & BIT3) - mvOsOutput("8GB, "); - if (dimmInfo.dimmBankDensity & BIT4) - mvOsOutput("16GB, "); - if (dimmInfo.dimmBankDensity & BIT5) - mvOsOutput("128MB, "); - if (dimmInfo.dimmBankDensity & BIT6) - mvOsOutput("256MB, "); - if (dimmInfo.dimmBankDensity & BIT7) - mvOsOutput("512MB, "); - } - mvOsOutput("\n"); - break; -/*----------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 36: /* Relevant for DDR2 only: Write Recovery Time */ - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); - rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; - mvOsOutput("Write Recovery Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - } - -} - - -/* - * translate ns.ns/10 coding of SPD timing values - * into ps unit values - */ -/******************************************************************************* -* cas2ps - Translate x.y ns parameter to pico-seconds values -* -* DESCRIPTION: -* This function translates x.y nano seconds to its value in pico seconds. -* For example 3.75ns will return 3750. -* -* INPUT: -* spd_byte - DIMM SPD byte. -* -* OUTPUT: -* None. -* -* RETURN: -* value in pico seconds. -* -*******************************************************************************/ -static MV_U32 cas2ps(MV_U8 spd_byte) -{ - MV_U32 ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - if( ns10 < 10 ) { - ns10 *= 10; - } - else if( ns10 == 10 ) - ns10 = 25; - else if( ns10 == 11 ) - ns10 = 33; - else if( ns10 == 12 ) - ns10 = 66; - else if( ns10 == 13 ) - ns10 = 75; - else - { - mvOsOutput("cas2ps Err. unsupported cycle time.\n"); - } - - return (ns*1000 + ns10*10); -} - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h deleted file mode 100644 index f95546624c..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h +++ /dev/null @@ -1,192 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCmvDram -#define __INCmvDram - -#include "ddr2/mvDramIf.h" -#include "twsi/mvTwsi.h" - -#define MAX_DIMM_NUM 2 -#define SPD_SIZE 128 - -/* Dimm spd offsets */ -#define DIMM_MEM_TYPE 2 -#define DIMM_ROW_NUM 3 -#define DIMM_COL_NUM 4 -#define DIMM_MODULE_BANK_NUM 5 -#define DIMM_DATA_WIDTH 6 -#define DIMM_VOLT_IF 8 -#define DIMM_MIN_CC_AT_MAX_CAS 9 -#define DIMM_ERR_CHECK_TYPE 11 -#define DIMM_REFRESH_INTERVAL 12 -#define DIMM_SDRAM_WIDTH 13 -#define DIMM_ERR_CHECK_DATA_WIDTH 14 -#define DIMM_MIN_CLK_DEL 15 -#define DIMM_BURST_LEN_SUP 16 -#define DIMM_DEV_BANK_NUM 17 -#define DIMM_SUP_CAL 18 -#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -#define DIMM_BUF_ADDR_CONT_IN 21 -#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -#define DIMM_MIN_RAS_PULSE_WIDTH 30 -#define DIMM_BANK_DENSITY 31 -#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -#define DIMM_SPD_VERSION 62 - -/* Dimm Memory Type values */ -#define DIMM_MEM_TYPE_SDRAM 0x4 -#define DIMM_MEM_TYPE_DDR1 0x7 -#define DIMM_MEM_TYPE_DDR2 0x8 - -#define DIMM_MODULE_MANU_OFFS 64 -#define DIMM_MODULE_MANU_SIZE 8 -#define DIMM_MODULE_VEN_OFFS 73 -#define DIMM_MODULE_VEN_SIZE 25 -#define DIMM_MODULE_ID_OFFS 99 -#define DIMM_MODULE_ID_SIZE 18 - -/* enumeration for voltage levels. */ -typedef enum _mvDimmVoltageIf -{ - TTL_5V_TOLERANT, - LVTTL, - HSTL_1_5V, - SSTL_3_3V, - SSTL_2_5V, - VOLTAGE_UNKNOWN, -} MV_DIMM_VOLTAGE_IF; - - -/* enumaration for SDRAM CAS Latencies. */ -typedef enum _mvDimmSdramCas -{ - SD_CL_1 =1, - SD_CL_2, - SD_CL_3, - SD_CL_4, - SD_CL_5, - SD_CL_6, - SD_CL_7, - SD_FAULT -}MV_DIMM_SDRAM_CAS; - - -/* DIMM information structure */ -typedef struct _mvDimmInfo -{ - MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ - - MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ - - /* DIMM dimensions */ - MV_U32 numOfRowAddr; - MV_U32 numOfColAddr; - MV_U32 numOfModuleBanks; - MV_U32 dataWidth; - MV_U32 errorCheckType; /* ECC , PARITY..*/ - MV_U32 sdramWidth; /* 4,8,16 or 32 */ - MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ - MV_U32 burstLengthSupported; - MV_U32 numOfBanksOnEachDevice; - MV_U32 suportedCasLatencies; - MV_U32 refreshInterval; - MV_U32 dimmBankDensity; - MV_U32 dimmTypeInfo; /* DDR2 only */ - MV_U32 dimmAttributes; - - /* DIMM timing parameters */ - MV_U32 minCycleTimeAtMaxCasLatPs; - MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; - MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; - MV_U32 minRowPrechargeTime; - MV_U32 minRowActiveToRowActive; - MV_U32 minRasToCasDelay; - MV_U32 minRasPulseWidth; - MV_U32 minWriteRecoveryTime; /* DDR2 only */ - MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ - MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ - MV_U32 minRefreshToActiveCmd; /* DDR2 only */ - - /* Parameters calculated from the extracted DIMM information */ - MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ - MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ - MV_U32 numberOfDevices; - -} MV_DIMM_INFO; - - -MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -MV_VOID dimmSpdPrint(MV_U32 dimmNum); -MV_STATUS dimmSpdCpy(MV_VOID); - -#endif /* __INCmvDram */ |