diff options
Diffstat (limited to 'target/linux/coldfire/files-2.6.31/arch/m68k/include/asm')
26 files changed, 0 insertions, 5731 deletions
diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/MCD_dma.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/MCD_dma.h deleted file mode 100644 index 700adf2754..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/MCD_dma.h +++ /dev/null @@ -1,432 +0,0 @@ -/********************************************************************* - * - * Copyright (C) 2004 Motorola, Inc. - * MOTOROLA, INC. All Rights Reserved. - * Copyright 2009 Freescale Semiconductor, Inc. - * Shrek Wu b16972@freescale.com - * - * You are hereby granted a copyright license to use - * the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Motorola, Inc. This - * software is provided on an "AS IS" basis and without warranty. - * - * To the maximum extent permitted by applicable law, MOTOROLA - * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING - * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE - * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY - * ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING - * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS - * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY - * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Motorola assumes no responsibility for the maintenance and support - * of this software - ********************************************************************/ - -/* - * File: MCD_dma.h - * Purpose: Main header file for multi-channel DMA API. - * - * Notes: - * - * Modifications: - */ -#ifndef _MCD_API_H -#define _MCD_API_H - -#include <asm/types.h> - -/* - * Turn Execution Unit tasks ON (#define) or OFF (#undef) - */ -#undef MCD_INCLUDE_EU - -/* - * Number of DMA channels - */ -#define NCHANNELS 16 - -/* - * Total number of variants - */ -#ifdef MCD_INCLUDE_EU -#define NUMOFVARIANTS 6 -#else -#define NUMOFVARIANTS 4 -#endif - -/* - * Define sizes of the various tables - */ -#define TASK_TABLE_SIZE (NCHANNELS*32) -#define VAR_TAB_SIZE (128) -#define CONTEXT_SAVE_SIZE (128) -#define FUNCDESC_TAB_SIZE (256) - -#ifdef MCD_INCLUDE_EU -#define FUNCDESC_TAB_NUM 16 -#else -#define FUNCDESC_TAB_NUM 1 -#endif - - -#ifndef DEFINESONLY - -/* - * Portability typedefs - */ - /* -#ifndef s32 -typedef int s32; -#endif -#ifndef u32 -typedef unsigned int u32; -#endif -#ifndef s16 -typedef short s16; -#endif -#ifndef u16 -typedef unsigned short u16; -#endif -#ifndef s8 -typedef char s8; -#endif -#ifndef u8 -typedef unsigned char u8; -#endif -*/ -/* - * These structures represent the internal registers of the - * multi-channel DMA - */ -struct dmaRegs_s { - u32 taskbar; /* task table base address register */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending register */ - u32 intMask; /* interrupt mask register */ - u16 taskControl[16]; /* task control registers */ - u8 priority[32]; /* priority registers */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control register 0. */ - u32 taskSize1; /* task size control register 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ -}; -typedef volatile struct dmaRegs_s dmaRegs; - -#endif - -/* - * PTD contrl reg bits - */ -#define PTD_CTL_TSK_PRI 0x8000 -#define PTD_CTL_COMM_PREFETCH 0x0001 - -/* - * Task Control reg bits and field masks - */ -#define TASK_CTL_EN 0x8000 -#define TASK_CTL_VALID 0x4000 -#define TASK_CTL_ALWAYS 0x2000 -#define TASK_CTL_INIT_MASK 0x1f00 -#define TASK_CTL_ASTRT 0x0080 -#define TASK_CTL_HIPRITSKEN 0x0040 -#define TASK_CTL_HLDINITNUM 0x0020 -#define TASK_CTL_ASTSKNUM_MASK 0x000f - -/* - * Priority reg bits and field masks - */ -#define PRIORITY_HLD 0x80 -#define PRIORITY_PRI_MASK 0x07 - -/* - * Debug Control reg bits and field masks - */ -#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 -#define DBG_CTL_AUTO_ARM 0x00008000 -#define DBG_CTL_BREAK 0x00004000 -#define DBG_CTL_COMP1_TYP_MASK 0x00003800 -#define DBG_CTL_COMP2_TYP_MASK 0x00000070 -#define DBG_CTL_EXT_BREAK 0x00000004 -#define DBG_CTL_INT_BREAK 0x00000002 - -/* - * PTD Debug reg selector addresses - * This reg must be written with a value to show the contents of - * one of the desired internal register. - */ -#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ -#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and - have initiators asserted */ - - -/* - * General return values - */ -#define MCD_OK 0 -#define MCD_ERROR -1 -#define MCD_TABLE_UNALIGNED -2 -#define MCD_CHANNEL_INVALID -3 - -/* - * MCD_initDma input flags - */ -#define MCD_RELOC_TASKS 0x00000001 -#define MCD_NO_RELOC_TASKS 0x00000000 -#define MCD_COMM_PREFETCH_EN 0x00000002 -/* Commbus Prefetching - MCF547x/548x ONLY */ - -/* - * MCD_dmaStatus Status Values for each channel - */ -#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ -#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ -#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ -#define MCD_PAUSED 4 /* DMA active but it is currently paused */ -#define MCD_HALTED 5 -/* the most recent DMA has been killed with MCD_killTask() */ -#define MCD_DONE 6 /* the most recent DMA has completed. */ - - -/* - * MCD_startDma parameter defines - */ - -/* - * Constants for the funcDesc parameter - */ -/* Byte swapping: */ -#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ -#define MCD_BYTE_REVERSE 0x00076540 -/* to reverse the bytes of each u32 of the DMAed data. */ -#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of - each 32-bit data value being DMAed.*/ -#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each - 16-bit half of each 32-bit data value DMAed */ -#define MCD_NO_BIT_REV 0x00000000 -/* do not reverse the bits of each byte DMAed. */ -#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ -/* CRCing: */ -#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ -#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ -#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ -#define MCD_CSUMINET 0xc0400000 -/* to perform internet checksums on DMAed data.*/ -#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ - -#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) -#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) - -/* - * Constants for the flags parameter - */ -#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ -#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ -#define MCD_TT_FLAGS_SP 0x00000004 -/* Speculative prefetch(XLB) MCF547x/548x ONLY */ -#define MCD_TT_FLAGS_MASK 0x000000ff -#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) - -#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ -#define MCD_CHAIN_DMA /* TBD */ -#define MCD_EU_DMA /* TBD */ -#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ -#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ - - -/* these flags are valid for MCD_startDma and the chained buffer descriptors */ -#define MCD_BUF_READY 0x80000000 -/* indicates that this buffer is now under the DMA's control */ -#define MCD_WRAP 0x20000000 -/* to tell the FEC Dmas to wrap to the first BD */ -#define MCD_INTERRUPT 0x10000000 -/* to generate an interrupt after completion of the DMA. */ -#define MCD_END_FRAME 0x08000000 -/* tell the DMA to end the frame when transferring - last byte of data in buffer */ -#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum - prior to performing the DMA. */ - -/* Defines for the FEC buffer descriptor control/status word*/ -#define MCD_FEC_BUF_READY 0x8000 -#define MCD_FEC_WRAP 0x2000 -#define MCD_FEC_INTERRUPT 0x1000 -#define MCD_FEC_END_FRAME 0x0800 - - -/* - * Defines for general intuitiveness - */ - -#define MCD_TRUE 1 -#define MCD_FALSE 0 - -/* - * Three different cases for destination and source. - */ -#define MINUS1 -1 -#define ZERO 0 -#define PLUS1 1 - -#ifndef DEFINESONLY - -/* Task Table Entry struct*/ -typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start and flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; -} TaskTableEntry; - - -/* Chained buffer descriptor */ -typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; -struct MCD_bufDesc_struct { - u32 flags; /* flags describing the DMA */ - u32 csumResult; - /* checksum from checksumming performed since last checksum reset */ - s8 *srcAddr; /* the address to move data from */ - s8 *destAddr; /* the address to move data to */ - s8 *lastDestAddr; /* the last address written to */ - u32 dmaSize; - /* the number of bytes to transfer independent of the transfer size */ - MCD_bufDesc *next; /* next buffer descriptor in chain */ - u32 info; - /* private information about this descriptor; DMA does not affect it */ -}; - -/* Progress Query struct */ -typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; - /* the most-recent or last, post-increment source address */ - s8 *lastDestAddr; - /* the most-recent or last, post-increment destination address */ - u32 dmaSize; - /* the amount of data transferred for the current buffer */ - MCD_bufDesc *currBufDesc; - /* pointer to the current buffer descriptor being DMAed */ -} MCD_XferProg; - - -/* FEC buffer descriptor */ -typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; -} MCD_bufDescFec; - - -/*************************************************************************/ -/* - * API function Prototypes - see MCD_dmaApi.c for further notes - */ - -/* - * MCD_startDma starts a particular kind of DMA . - */ -int MCD_startDma( - int channel, /* the channel on which to run the DMA */ - s8 *srcAddr, - /* the address to move data from, or buffer-descriptor address */ - s16 srcIncr, /* the amount to increment the source address per transfer */ - s8 *destAddr, /* the address to move data to */ - s16 destIncr, - /* the amount to increment the destination address per transfer */ - u32 dmaSize, - /* the number of bytes to transfer independent of the transfer size */ - u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ - u32 initiator, /* what device initiates the DMA */ - int priority, /* priority of the DMA */ - u32 flags, /* flags describing the DMA */ - u32 funcDesc -/* a description of byte swapping, bit swapping, and CRC actions */ -); - -/* - * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task structures, and - * setting up some global settings - */ -int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); - -/* - * MCD_dmaStatus() returns the status of the DMA on the requested channel. - */ -int MCD_dmaStatus(int channel); - -/* - * MCD_XferProgrQuery() returns progress of DMA on requested channel - */ -int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep); - -/* - * MCD_killDma() halts the DMA on the requested channel, without any - * intention of resuming the DMA. - */ -int MCD_killDma(int channel); - -/* - * MCD_continDma() continues a DMA which as stopped due to encountering an - * unready buffer descriptor. - */ -int MCD_continDma(int channel); - -/* - * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is - * running on that channel). - */ -int MCD_pauseDma(int channel); - -/* - * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is - * running on that channel). - */ -int MCD_resumeDma(int channel); - -/* - * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA - */ -int MCD_csumQuery(int channel, u32 *csum); - -/* - * MCD_getCodeSize provides the packed size required by the microcoded task - * and structures. - */ -int MCD_getCodeSize(void); - -/* - * MCD_getVersion provides a pointer to a version string and returns a - * version number. - */ -int MCD_getVersion(char **longVersion); - -/* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab, idx, value) ((u32 *)(taskTab)->varTab)[idx] = value - /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, - so I'm avoiding surrounding it with "do {} while(0)" */ - -#endif /* DEFINESONLY */ - -#endif /* _MCD_API_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/asm-offsets.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/asm-offsets.h deleted file mode 100644 index dffe187b7c..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/asm-offsets.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by Kbuild - * - */ - -#define TASK_STATE 0 /* offsetof(struct task_struct, state) | */ -#define TASK_FLAGS 12 /* offsetof(struct task_struct, flags) | */ -#define TASK_PTRACE 16 /* offsetof(struct task_struct, ptrace) | */ -#define TASK_THREAD 476 /* offsetof(struct task_struct, thread) | */ -#define TASK_INFO 638 /* offsetof(struct task_struct, thread.info) | */ -#define TASK_MM 178 /* offsetof(struct task_struct, mm) | */ -#define TASK_ACTIVE_MM 182 /* offsetof(struct task_struct, active_mm) | */ -#define THREAD_KSP 0 /* offsetof(struct thread_struct, ksp) | */ -#define THREAD_USP 4 /* offsetof(struct thread_struct, usp) | */ -#define THREAD_SR 8 /* offsetof(struct thread_struct, sr) | */ -#define THREAD_FS 10 /* offsetof(struct thread_struct, fs) | */ -#define THREAD_CRP 14 /* offsetof(struct thread_struct, crp) | */ -#define THREAD_ESP0 22 /* offsetof(struct thread_struct, esp0) | */ -#define THREAD_FPREG 38 /* offsetof(struct thread_struct, fp) | */ -#define THREAD_FPCNTL 134 /* offsetof(struct thread_struct, fpcntl) | */ -#define THREAD_FPSTATE 146 /* offsetof(struct thread_struct, fpstate) | */ -#define TINFO_PREEMPT 12 /* offsetof(struct thread_info, preempt_count) | */ -#define TINFO_FLAGS 4 /* offsetof(struct thread_info, flags) | */ -#define PT_D0 32 /* offsetof(struct pt_regs, d0) | */ -#define PT_ORIG_D0 36 /* offsetof(struct pt_regs, orig_d0) | */ -#define PT_D1 0 /* offsetof(struct pt_regs, d1) | */ -#define PT_D2 4 /* offsetof(struct pt_regs, d2) | */ -#define PT_D3 8 /* offsetof(struct pt_regs, d3) | */ -#define PT_D4 12 /* offsetof(struct pt_regs, d4) | */ -#define PT_D5 16 /* offsetof(struct pt_regs, d5) | */ -#define PT_A0 20 /* offsetof(struct pt_regs, a0) | */ -#define PT_A1 24 /* offsetof(struct pt_regs, a1) | */ -#define PT_A2 28 /* offsetof(struct pt_regs, a2) | */ -#define PT_PC 56 /* offsetof(struct pt_regs, pc) | */ -#define PT_SR 54 /* offsetof(struct pt_regs, sr) | */ -#define MM_CONTEXT 328 /* offsetof(struct mm_struct, context) | */ -#define PT_VECTOR 52 /* offsetof(struct pt_regs, pc) - 4 | */ -#define IRQ_HANDLER 0 /* offsetof(struct irq_node, handler) | */ -#define IRQ_DEVID 4 /* offsetof(struct irq_node, dev_id) | */ -#define IRQ_NEXT 8 /* offsetof(struct irq_node, next) | */ -#define STAT_IRQ 72 /* offsetof(struct kernel_stat, irqs) | */ -#define CPUSTAT_SOFTIRQ_PENDING 0 /* offsetof(irq_cpustat_t, __softirq_pending) | */ -#define BIR_TAG 0 /* offsetof(struct bi_record, tag) | */ -#define BIR_SIZE 2 /* offsetof(struct bi_record, size) | */ -#define BIR_DATA 4 /* offsetof(struct bi_record, data) | */ -#define FONT_DESC_IDX 0 /* offsetof(struct font_desc, idx) | */ -#define FONT_DESC_NAME 4 /* offsetof(struct font_desc, name) | */ -#define FONT_DESC_WIDTH 8 /* offsetof(struct font_desc, width) | */ -#define FONT_DESC_HEIGHT 12 /* offsetof(struct font_desc, height) | */ -#define FONT_DESC_DATA 16 /* offsetof(struct font_desc, data) | */ -#define FONT_DESC_PREF 20 /* offsetof(struct font_desc, pref) | */ -#define SIGSEGV 11 /* SIGSEGV | */ -#define SEGV_MAPERR 196609 /* SEGV_MAPERR | */ -#define SIGTRAP 5 /* SIGTRAP | */ -#define TRAP_TRACE 196610 /* TRAP_TRACE | */ -#define CUSTOMBASE -2132807680 /* &amiga_custom | */ -#define C_INTENAR 28 /* offsetof(struct CUSTOM, intenar) | */ -#define C_INTREQR 30 /* offsetof(struct CUSTOM, intreqr) | */ -#define C_INTENA 154 /* offsetof(struct CUSTOM, intena) | */ -#define C_INTREQ 156 /* offsetof(struct CUSTOM, intreq) | */ -#define C_SERDATR 24 /* offsetof(struct CUSTOM, serdatr) | */ -#define C_SERDAT 48 /* offsetof(struct CUSTOM, serdat) | */ -#define C_SERPER 50 /* offsetof(struct CUSTOM, serper) | */ -#define CIAABASE -2134908927 /* &ciaa | */ -#define CIABBASE -2134913024 /* &ciab | */ -#define C_PRA 0 /* offsetof(struct CIA, pra) | */ -#define ZTWOBASE -2147483648 /* zTwoBase | */ - -#endif diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_548x_cacheflush.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_548x_cacheflush.h deleted file mode 100644 index bc19dfc15c..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_548x_cacheflush.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * arch/m68k/include/asm/cf_548x_cacheflush.h - Coldfire 547x/548x Cache - * - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Kurt Mahan kmahan@freescale.com - * Shrek Wu b16972@freescale.com - * - * Based on include/asm-m68k/cacheflush.h - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef M68K_CF_548x_CACHEFLUSH_H -#define M68K_CF_548x_CACHEFLUSH_H - -#include <asm/cfcache.h> -/* - * Cache handling functions - */ - -#define flush_icache() \ -({ \ - unsigned long set; \ - unsigned long start_set; \ - unsigned long end_set; \ - \ - start_set = 0; \ - end_set = (unsigned long)LAST_DCACHE_ADDR; \ - \ - for (set = start_set; set <= end_set; set += (0x10 - 3)) {\ - asm volatile("cpushl %%ic,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%ic,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%ic,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \ - } \ -}) - -#define flush_dcache() \ -({ \ - unsigned long set; \ - unsigned long start_set; \ - unsigned long end_set; \ - \ - start_set = 0; \ - end_set = (unsigned long)LAST_DCACHE_ADDR; \ - \ - for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ - asm volatile("cpushl %%dc,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%dc,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%dc,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \ - } \ -}) - -#define flush_bcache() \ -({ \ - unsigned long set; \ - unsigned long start_set; \ - unsigned long end_set; \ - \ - start_set = 0; \ - end_set = (unsigned long)LAST_DCACHE_ADDR; \ - \ - for (set = start_set; set <= end_set; set += (0x10 - 3)) { \ - asm volatile("cpushl %%bc,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%bc,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%bc,(%0)\n" \ - "\taddq%.l #1,%0\n" \ - "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \ - } \ -}) - -/* - * invalidate the cache for the specified memory range. - * It starts at the physical address specified for - * the given number of bytes. - */ -extern void cache_clear(unsigned long paddr, int len); -/* - * push any dirty cache in the specified memory range. - * It starts at the physical address specified for - * the given number of bytes. - */ -extern void cache_push(unsigned long paddr, int len); - -/* - * push and invalidate pages in the specified user virtual - * memory range. - */ -extern void cache_push_v(unsigned long vaddr, int len); - -/* This is needed whenever the virtual mapping of the current - process changes. */ - -/** - * flush_cache_mm - Flush an mm_struct - * @mm: mm_struct to flush - */ -static inline void flush_cache_mm(struct mm_struct *mm) -{ - if (mm == current->mm) - flush_bcache(); -} - -#define flush_cache_dup_mm(mm) flush_cache_mm(mm) - -#define flush_cache_all() flush_bcache() - -/** - * flush_cache_range - Flush a cache range - * @vma: vma struct - * @start: Starting address - * @end: Ending address - * - * flush_cache_range must be a macro to avoid a dependency on - * linux/mm.h which includes this file. - */ -static inline void flush_cache_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - if (vma->vm_mm == current->mm) - flush_bcache(); -/*cf_cache_flush_range(start, end);*/ -} - -/** - * flush_cache_page - Flush a page of the cache - * @vma: vma struct - * @vmaddr: - * @pfn: page numer - * - * flush_cache_page must be a macro to avoid a dependency on - * linux/mm.h which includes this file. - */ -static inline void flush_cache_page(struct vm_area_struct *vma, - unsigned long vmaddr, unsigned long pfn) -{ - if (vma->vm_mm == current->mm) - flush_bcache(); -/*cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);*/ -} - -/* Push the page at kernel virtual address and clear the icache */ -/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ -#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page)) -extern inline void __flush_page_to_ram(void *address) -{ - unsigned long set; - unsigned long start_set; - unsigned long end_set; - unsigned long addr = (unsigned long) address; - - addr &= ~(PAGE_SIZE - 1); - /* round down to page start address */ - - start_set = addr & _ICACHE_SET_MASK; - end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK; - - if (start_set > end_set) { - /* from the begining to the lowest address */ - for (set = 0; set <= end_set; set += (0x10 - 3)) { - asm volatile("cpushl %%bc,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%bc,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%bc,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); - } - /* next loop will finish the cache ie pass the hole */ - end_set = LAST_ICACHE_ADDR; - } - - for (set = start_set; set <= end_set; set += (0x10 - 3)) { - asm volatile("cpushl %%bc,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%bc,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%bc,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); - } -} - -/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */ -#define flush_dcache_page(page) \ - __flush_page_to_ram((void *) page_address(page)) -#define flush_icache_page(vma, pg) \ - __flush_page_to_ram((void *) page_address(pg)) -#define flush_icache_user_range(adr, len) \ - do { } while (0) -/* NL */ -#define flush_icache_user_page(vma, page, addr, len) \ - do { } while (0) - -/* Push n pages at kernel virtual address and clear the icache */ -/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ -extern inline void flush_icache_range(unsigned long address, - unsigned long endaddr) -{ - unsigned long set; - unsigned long start_set; - unsigned long end_set; - - start_set = address & _ICACHE_SET_MASK; - end_set = endaddr & _ICACHE_SET_MASK; - - if (start_set > end_set) { - /* from the begining to the lowest address */ - for (set = 0; set <= end_set; set += (0x10 - 3)) { - asm volatile("cpushl %%ic,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%ic,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%ic,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); - } - /* next loop will finish the cache ie pass the hole */ - end_set = LAST_ICACHE_ADDR; - } - for (set = start_set; set <= end_set; set += (0x10 - 3)) { - asm volatile("cpushl %%ic,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%ic,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%ic,(%0)\n" - "\taddq%.l #1,%0\n" - "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); - } -} - -static inline void copy_to_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, - void *dst, void *src, int len) -{ - memcpy(dst, src, len); - flush_icache_user_page(vma, page, vaddr, len); -} -static inline void copy_from_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, - void *dst, void *src, int len) -{ - memcpy(dst, src, len); -} - -#define flush_cache_vmap(start, end) flush_cache_all() -#define flush_cache_vunmap(start, end) flush_cache_all() -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -#endif /* M68K_CF_548x_CACHEFLUSH_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_bitops.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_bitops.h deleted file mode 100644 index 6f9e9c0990..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_bitops.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef __CF_BITOPS__ -#define __CF_BITOPS__ - -#ifndef _LINUX_BITOPS_H -#error only <linux/bitops.h> can be included directly -#endif - -#include <linux/compiler.h> - -#define test_and_set_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_coldfire_test_and_set_bit(nr, vaddr) : \ - __generic_coldfire_test_and_set_bit(nr, vaddr)) - -static __inline__ int __constant_coldfire_test_and_set_bit(int nr, - volatile void *vaddr) -{ - char retval; - volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; - __asm__ __volatile__ ("bset %2,(%4); sne %0" - : "=d" (retval), "=m" (*p) - : "di" (nr & 7), "m" (*p), "a" (p)); - return retval; -} - -static __inline__ int __generic_coldfire_test_and_set_bit(int nr, - volatile void *vaddr) -{ - char retval; - - __asm__ __volatile__ ("bset %2,%1; sne %0" - : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) - : "d" (nr) - : "memory"); - return retval; -} -#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr) - -#define set_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_coldfire_set_bit(nr, vaddr) : \ - __generic_coldfire_set_bit(nr, vaddr)) - -static __inline__ void __constant_coldfire_set_bit(int nr, - volatile void *vaddr) -{ - volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; - __asm__ __volatile__ ("bset %1,(%3)" - : "=m" (*p) : "di" (nr & 7), "m" (*p), "a" (p)); -} - -static __inline__ void __generic_coldfire_set_bit(int nr, - volatile void *vaddr) -{ - __asm__ __volatile__ ("bset %1,%0" - : "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) - : "d" (nr) - : "memory"); -} -#define __set_bit(nr, vaddr) set_bit(nr, vaddr) - -#define test_and_clear_bit(nr, vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_coldfire_test_and_clear_bit(nr, vaddr) : \ - __generic_coldfire_test_and_clear_bit(nr, vaddr)) - -static __inline__ int __constant_coldfire_test_and_clear_bit(int nr, - volatile void *vaddr) -{ - char retval; - volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; - - __asm__ __volatile__ ("bclr %2,(%4); sne %0" - : "=d" (retval), "=m" (*p) - : "id" (nr & 7), "m" (*p), "a" (p)); - - return retval; -} - -static __inline__ int __generic_coldfire_test_and_clear_bit(int nr, - volatile void *vaddr) -{ - char retval; - - __asm__ __volatile__ ("bclr %2,%1; sne %0" - : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) - : "d" (nr & 7) - : "memory"); - - return retval; -} -#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr) - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -#define clear_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_coldfire_clear_bit(nr, vaddr) : \ - __generic_coldfire_clear_bit(nr, vaddr)) - -static __inline__ void __constant_coldfire_clear_bit(int nr, - volatile void *vaddr) -{ - volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; - __asm__ __volatile__ ("bclr %1,(%3)" - : "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p)); -} - -static __inline__ void __generic_coldfire_clear_bit(int nr, - volatile void *vaddr) -{ - __asm__ __volatile__ ("bclr %1,%0" - : "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) - : "d" (nr) - : "memory"); -} -#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr) - -#define test_and_change_bit(nr, vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_coldfire_test_and_change_bit(nr, vaddr) : \ - __generic_coldfire_test_and_change_bit(nr, vaddr)) - -static __inline__ int __constant_coldfire_test_and_change_bit(int nr, - volatile void *vaddr) -{ - char retval; - volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; - - __asm__ __volatile__ ("bchg %2,(%4); sne %0" - : "=d" (retval), "=m" (*p) - : "id" (nr & 7), "m" (*p), "a" (p)); - - return retval; -} - -static __inline__ int __generic_coldfire_test_and_change_bit(int nr, - volatile void *vaddr) -{ - char retval; - - __asm__ __volatile__ ("bchg %2,%1; sne %0" - : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) - : "id" (nr) - : "memory"); - - return retval; -} -#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr) -#define __change_bit(nr, vaddr) change_bit(nr, vaddr) - -#define change_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_coldfire_change_bit(nr, vaddr) : \ - __generic_coldfire_change_bit(nr, vaddr)) - -static __inline__ void __constant_coldfire_change_bit(int nr, - volatile void *vaddr) -{ - volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; - __asm__ __volatile__ ("bchg %1,(%3)" - : "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p)); -} - -static __inline__ void __generic_coldfire_change_bit(int nr, - volatile void *vaddr) -{ - __asm__ __volatile__ ("bchg %1,%0" - : "=m" (((volatile char *)vaddr)[(nr^31) >> 3]) - : "d" (nr) - : "memory"); -} - -static inline int test_bit(int nr, const unsigned long *vaddr) -{ - return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0; -} - -static __inline__ unsigned long ffz(unsigned long word) -{ - unsigned long result = 0; - - while (word & 1) { - result++; - word >>= 1; - } - return result; -} - -/* find_next_zero_bit() finds the first zero bit in a bit string of length - * 'size' bits, starting the search at bit 'offset'. This is largely based - * on Linus's ALPHA routines. - */ -static __inline__ unsigned long find_next_zero_bit(void *addr, - unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - tmp = *(p++); - if (~tmp) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp |= ~0UL >> size; -found_middle: - return result + ffz(tmp); -} - -#define find_first_zero_bit(addr, size) find_next_zero_bit(((void *)addr), \ - (size), 0) - -/* Ported from included/linux/bitops.h */ -static __inline__ int ffs(int x) -{ - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; -} -#define __ffs(x) (ffs(x) - 1) - -/* find_next_bit - find the next set bit in a memory region - * (from asm-ppc/bitops.h) - */ -static __inline__ unsigned long find_next_bit(const unsigned long *addr, - unsigned long size, unsigned long offset) -{ - unsigned int *p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31UL; - unsigned int tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *p++; - tmp &= ~0UL << offset; - if (size < 32) - goto found_first; - if (tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - tmp = *p++; - if (tmp != 0) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp &= ~0UL >> (32 - size); - if (tmp == 0UL) /* Are any bits set? */ - return result + size; /* Nope. */ -found_middle: - return result + __ffs(tmp); -} - -#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) - -#ifdef __KERNEL__ - -/* Ported from include/linux/bitops.h */ -static __inline__ int fls(int x) -{ - int r = 32; - - if (!x) - return 0; - if (!(x & 0xffff0000u)) { - x <<= 16; - r -= 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r -= 1; - } - return r; -} - -static inline int __fls(int x) -{ - return fls(x) - 1; -} - -#include <asm-generic/bitops/fls64.h> -#include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/hweight.h> -#include <asm-generic/bitops/lock.h> - -#define minix_find_first_zero_bit(addr, size) find_next_zero_bit((addr), \ - (size), 0) -#define minix_test_and_set_bit(nr, addr) test_and_set_bit((nr), \ - (unsigned long *)(addr)) -#define minix_set_bit(nr, addr) set_bit((nr), \ - (unsigned long *)(addr)) -#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit((nr), \ - (unsigned long *)(addr)) - -static inline int minix_test_bit(int nr, const volatile unsigned long *vaddr) -{ - int *a = (int *)vaddr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 24, \ - (unsigned long *)(addr)) -#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, \ - (unsigned long *)(addr)) -#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 24, \ - (unsigned long *)(addr)) -#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, \ - (unsigned long *)(addr)) - -static inline int ext2_test_bit(int nr, const void *vaddr) -{ - const unsigned char *p = vaddr; - return (p[nr >> 3] & (1U << (nr & 7))) != 0; -} - -static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) -{ - const unsigned long *p = vaddr, *addr = vaddr; - int res; - - if (!size) - return 0; - - size = (size >> 5) + ((size & 31) > 0); - while (*p++ == ~0UL) { - if (--size == 0) - return (p - addr) << 5; - } - - --p; - for (res = 0; res < 32; res++) - if (!ext2_test_bit (res, p)) - break; - return (p - addr) * 32 + res; -} - -static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size, - unsigned offset) -{ - const unsigned long *addr = vaddr; - const unsigned long *p = addr + (offset >> 5); - int bit = offset & 31UL, res; - - if (offset >= size) - return size; - - if (bit) { - /* Look for zero in first longword */ - for (res = bit; res < 32; res++) - if (!ext2_test_bit (res, p)) - return (p - addr) * 32 + res; - p++; - } - /* No zero yet, search remaining full bytes for a zero */ - res = ext2_find_first_zero_bit(p, size - 32 * (p - addr)); - return (p - addr) * 32 + res; -} - -#endif /* KERNEL */ - -#endif /* __CF_BITOPS__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_cacheflush.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_cacheflush.h deleted file mode 100644 index 49c5c4cca7..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_cacheflush.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef M68K_CF_CACHEFLUSH_H -#define M68K_CF_CACHEFLUSH_H - -#ifdef CONFIG_M5445X -#include "cf_5445x_cacheflush.h" -#else -#include "cf_548x_cacheflush.h" -#endif - -#endif /* M68K_CF_CACHEFLUSH_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_entry.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_entry.h deleted file mode 100644 index c8f37a4105..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_entry.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef __CF_M68K_ENTRY_H -#define __CF_M68K_ENTRY_H - -#include <asm/setup.h> -#include <asm/page.h> -#include <asm/coldfire.h> -#include <asm/cfmmu.h> -#include <asm/asm-offsets.h> - -/* - * Stack layout in 'ret_from_exception': - * - * This allows access to the syscall arguments in registers d1-d5 - * - * 0(sp) - d1 - * 4(sp) - d2 - * 8(sp) - d3 - * C(sp) - d4 - * 10(sp) - d5 - * 14(sp) - a0 - * 18(sp) - a1 - * 1C(sp) - a2 - * 20(sp) - d0 - * 24(sp) - orig_d0 - * 28(sp) - stack adjustment - * 2C(sp) - sr - * 2E(sp) - pc - * 32(sp) - format & vector - * 36(sp) - MMUSR - * 3A(sp) - MMUAR - */ - -/* - * 97/05/14 Andreas: Register %a2 is now set to the current task throughout - * the whole kernel. - */ - -/* the following macro is used when enabling interrupts */ -/* portable version */ -#define ALLOWINT (~0x700) -#define MAX_NOINT_IPL 0 - -#ifdef __ASSEMBLY__ - -#define curptr a2 - -LFLUSH_I_AND_D = 0x00000808 -LSIGTRAP = 5 - -/* process bits for task_struct.ptrace */ -PT_TRACESYS_OFF = 3 -PT_TRACESYS_BIT = 1 -PT_PTRACED_OFF = 3 -PT_PTRACED_BIT = 0 -PT_DTRACE_OFF = 3 -PT_DTRACE_BIT = 2 - -#define SAVE_ALL_INT save_all_int -#define SAVE_ALL_SYS save_all_sys -#define RESTORE_ALL restore_all -/* - * This defines the normal kernel pt-regs layout. - * - * regs a3-a6 and d6-d7 are preserved by C code - * the kernel doesn't mess with usp unless it needs to - */ - -/* - * a -1 in the orig_d0 field signifies - * that the stack frame is NOT for syscall - */ -.macro save_all_int - movel MMUSR,%sp@- - movel MMUAR,%sp@- - clrl %sp@- | stk_adj - pea -1:w | orig d0 - movel %d0,%sp@- | d0 - subal #(8*4), %sp - moveml %d1-%d5/%a0-%a1/%curptr,%sp@ -.endm - -.macro save_all_sys - movel MMUSR,%sp@- - movel MMUAR,%sp@- - clrl %sp@- | stk_adj - movel %d0,%sp@- | orig d0 - movel %d0,%sp@- | d0 - subal #(8*4), %sp - moveml %d1-%d5/%a0-%a1/%curptr,%sp@ -.endm - -.macro restore_all - moveml %sp@,%a0-%a1/%curptr/%d1-%d5 - addal #(8*4), %sp - movel %sp@+,%d0 | d0 - addql #4,%sp | orig d0 - addl %sp@+,%sp | stk_adj - addql #8,%sp | MMUAR & MMUSR - rte -.endm - -#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */ - -#define SAVE_SWITCH_STACK save_switch_stack -#define RESTORE_SWITCH_STACK restore_switch_stack -#define GET_CURRENT(tmp) get_current tmp - -.macro save_switch_stack - subal #(6*4), %sp - moveml %a3-%a6/%d6-%d7,%sp@ -.endm - -.macro restore_switch_stack - moveml %sp@,%a3-%a6/%d6-%d7 - addal #(6*4), %sp -.endm - -.macro get_current reg=%d0 - movel %sp,\reg - andl #-THREAD_SIZE,\reg - movel \reg,%curptr - movel %curptr@,%curptr -.endm - -#else /* C source */ - -#define STR(X) STR1(X) -#define STR1(X) #X - -#define PT_OFF_ORIG_D0 0x24 -#define PT_OFF_FORMATVEC 0x32 -#define PT_OFF_SR 0x2C -#define SAVE_ALL_INT \ - "clrl %%sp@-;" /* stk_adj */ \ - "pea -1:w;" /* orig d0 = -1 */ \ - "movel %%d0,%%sp@-;" /* d0 */ \ - "subal #(8*4),%sp" \ - "moveml %%d1-%%d5/%%a0-%%a2,%%sp@" -#define GET_CURRENT(tmp) \ - "movel %%sp,"#tmp"\n\t" \ - "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \ - "movel "#tmp",%%a2\n\t" - -#endif - -#endif /* __CF_M68K_ENTRY_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_io.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_io.h deleted file mode 100644 index b2c7a46481..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_io.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * linux/include/asm-m68k/cf_io.h - * - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * 9/30/08 JKM - Separated Coldfire pieces out from m68k. - */ - -#ifndef __CF_IO__ -#define __CF_IO__ - -#ifdef __KERNEL__ - -#include <linux/compiler.h> -#include <asm/raw_io.h> -#include <asm/virtconvert.h> - -#include <asm-generic/iomap.h> - -/* - * These should be valid on any ioremap()ed region - */ -#define readb(addr) in_8(addr) -#define writeb(val,addr) out_8((addr),(val)) -#define readw(addr) in_le16(addr) -#define writew(val,addr) out_le16((addr),(val)) -#define readl(addr) in_le32(addr) -#define writel(val,addr) out_le32((addr),(val)) - -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) - -#ifdef CONFIG_PCI - -/* - * IO space in Coldfire - */ -/*#define HAVE_ARCH_PIO_SIZE 1 -#define PIO_OFFSET 0x00000000UL -#define PIO_RESERVED 0x100000000UL -#define PIO_MASK (PIO_RESERVED - 1) -*/ -#define inb_p inb -#define inw_p inw -#define inl_p inl -#define outb_p outb -#define outw_p outw -#define outl_p outl - -#ifndef CONFIG_COLDFIRE -#define inb(port) in_8(port) -#define outb(val,port) out_8((port),(val)) -#define inw(port) in_le16(port) -#define outw(val,port) out_le16((port),(val)) -#define inl(port) in_le32(port) -#define outl(val,port) out_le32((port),(val)) -#define insb(port, buf, nr) \ - raw_insb((u8 *)(port), (u8 *)(buf), (nr)) -#define outsb(port, buf, nr) \ - raw_outsb((u8 *)(port), (u8 *)(buf), (nr)) -#define insw(port, buf, nr) \ - raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)) -#define outsw(port, buf, nr) \ - raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)) -#define insl(port, buf, nr) \ - raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) -#define outsl(port, buf, nr) \ - raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) -#else -#define inb(port) pci_inb(port) -#define outb(val, port) pci_outb((val), (port)) -#define inw(port) pci_inw(port) -#define outw(val, port) pci_outw((val), (port)) -#define insb(a, b, c) \ - pci_insb((volatile unsigned char *)a, (unsigned char *)b, c) -#define insw(a, b, c) \ - pci_insw((volatile unsigned short *)a, (const unsigned short *)b, c) -#define insl(a, b, c) \ - pci_insl((volatile unsigned long *)a, (const unsigned long *)b, c) -#define outsb(a, b, c) \ - pci_outsb((volatile unsigned char *)a, (const unsigned char *)b, c) -#define outsw(a, b, c) \ - pci_outsw((volatile unsigned short *)a, (const unsigned short *)b, c) -#define outsl(a, b, c) \ - pci_outsl((volatile unsigned long *)a, (const unsigned long *)b, c) -#define inl(port) pci_inl(port) -#define outl(val, port) pci_outl((val), (port)) -#endif - -#else -/* no pci */ - -#define inb(port) in_8(port) -#define outb(val, port) out_8((port), (val)) -#define inw(port) in_le16(port) -#define outw(val, port) out_le16((port), (val)) -#define inl(port) in_le32(port) -#define outl(val, port) out_le32((port), (val)) -#define insb(port, buf, nr) \ - raw_insb((u8 *)(port), (u8 *)(buf), (nr)) -#define outsb(port, buf, nr) \ - raw_outsb((u8 *)(port), (u8 *)(buf), (nr)) -#define insw(port, buf, nr) \ - raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)) -#define outsw(port, buf, nr) \ - raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)) -#define insl(port, buf, nr) \ - raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) -#define outsl(port, buf, nr) \ - raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1) - -#endif /* CONFIG_PCI */ - -#define mmiowb() - -static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -static inline void __iomem *ioremap_writethrough(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); -} -static inline void __iomem *ioremap_fullcache(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_FULL_CACHING); -} - -static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) -{ - __builtin_memset((void __force *) addr, val, count); -} -static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) -{ - __builtin_memcpy(dst, (void __force *) src, count); -} -static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) -{ - __builtin_memcpy((void __force *) dst, src, count); -} - -#define IO_SPACE_LIMIT 0xffffffff - -#endif /* __KERNEL__ */ - -#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1 - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#define __raw_readb(addr) \ - ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) -#define __raw_readw(addr) \ - ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) -#define __raw_readl(addr) \ - ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; }) -#define __raw_writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define __raw_writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define __raw_writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) - -#define memset_io(a, b, c) memset((void *)(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) -#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) - -#if !defined(readb) -#define readb(addr) \ - ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) -#define readw(addr) \ - ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) -#define readl(addr) \ - ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) -#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) -#endif /* readb */ - -#endif /* _IO_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_page.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_page.h deleted file mode 100644 index 1421f49437..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_page.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * linux/include/asm-m68k/cf_page.h - * - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Based on linux/include/asm-m68k/page.h - * - * 10/09/08 JKM: split Coldfire pieces into separate file - */ -#ifndef __CF_PAGE__ -#define __CF_PAGE__ - -#include <linux/const.h> -#include <asm/setup.h> -#include <asm/page_offset.h> - -/* Virtual base page location */ -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT (13) /* 8K pages */ -#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#define THREAD_SIZE PAGE_SIZE - -#ifndef __ASSEMBLY__ -#include <linux/compiler.h> -#include <asm/module.h> - -#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -#define free_user_page(page, addr) free_page(addr) - -#define clear_page(page) memset((page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(addr, vaddr, page) \ - do { clear_page(addr); \ - flush_dcache_page(page); \ - } while (0) - -#define copy_user_page(to, from, vaddr, page) \ - do { copy_page(to, from); \ - flush_dcache_page(page); \ - } while (0) - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd[16]; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* to align the pointer to the (next) page boundary */ -/*Defined in linux/mm.h*/ -/*#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)*/ - -extern unsigned long m68k_memoffset; - -#define WANT_PAGE_VIRTUAL - -extern unsigned long cf_dma_base; -extern unsigned long cf_dma_end; - -/* - * Convert a virt to a phys - */ -static inline unsigned long ___pa(void *vaddr) -{ -#if CONFIG_SDRAM_BASE != PAGE_OFFSET - return (((unsigned long)vaddr & 0x0fffffff) + CONFIG_SDRAM_BASE); -#else - if ((unsigned long)vaddr >= CONFIG_DMA_BASE && - (unsigned long)vaddr < (CONFIG_DMA_BASE + CONFIG_DMA_SIZE)) { - /* address is in carved out DMA range */ - return ((unsigned long)vaddr - CONFIG_DMA_BASE) + CONFIG_SDRAM_BASE; - } - else if ((unsigned long)vaddr >= PAGE_OFFSET && - (unsigned long)vaddr < (PAGE_OFFSET + CONFIG_SDRAM_SIZE)) { - /* normal mapping */ - return ((unsigned long)vaddr - PAGE_OFFSET) + CONFIG_SDRAM_BASE; - } - - return (unsigned long)vaddr; -#endif -} -#define __pa(vaddr) ___pa((void *)(vaddr)) - -/* - * Convert a phys to a virt - */ -static inline void *__va(unsigned long paddr) -{ -#if CONFIG_SDRAM_BASE != PAGE_OFFSET - return (void *)((paddr & 0x0fffffff) + PAGE_OFFSET); -#else - if (paddr >= cf_dma_base && paddr <= cf_dma_end) { - /* mapped address for DMA */ - return (void *)((paddr - CONFIG_SDRAM_BASE) + CONFIG_DMA_BASE); - } - else if (paddr >= cf_dma_end && - paddr < (CONFIG_SDRAM_BASE + CONFIG_SDRAM_SIZE)) { - /* normal mapping */ - return (void *)((paddr - CONFIG_SDRAM_BASE) + PAGE_OFFSET); - } - return (void *)paddr; -#endif -} - -/* - * NOTE: virtual isn't really correct, actually it should be the offset into the - * memory node, but we have no highmem, so that works for now. - * - * TODO: implement (fast) pfn<->pgdat_idx conversion functions, this makes lots - * of the shifts unnecessary. - * - * PFNs are used to map physical pages. So PFN[0] maps to the base phys addr. - */ -#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) -#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) - -extern int m68k_virt_to_node_shift; - -#ifdef CONFIG_SINGLE_MEMORY_CHUNK -#define __virt_to_node(addr) (&pg_data_map[0]) -#else -extern struct pglist_data *pg_data_table[]; - -static inline __attribute_const__ int __virt_to_node_shift(void) -{ - return m68k_virt_to_node_shift; -} - -#define __virt_to_node(addr) (pg_data_table[(unsigned long)(addr) >> __virt_to_node_shift()]) -#endif /* !CONFIG_SINGLE_MEMORY_CHUNK */ - -#define virt_to_page(addr) ({ \ - pfn_to_page(virt_to_pfn(addr)); \ -}) -#define page_to_virt(page) ({ \ - pfn_to_virt(page_to_pfn(page)); \ -}) - -#define pfn_to_page(pfn) ({ \ - unsigned long __pfn = (pfn); \ - struct pglist_data *pgdat; \ - pgdat = __virt_to_node((unsigned long)pfn_to_virt(__pfn)); \ - pgdat->node_mem_map + (__pfn - pgdat->node_start_pfn); \ -}) -#define page_to_pfn(_page) ({ \ - struct page *__p = (_page); \ - struct pglist_data *pgdat; \ - pgdat = &pg_data_map[page_to_nid(__p)]; \ - ((__p) - pgdat->node_mem_map) + pgdat->node_start_pfn; \ -}) - -#define virt_addr_valid(kaddr) ( ((void *)(kaddr) >= (void *)PAGE_OFFSET && \ - (void *)(kaddr) < high_memory) || \ - ((void *)(kaddr) >= (void*)CONFIG_DMA_BASE && \ - (void *)(kaddr) < (void*)(CONFIG_DMA_BASE+CONFIG_DMA_SIZE))) - -#define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn)) - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#include <asm-generic/getorder.h> - -#ifdef CONFIG_VDSO -#define __HAVE_ARCH_GATE_AREA -#endif - -#endif /* __CF_PAGE__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_pgalloc.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_pgalloc.h deleted file mode 100644 index de3916762a..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_pgalloc.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef M68K_CF_PGALLOC_H -#define M68K_CF_PGALLOC_H -#include <linux/highmem.h> -#include <asm/coldfire.h> -#include <asm/page.h> -#include <asm/cf_tlbflush.h> -#include <asm/cf_cacheflush.h> - -extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_page((unsigned long) pte); -} - -extern const char bad_pmd_string[]; - -extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, - unsigned long address) -{ - unsigned long page = __get_free_page(GFP_KERNEL|__GFP_REPEAT); - - if (!page) - return NULL; - - memset((void *)page, 0, PAGE_SIZE); - return (pte_t *) (page); -} - -extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address) -{ - return (pmd_t *) pgd; -} - -#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); }) -#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); }) - -#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr) - -#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \ - (unsigned long)(page_address(page))) - -#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte)) - -#define pmd_pgtable(pmd) pmd_page(pmd) - -static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page, unsigned long address) -{ - __free_page(page); -} - -#define __pmd_free_tlb(tlb, pmd, addr) do { } while (0) - -static inline struct page *pte_alloc_one(struct mm_struct *mm, - unsigned long address) -{ - struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0); - pte_t *pte; - - if (!page) - return NULL; - - pte = kmap(page); -// if (pte) { - clear_page(pte); - __flush_page_to_ram(pte); - flush_tlb_kernel_page(pte); - nocache_page(pte); -// } - kunmap(page); - - return page; -} - -extern inline void pte_free(struct mm_struct *mm, struct page *page) -{ - __free_page(page); -} - -/* - * In our implementation, each pgd entry contains 1 pmd that is never allocated - * or freed. pgd_present is always 1, so this should never be called. -NL - */ -#define pmd_free(mm, pmd) BUG() - -extern inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - free_page((unsigned long) pgd); -} - -extern inline pgd_t *pgd_alloc(struct mm_struct *mm) -{ - pgd_t *new_pgd; - - new_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_NOWARN); - if (!new_pgd) - return NULL; - memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE); - memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT); - return new_pgd; -} - -#define pgd_populate(mm, pmd, pte) BUG() - -#endif /* M68K_CF_PGALLOC_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_pgtable.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_pgtable.h deleted file mode 100644 index 65668381d6..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_pgtable.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef _CF_PGTABLE_H -#define _CF_PGTABLE_H - -#include <asm/cfmmu.h> -#include <asm/page.h> - -#ifndef __ASSEMBLY__ -#include <asm/virtconvert.h> -#include <linux/linkage.h> - -/* For virtual address to physical address conversion */ -#define VTOP(addr) __pa(addr) -#define PTOV(addr) __va(addr) - - -#endif /* !__ASSEMBLY__ */ - -/* Page protection values within PTE. */ - -/* MMUDR bits, in proper place. */ -#define CF_PAGE_LOCKED (0x00000002) -#define CF_PAGE_EXEC (0x00000004) -#define CF_PAGE_WRITABLE (0x00000008) -#define CF_PAGE_READABLE (0x00000010) -#define CF_PAGE_SYSTEM (0x00000020) -#define CF_PAGE_COPYBACK (0x00000040) -#define CF_PAGE_NOCACHE (0x00000080) - -#define CF_CACHEMASK (~0x00000040) -#define CF_PAGE_MMUDR_MASK (0x000000fe) - -#define _PAGE_NOCACHE030 (CF_PAGE_NOCACHE) - -/* MMUTR bits, need shifting down. */ -#define CF_PAGE_VALID (0x00000400) -#define CF_PAGE_SHARED (0x00000800) - -#define CF_PAGE_MMUTR_MASK (0x00000c00) -#define CF_PAGE_MMUTR_SHIFT (10) -#define CF_ASID_MMU_SHIFT (2) - -/* Fake bits, not implemented in CF, will get masked out before - hitting hardware, and might go away altogether once this port is - complete. */ -#if PAGE_SHIFT < 13 -#error COLDFIRE Error: Pages must be at least 8k in size -#endif -#define CF_PAGE_ACCESSED (0x00001000) -#define CF_PAGE_FILE (0x00000200) -#define CF_PAGE_DIRTY (0x00000001) - -#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */ -#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */ -#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */ -#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */ -#define _DESCTYPE_MASK 0x003 -#define _CACHEMASK040 (~0x060) -#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ - - -/* Externally used page protection values. */ -#define _PAGE_PRESENT (CF_PAGE_VALID) -#define _PAGE_ACCESSED (CF_PAGE_ACCESSED) -#define _PAGE_DIRTY (CF_PAGE_DIRTY) -#define _PAGE_READWRITE (CF_PAGE_WRITABLE \ - | CF_PAGE_READABLE \ - | CF_PAGE_SHARED \ - | CF_PAGE_SYSTEM) - -/* Compound page protection values. */ -#define PAGE_NONE __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED) - -#define PAGE_SHARED __pgprot(CF_PAGE_VALID \ - | CF_PAGE_READABLE \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_ACCESSED) - -#define PAGE_INIT __pgprot(CF_PAGE_VALID \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_READABLE \ - | CF_PAGE_EXEC \ - | CF_PAGE_SYSTEM \ - | CF_PAGE_SHARED) - -#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_READABLE \ - | CF_PAGE_EXEC \ - | CF_PAGE_SYSTEM \ - | CF_PAGE_SHARED \ - | CF_PAGE_ACCESSED) - -#define PAGE_COPY __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_READABLE) - -/* - * Page protections for initialising protection_map. See mm/mmap.c - * for use. In general, the bit positions are xwr, and P-items are - * private, the S-items are shared. - */ - -#define __P000 PAGE_NONE -#define __P100 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_EXEC) -#define __P010 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_ACCESSED) -#define __P110 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_EXEC) -#define __P001 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_READABLE) -#define __P101 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_READABLE \ - | CF_PAGE_EXEC) -#define __P011 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_READABLE \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_ACCESSED) -#define __P111 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_READABLE \ - | CF_PAGE_EXEC) - -#define __S000 PAGE_NONE -#define __S100 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_EXEC) -#define __S010 PAGE_SHARED -#define __S110 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_EXEC) -#define __S001 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_READABLE) -#define __S101 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_READABLE \ - | CF_PAGE_EXEC) -#define __S011 PAGE_SHARED -#define __S111 __pgprot(CF_PAGE_VALID \ - | CF_PAGE_ACCESSED \ - | CF_PAGE_READABLE \ - | CF_PAGE_WRITABLE \ - | CF_PAGE_EXEC) - -#define PTE_MASK PAGE_MASK -#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY) - -#ifndef __ASSEMBLY__ - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) - -extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); - return pte; -} - -#define pmd_set(pmdp, ptep) do {} while (0) - -static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) -{ - pgd_val(*pgdp) = virt_to_phys(pmdp); -} - -#define __pte_page(pte) \ - ((unsigned long) ((pte_val(pte) & CF_PAGE_PGNUM_MASK) + PAGE_OFFSET)) -#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd))) - -extern inline int pte_none(pte_t pte) -{ - return !pte_val(pte); -} -extern inline int pte_present(pte_t pte) -{ - return pte_val(pte) & CF_PAGE_VALID; -} -extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, - pte_t *ptep) -{ - pte_val(*ptep) = 0; -} - -#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) -#define pte_page(pte) virt_to_page(__pte_page(pte)) - -extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); } -#define pmd_none(pmd) pmd_none2(&(pmd)) -extern inline int pmd_bad2(pmd_t *pmd) { return 0; } -#define pmd_bad(pmd) pmd_bad2(&(pmd)) -#define pmd_present(pmd) (!pmd_none2(&(pmd))) -extern inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; } - -extern inline int pgd_none(pgd_t pgd) { return 0; } -extern inline int pgd_bad(pgd_t pgd) { return 0; } -extern inline int pgd_present(pgd_t pgd) { return 1; } -extern inline void pgd_clear(pgd_t *pgdp) {} - - -#define pte_ERROR(e) \ - printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ - __FILE__, __LINE__, pte_val(e)) -#define pmd_ERROR(e) \ - printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \ - __FILE__, __LINE__, pmd_val(e)) -#define pgd_ERROR(e) \ - printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ - __FILE__, __LINE__, pgd_val(e)) - - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not... - * [we have the full set here even if they don't change from m68k] - */ -extern inline int pte_read(pte_t pte) \ - { return pte_val(pte) & CF_PAGE_READABLE; } -extern inline int pte_write(pte_t pte) \ - { return pte_val(pte) & CF_PAGE_WRITABLE; } -extern inline int pte_exec(pte_t pte) \ - { return pte_val(pte) & CF_PAGE_EXEC; } -extern inline int pte_dirty(pte_t pte) \ - { return pte_val(pte) & CF_PAGE_DIRTY; } -extern inline int pte_young(pte_t pte) \ - { return pte_val(pte) & CF_PAGE_ACCESSED; } -extern inline int pte_file(pte_t pte) \ - { return pte_val(pte) & CF_PAGE_FILE; } -static inline int pte_special(pte_t pte) { return 0; } - - -extern inline pte_t pte_wrprotect(pte_t pte) \ - { pte_val(pte) &= ~CF_PAGE_WRITABLE; return pte; } -extern inline pte_t pte_rdprotect(pte_t pte) \ - { pte_val(pte) &= ~CF_PAGE_READABLE; return pte; } -extern inline pte_t pte_exprotect(pte_t pte) \ - { pte_val(pte) &= ~CF_PAGE_EXEC; return pte; } -extern inline pte_t pte_mkclean(pte_t pte) \ - { pte_val(pte) &= ~CF_PAGE_DIRTY; return pte; } -extern inline pte_t pte_mkold(pte_t pte) \ - { pte_val(pte) &= ~CF_PAGE_ACCESSED; return pte; } -extern inline pte_t pte_mkwrite(pte_t pte) \ - { pte_val(pte) |= CF_PAGE_WRITABLE; return pte; } -extern inline pte_t pte_mkread(pte_t pte) \ - { pte_val(pte) |= CF_PAGE_READABLE; return pte; } -extern inline pte_t pte_mkexec(pte_t pte) \ - { pte_val(pte) |= CF_PAGE_EXEC; return pte; } -extern inline pte_t pte_mkdirty(pte_t pte) \ - { pte_val(pte) |= CF_PAGE_DIRTY; return pte; } -extern inline pte_t pte_mkyoung(pte_t pte) \ - { pte_val(pte) |= CF_PAGE_ACCESSED; return pte; } -extern inline pte_t pte_mknocache(pte_t pte) \ - { pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); return pte; } -extern inline pte_t pte_mkcache(pte_t pte) \ - { pte_val(pte) &= ~CF_PAGE_NOCACHE; return pte; } -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } - - -#define swapper_pg_dir kernel_pg_dir -extern pgd_t kernel_pg_dir[PTRS_PER_PGD]; - -/* Find an entry in a pagetable directory. */ -#define pgd_index(address) ((address) >> PGDIR_SHIFT) - -#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) - -/* Find an entry in a kernel pagetable directory. */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* Find an entry in the second-level pagetable. */ -extern inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address) -{ - return (pmd_t *) pgd; -} - -/* Find an entry in the third-level pagetable. */ -#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset_kernel(dir, address) ((pte_t *) __pmd_page(*(dir)) + \ - __pte_offset(address)) - -/* Disable caching for page at given kernel virtual address. */ -static inline void nocache_page(void *vaddr) -{ - pgd_t *dir; - pmd_t *pmdp; - pte_t *ptep; - unsigned long addr = (unsigned long)vaddr; - - dir = pgd_offset_k(addr); - pmdp = pmd_offset(dir, addr); - ptep = pte_offset_kernel(pmdp, addr); - *ptep = pte_mknocache(*ptep); -} - -/* Enable caching for page at given kernel virtual address. */ -static inline void cache_page(void *vaddr) -{ - pgd_t *dir; - pmd_t *pmdp; - pte_t *ptep; - unsigned long addr = (unsigned long)vaddr; - - dir = pgd_offset_k(addr); - pmdp = pmd_offset(dir, addr); - ptep = pte_offset_kernel(pmdp, addr); - *ptep = pte_mkcache(*ptep); -} - -#define PTE_FILE_MAX_BITS 21 -#define PTE_FILE_SHIFT 11 - -static inline unsigned long pte_to_pgoff(pte_t pte) -{ - return pte_val(pte) >> PTE_FILE_SHIFT; -} - -static inline pte_t pgoff_to_pte(unsigned pgoff) -{ - pte_t pte = __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE); - return pte; -} - -/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ -#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ - (offset << PTE_FILE_SHIFT) }) -#define __swp_type(x) ((x).val & 0xFF) -#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) (__pte((x).val)) - -#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) - -#define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) + \ - __pte_offset(address)) -#define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address) -#define pte_unmap(pte) kunmap(pte) -#define pte_unmap_nested(pte) kunmap(pte) - -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) - - -#endif /* !__ASSEMBLY__ */ -#endif /* !_CF_PGTABLE_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_raw_io.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_raw_io.h deleted file mode 100644 index 246a45568d..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_raw_io.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * linux/include/asm-m68k/cf_raw_io.h - * - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * 09/30/08 JKM: split Coldfire pieces into separate file - */ -#ifndef __CF_RAW_IO__ -#define __CF_RAW_IO__ - -#ifdef __KERNEL__ - -#include <asm/types.h> - -/* Values for nocacheflag and cmode */ -#define IOMAP_FULL_CACHING 0 -#define IOMAP_NOCACHE_SER 1 -#define IOMAP_NOCACHE_NONSER 2 -#define IOMAP_WRITETHROUGH 3 - -extern void iounmap(void __iomem *addr); - -extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size, - int cacheflag); -extern void __iounmap(void *addr, unsigned long size); - - -/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates - * two accesses to memory, which may be undesirable for some devices. - */ -#define in_8(addr) \ - ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; }) -#define in_be16(addr) \ - ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; }) -#define in_be32(addr) \ - ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; }) -#define in_le16(addr) \ - ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; }) -#define in_le32(addr) \ - ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; }) - -#define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b)) -#define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w)) -#define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l)) -#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w)) -#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l)) - - -#ifdef CONFIG_PCI -/* pci */ -unsigned char pci_inb(long addr); -unsigned short pci_inw(long addr); -unsigned long pci_inl(long addr); - -void pci_outb(unsigned char val, long addr); -void pci_outw(unsigned short val, long addr); -void pci_outl(unsigned long val, long addr); - -void pci_insb(volatile unsigned char *addr, - unsigned char *buf, int len); -void pci_insw(volatile unsigned short *addr, - unsigned short *buf, int len); -void pci_insl(volatile unsigned long *addr, - unsigned long *buf, int len); - -void pci_outsb(volatile unsigned char *addr, - const unsigned char *buf, int len); -void pci_outsw(volatile unsigned short *addr, - const unsigned short *buf, int len); -void pci_outsl(volatile unsigned long *addr, - const unsigned long *buf, int len); - -unsigned short pci_raw_inw(long addr); -unsigned long pci_raw_inl(long addr); -void pci_raw_outw(unsigned short val, long addr); -void pci_raw_outl(unsigned long val, long addr); - -#define raw_inb(port) pci_inb((long)((volatile unsigned char *)(port))) -#define raw_inw(port) pci_raw_inw((long)((volatile unsigned short *)(port))) -#define raw_inl(port) pci_raw_inl((long)((volatile unsigned long *)(port))) - -#define raw_outb(val, port) \ - pci_outb((val), (long)((volatile unsigned char *)(port))) -#define raw_outw(val, port) \ - pci_raw_outw((val), (long)((volatile unsigned short *)(port))) -#define raw_outl(val, port) \ - pci_raw_outl((val), (long)((volatile unsigned long *)(port))) - -#define swap_inw(port) pci_inw((long)((volatile unsigned short *)(port))) -#define swap_outw(val, port) \ - pci_outw((val), (long)((volatile unsigned short *)(port))) - -#else -/* non-pci */ -#define raw_inb in_8 -#define raw_inw in_be16 -#define raw_inl in_be32 - -#define raw_outb(val,port) out_8((port),(val)) -#define raw_outw(val,port) out_be16((port),(val)) -#define raw_outl(val,port) out_be32((port),(val)) - -#define swap_inw(port) in_le16((port)) -#define swap_outw(val,port) out_le16((port),(val)) -#endif - -static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len) -{ - unsigned int i; - - for (i = 0; i < len; i++) - *buf++ = in_8(port); -} - -static inline void raw_outsb(volatile u8 __iomem *port, const u8 *buf, - unsigned int len) -{ - unsigned int i; - - for (i = 0; i < len; i++) - out_8(port, *buf++); -} - -static inline void raw_insw(volatile u16 *port, u16 *buf, unsigned int nr) -{ - unsigned int i; - - for (i = 0; i < nr; i++) - *buf++ = raw_inw(port); -} - -static inline void raw_outsw(volatile u16 *port, const u16 *buf, - unsigned int nr) -{ - unsigned int i; - - for (i = 0; i < nr; i++, buf++) - raw_outw(*buf, port); -} - -static inline void raw_insl(volatile u32 *port, u32 *buf, unsigned int nr) -{ - unsigned int i; - - for (i = 0; i < nr; i++) - *buf++ = raw_inl(port); -} - -static inline void raw_outsl(volatile u32 *port, const u32 *buf, - unsigned int nr) -{ - unsigned int i; - - for (i = 0; i < nr; i++, buf++) - raw_outl(*buf, port); -} - -static inline void raw_insw_swapw(volatile u16 *port, u16 *buf, - unsigned int nr) -{ -#ifdef UNDEF - unsigned int i; - - for (i = 0; i < nr; i++) - *buf++ = in_le16(port); -#endif -} - -static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf, - unsigned int nr) -{ -#ifdef UNDEF - unsigned int i; - - for (i = 0; i < nr; i++, buf++) - out_le16(port, *buf); -#endif -} - -#endif /* __KERNEL__ */ - -#endif /* __CF_RAW_IO__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_tlbflush.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_tlbflush.h deleted file mode 100644 index ae253d4eef..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_tlbflush.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#ifndef M68K_CF_TLBFLUSH_H -#define M68K_CF_TLBFLUSH_H - -#include <asm/coldfire.h> - -/* Flush all userspace mappings. */ -static inline void flush_tlb_all(void) -{ - preempt_disable(); - *MMUOR = MMUOR_CNL; - preempt_enable(); -} - -/* Clear user TLB entries within the context named in mm */ -static inline void flush_tlb_mm(struct mm_struct *mm) -{ - preempt_disable(); - *MMUOR = MMUOR_CNL; - preempt_enable(); -} - -/* Flush a single TLB page. */ -static inline void flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr) -{ - preempt_disable(); - *MMUOR = MMUOR_CNL; - preempt_enable(); -} -/* Flush a range of pages from TLB. */ - -static inline void flush_tlb_range(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ - preempt_disable(); - *MMUOR = MMUOR_CNL; - preempt_enable(); -} - -/* Flush kernel page from TLB. */ -static inline void flush_tlb_kernel_page(void *addr) -{ - preempt_disable(); - *MMUOR = MMUOR_CNL; - preempt_enable(); -} - -static inline void flush_tlb_kernel_range(unsigned long start, - unsigned long end) -{ - flush_tlb_all(); -} - -extern inline void flush_tlb_pgtables(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ -} - -#endif /* M68K_CF_TLBFLUSH_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_uaccess.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_uaccess.h deleted file mode 100644 index d667097dd0..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_uaccess.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#ifndef __M68K_CF_UACCESS_H -#define __M68K_CF_UACCESS_H - -/* - * User space memory access functions - */ - -/* The "moves" command is not available in the CF instruction set. */ -#include <linux/compiler.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <asm/segment.h> - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -/* We let the MMU do all checking */ -#define access_ok(type, addr, size) 1 - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -extern int __put_user_bad(void); -extern int __get_user_bad(void); - -#define __put_user_asm(res, x, ptr, bwl, reg, err) \ -asm volatile ("\n" \ - "1: move."#bwl" %2,%1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - " .even\n" \ - "10: moveq.l %3,%0\n" \ - " jra 2b\n" \ - " .previous\n" \ - "\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 4\n" \ - " .long 1b,10b\n" \ - " .long 2b,10b\n" \ - " .previous" \ - : "+d" (res), "=m" (*(ptr)) \ - : #reg (x), "i" (err)) - -/* - * These are the main single-value transfer routines. They automatically - * use the right size if we just have the right pointer type. - */ - -#define __put_user(x, ptr) \ -({ \ - typeof(*(ptr)) __pu_val = (x); \ - int __pu_err = 0; \ - __chk_user_ptr(ptr); \ - switch (sizeof (*(ptr))) { \ - case 1: \ - __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \ - break; \ - case 2: \ - __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \ - break; \ - case 4: \ - __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \ - break; \ - case 8: \ - { \ - const void __user *__pu_ptr = (ptr); \ - asm volatile ("\n" \ - "1: move.l %2,(%1)+\n" \ - "2: move.l %R2,(%1)\n" \ - "3:\n" \ - " .section .fixup,\"ax\"\n" \ - " .even\n" \ - "10: movel %3,%0\n" \ - " jra 3b\n" \ - " .previous\n" \ - "\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 4\n" \ - " .long 1b,10b\n" \ - " .long 2b,10b\n" \ - " .long 3b,10b\n" \ - " .previous" \ - : "+d" (__pu_err), "+a" (__pu_ptr) \ - : "r" (__pu_val), "i" (-EFAULT) \ - : "memory"); \ - break; \ - } \ - default: \ - __pu_err = __put_user_bad(); \ - break; \ - } \ - __pu_err; \ -}) -#define put_user(x, ptr) __put_user(x, ptr) - - -#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \ - type __gu_val; \ - asm volatile ("\n" \ - "1: move."#bwl" %2,%1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - " .even\n" \ - "10: move.l %3,%0\n" \ - " subl %1,%1\n" \ - " jra 2b\n" \ - " .previous\n" \ - "\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 4\n" \ - " .long 1b,10b\n" \ - " .previous" \ - : "+d" (res), "=&" #reg (__gu_val) \ - : "m" (*(ptr)), "i" (err)); \ - (x) = (typeof(*(ptr)))(unsigned long)__gu_val; \ -}) - -#define __get_user(x, ptr) \ -({ \ - int __gu_err = 0; \ - __chk_user_ptr(ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \ - break; \ - case 2: \ - __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \ - break; \ - case 4: \ - __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \ - break; \ -/* case 8: disabled because gcc-4.1 has a broken typeof \ - { \ - const void *__gu_ptr = (ptr); \ - u64 __gu_val; \ - asm volatile ("\n" \ - "1: move.l (%2)+,%1\n" \ - "2: move.l (%2),%R1\n" \ - "3:\n" \ - " .section .fixup,\"ax\"\n" \ - " .even\n" \ - "10: move.l %3,%0\n" \ - " subl %1,%1\n" \ - " subl %R1,%R1\n" \ - " jra 3b\n" \ - " .previous\n" \ - "\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 4\n" \ - " .long 1b,10b\n" \ - " .long 2b,10b\n" \ - " .previous" \ - : "+d" (__gu_err), "=&r" (__gu_val), \ - "+a" (__gu_ptr) \ - : "i" (-EFAULT) \ - : "memory"); \ - (x) = (typeof(*(ptr)))__gu_val; \ - break; \ - } */ \ - default: \ - __gu_err = __get_user_bad(); \ - break; \ - } \ - __gu_err; \ -}) -#define get_user(x, ptr) __get_user(x, ptr) - -unsigned long __generic_copy_from_user(void *to, const void __user *from, - unsigned long n); -unsigned long __generic_copy_to_user(void __user *to, const void *from, - unsigned long n); - -#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\ - asm volatile ("\n" \ - "1: move."#s1" (%2)+,%3\n" \ - " move."#s1" %3,(%1)+\n" \ - "2: move."#s2" (%2)+,%3\n" \ - " move."#s2" %3,(%1)+\n" \ - " .ifnc \""#s3"\",\"\"\n" \ - "3: move."#s3" (%2)+,%3\n" \ - " move."#s3" %3,(%1)+\n" \ - " .endif\n" \ - "4:\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 4\n" \ - " .long 1b,10f\n" \ - " .long 2b,20f\n" \ - " .ifnc \""#s3"\",\"\"\n" \ - " .long 3b,30f\n" \ - " .endif\n" \ - " .previous\n" \ - "\n" \ - " .section .fixup,\"ax\"\n" \ - " .even\n" \ - "10: clr."#s1" (%1)+\n" \ - "20: clr."#s2" (%1)+\n" \ - " .ifnc \""#s3"\",\"\"\n" \ - "30: clr."#s3" (%1)+\n" \ - " .endif\n" \ - " moveq.l #"#n",%0\n" \ - " jra 4b\n" \ - " .previous\n" \ - : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \ - : : "memory") - -static __always_inline unsigned long -__constant_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - unsigned long res = 0, tmp; - - switch (n) { - case 1: - __get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1); - break; - case 2: - __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w, - d, 2); - break; - case 3: - __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,); - break; - case 4: - __get_user_asm(res, *(u32 *)to, (u32 __user *)from, u32, l, - r, 4); - break; - case 5: - __constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,); - break; - case 6: - __constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,); - break; - case 7: - __constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b); - break; - case 8: - __constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,); - break; - case 9: - __constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b); - break; - case 10: - __constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w); - break; - case 12: - __constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l); - break; - default: - /* we limit the inlined version to 3 moves */ - return __generic_copy_from_user(to, from, n); - } - - return res; -} - -#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ - asm volatile ("\n" \ - " move."#s1" (%2)+,%3\n" \ - "11: move."#s1" %3,(%1)+\n" \ - "12: move."#s2" (%2)+,%3\n" \ - "21: move."#s2" %3,(%1)+\n" \ - "22:\n" \ - " .ifnc \""#s3"\",\"\"\n" \ - " move."#s3" (%2)+,%3\n" \ - "31: move."#s3" %3,(%1)+\n" \ - "32:\n" \ - " .endif\n" \ - "4:\n" \ - "\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 4\n" \ - " .long 11b,5f\n" \ - " .long 12b,5f\n" \ - " .long 21b,5f\n" \ - " .long 22b,5f\n" \ - " .ifnc \""#s3"\",\"\"\n" \ - " .long 31b,5f\n" \ - " .long 32b,5f\n" \ - " .endif\n" \ - " .previous\n" \ - "\n" \ - " .section .fixup,\"ax\"\n" \ - " .even\n" \ - "5: moveq.l #"#n",%0\n" \ - " jra 4b\n" \ - " .previous\n" \ - : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \ - : : "memory") - -static __always_inline unsigned long -__constant_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - unsigned long res = 0, tmp; - - switch (n) { - case 1: - __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1); - break; - case 2: - __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2); - break; - case 3: - __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,); - break; - case 4: - __put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4); - break; - case 5: - __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,); - break; - case 6: - __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,); - break; - case 7: - __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b); - break; - case 8: - __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,); - break; - case 9: - __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b); - break; - case 10: - __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w); - break; - case 12: - __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l); - break; - default: - /* limit the inlined version to 3 moves */ - return __generic_copy_to_user(to, from, n); - } - - return res; -} - -#define __copy_from_user(to, from, n) \ -(__builtin_constant_p(n) ? \ - __constant_copy_from_user(to, from, n) : \ - __generic_copy_from_user(to, from, n)) - -#define __copy_to_user(to, from, n) \ -(__builtin_constant_p(n) ? \ - __constant_copy_to_user(to, from, n) : \ - __generic_copy_to_user(to, from, n)) - -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user - -#define copy_from_user(to, from, n) __copy_from_user(to, from, n) -#define copy_to_user(to, from, n) __copy_to_user(to, from, n) - -long strncpy_from_user(char *dst, const char __user *src, long count); -long strnlen_user(const char __user *src, long n); -unsigned long __clear_user(void __user *to, unsigned long n); - -#define clear_user __clear_user - -#define strlen_user(str) strnlen_user(str, 32767) - -#endif /* _M68K_CF_UACCESS_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_virtconvert.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_virtconvert.h deleted file mode 100644 index ed95887da2..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cf_virtconvert.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#ifndef __CF_VIRTCONVERT__ -#define __CF_VIRTCONVERT__ - -/* - * Macros used for converting between virtual and physical mappings. - * - * Coldfire Specific - */ - -#ifdef __KERNEL__ - -#include <linux/compiler.h> -#include <linux/mmzone.h> -#include <asm/setup.h> -#include <asm/page.h> - -/* - * Change virtual addresses to physical addresses and vv. - */ -static inline unsigned long virt_to_phys(void *address) -{ - return __pa(address); -} - -static inline void *phys_to_virt(unsigned long address) -{ - return __va(address); -} - -/* Permanent address of a page. */ -#ifdef CONFIG_SINGLE_MEMORY_CHUNK -#define page_to_phys(page) \ - __pa(PAGE_OFFSET + (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT)) -#else -#define page_to_phys(_page) ({ \ - struct page *__page = _page; \ - struct pglist_data *pgdat; \ - pgdat = pg_data_table[page_to_nid(__page)]; \ - page_to_pfn(__page) << PAGE_SHIFT; \ -}) -#endif - -/* - * IO bus memory addresses are 1:1 with the physical address, - */ -#ifdef CONFIG_PCI -#define virt_to_bus(a) (a + PCI_DMA_BASE) -#define bus_to_virt(a) (a - PCI_DMA_BASE) -#else -#define virt_to_bus(a) (a) -#define bus_to_virt(a) (a) -#endif - -#endif /* __KERNEL__ */ -#endif /* __CF_VIRTCONVERT__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfcache.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfcache.h deleted file mode 100644 index 730ee97770..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfcache.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * include/asm-m68k/cfcache.h - Coldfire Cache Controller - * - * Kurt Mahan kmahan@freescale.com - * - * Copyright Freescale Semiconductor, Inc. 2007 - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef CF_CFCACHE_H -#define CF_CFCACHE_H - -/* - * CACR Cache Control Register - */ -#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */ -#define CF_CACR_DW (0x40000000) /* Data default Write-protect */ -#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */ -#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */ -#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */ -#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */ -#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */ -#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */ -#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */ -#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */ -#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */ -#define CF_CACR_IVO (0x00100000) /* Invalidate only */ -#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */ -#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */ -#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */ -#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */ -#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */ -#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */ -#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */ -#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */ -#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */ -#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */ -#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */ - -#ifdef CONFIG_M5445X -/* - * M5445x Cache Configuration - * - cache line size is 16 bytes - * - cache is 4-way set associative - * - each cache has 256 sets (64k / 16bytes / 4way) - * - I-Cache size is 16KB - * - D-Cache size is 16KB - */ -#define ICACHE_SIZE 0x4000 /* instruction - 16k */ -#define DCACHE_SIZE 0x4000 /* data - 16k */ - -#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ -#define CACHE_SETS 0x0100 /* 256 sets */ -#define CACHE_WAYS 0x0004 /* 4 way */ - -#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ - CF_CACR_BCINVA+ \ - CF_CACR_ICINVA) - -#ifndef CONFIG_M5445X_DISABLE_CACHE -#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ - CF_CACR_BEC+ \ - CF_CACR_IEC+ \ - CF_CACR_DESB+ \ - CF_CACR_EUSP) -#else -/* cache disabled for testing */ -#define CACHE_INITIAL_MODE (CF_CACR_EUSP) -#endif /* CONFIG_M5445X_DISABLE_CACHE */ - -#elif defined(CONFIG_M547X_8X) -/* - * * M547x/M548x Cache Configuration - * * - cache line size is 16 bytes - * * - cache is 4-way set associative - * * - each cache has 512 sets (128k / 16bytes / 4way) - * * - I-Cache size is 32KB - * * - D-Cache size is 32KB - * */ -#define ICACHE_SIZE 0x8000 /* instruction - 32k */ -#define DCACHE_SIZE 0x8000 /* data - 32k */ - -#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ -#define CACHE_SETS 0x0200 /* 512 sets */ -#define CACHE_WAYS 0x0004 /* 4 way */ - -/* in for the old cpushl caching code */ -#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS) -#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS) -#define LAST_DCACHE_ADDR _DCACHE_SET_MASK -#define LAST_ICACHE_ADDR _ICACHE_SET_MASK - -#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ - CF_CACR_BCINVA+ \ - CF_CACR_ICINVA) - -#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ - CF_CACR_BEC+ \ - CF_CACR_IEC+ \ - CF_CACR_DESB+ \ - CF_CACR_EUSP) -#endif /* CONFIG_M547X_8X */ - -#ifndef __ASSEMBLY__ - -extern unsigned long shadow_cacr; -extern void cacr_set(unsigned long x); - -#endif /* !__ASSEMBLY__ */ - -#endif /* CF_CACHE_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfmmu.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfmmu.h deleted file mode 100644 index 758a9eb3fd..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/cfmmu.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Definitions for Coldfire V4e MMU - */ -#include <asm/movs.h> - -#ifndef __CF_MMU_H__ -#define __CF_MMU_H__ - - -#define MMU_BASE 0xE8000000 - - -#define MMUCR (MMU_BASE+0x00) -#define MMUCR_ASMN 1 -#define MMUCR_ASM (1<<MMUCR_ASMN) -#define MMUCR_ENN 0 -#define MMUCR_EN (1<<MMUCR_ENN) - -#define MMUOR REG16(MMU_BASE+0x04+0x02) -#define MMUOR_AAN 16 -#define MMUOR_AA (0xffff<<MMUOR_AAN) -#define MMUOR_STLBN 8 -#define MMUOR_STLB (1<<MMUOR_STLBN) -#define MMUOR_CAN 7 -#define MMUOR_CA (1<<MMUOR_CAN) -#define MMUOR_CNLN 6 -#define MMUOR_CNL (1<<MMUOR_CNLN) -#define MMUOR_CASN 5 -#define MMUOR_CAS (1<<MMUOR_CASN) -#define MMUOR_ITLBN 4 -#define MMUOR_ITLB (1<<MMUOR_ITLBN) -#define MMUOR_ADRN 3 -#define MMUOR_ADR (1<<MMUOR_ADRN) -#define MMUOR_RWN 2 -#define MMUOR_RW (1<<MMUOR_RWN) -#define MMUOR_ACCN 1 -#define MMUOR_ACC (1<<MMUOR_ACCN) -#define MMUOR_UAAN 0 -#define MMUOR_UAA (1<<MMUOR_UAAN) - -#define MMUSR REG32(MMU_BASE+0x08) -#define MMUSR_SPFN 5 -#define MMUSR_SPF (1<<MMUSR_SPFN) -#define MMUSR_RFN 4 -#define MMUSR_RF (1<<MMUSR_RFN) -#define MMUSR_WFN 3 -#define MMUSR_WF (1<<MMUSR_WFN) -#define MMUSR_HITN 1 -#define MMUSR_HIT (1<<MMUSR_HITN) - -#define MMUAR REG32(MMU_BASE+0x10) -#define MMUAR_VPN 1 -#define MMUAR_VP (0xfffffffe) -#define MMUAR_SN 0 -#define MMUAR_S (1<<MMUAR_SN) - -#define MMUTR REG32(MMU_BASE+0x14) -#define MMUTR_VAN 10 -#define MMUTR_VA (0xfffffc00) -#define MMUTR_IDN 2 -#define MMUTR_ID (0xff<<MMUTR_IDN) -#define MMUTR_SGN 1 -#define MMUTR_SG (1<<MMUTR_SGN) -#define MMUTR_VN 0 -#define MMUTR_V (1<<MMUTR_VN) - -#define MMUDR REG32(MMU_BASE+0x18) -#define MMUDR_PAN 10 -#define MMUDR_PA (0xfffffc00) -#define MMUDR_SZN 8 -#define MMUDR_SZ_MASK (0x2<<MMUDR_SZN) -#define MMUDR_SZ1M (0<<MMUDR_SZN) -#define MMUDR_SZ4K (1<<MMUDR_SZN) -#define MMUDR_SZ8K (2<<MMUDR_SZN) -#define MMUDR_SZ16M (3<<MMUDR_SZN) -#define MMUDR_CMN 6 -#define MMUDR_INC (2<<MMUDR_CMN) -#define MMUDR_IC (0<<MMUDR_CMN) -#define MMUDR_DWT (0<<MMUDR_CMN) -#define MMUDR_DCB (1<<MMUDR_CMN) -#define MMUDR_DNCP (2<<MMUDR_CMN) -#define MMUDR_DNCIP (3<<MMUDR_CMN) -#define MMUDR_SPN 5 -#define MMUDR_SP (1<<MMUDR_SPN) -#define MMUDR_RN 4 -#define MMUDR_R (1<<MMUDR_RN) -#define MMUDR_WN 3 -#define MMUDR_W (1<<MMUDR_WN) -#define MMUDR_XN 2 -#define MMUDR_X (1<<MMUDR_XN) -#define MMUDR_LKN 1 -#define MMUDR_LK (1<<MMUDR_LKN) - - -#ifndef __ASSEMBLY__ -#define CF_PMEGS_NUM 256 -#define CF_INVALID_CONTEXT 255 -#define CF_PAGE_PGNUM_MASK (PAGE_MASK) - -extern int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, - int extension_word); -#endif /* __ASSEMBLY__*/ - -#endif /* !__CF_MMU_H__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dma.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dma.h deleted file mode 100644 index aba920c4b4..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dma.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * m5485dma.h -- ColdFire 547x/548x DMA controller support. - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#ifndef __MCF548X_DMA_H__ -#define __MCF548X_DMA_H__ - - -/* Register read/write macros */ -#define MCF_DMA_DIPR MCF_REG32(0x008014) -#define MCF_DMA_DIMR MCF_REG32(0x008018) -#define MCF_DMA_IMCR MCF_REG32(0x00805C) - -/* Bit definitions and macros for MCF_DMA_DIPR */ -#define MCF_DMA_DIPR_TASK0 (0x00000001) -#define MCF_DMA_DIPR_TASK1 (0x00000002) -#define MCF_DMA_DIPR_TASK2 (0x00000004) -#define MCF_DMA_DIPR_TASK3 (0x00000008) -#define MCF_DMA_DIPR_TASK4 (0x00000010) -#define MCF_DMA_DIPR_TASK5 (0x00000020) -#define MCF_DMA_DIPR_TASK6 (0x00000040) -#define MCF_DMA_DIPR_TASK7 (0x00000080) -#define MCF_DMA_DIPR_TASK8 (0x00000100) -#define MCF_DMA_DIPR_TASK9 (0x00000200) -#define MCF_DMA_DIPR_TASK10 (0x00000400) -#define MCF_DMA_DIPR_TASK11 (0x00000800) -#define MCF_DMA_DIPR_TASK12 (0x00001000) -#define MCF_DMA_DIPR_TASK13 (0x00002000) -#define MCF_DMA_DIPR_TASK14 (0x00004000) -#define MCF_DMA_DIPR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF_DMA_DIMR */ -#define MCF_DMA_DIMR_TASK0 (0x00000001) -#define MCF_DMA_DIMR_TASK1 (0x00000002) -#define MCF_DMA_DIMR_TASK2 (0x00000004) -#define MCF_DMA_DIMR_TASK3 (0x00000008) -#define MCF_DMA_DIMR_TASK4 (0x00000010) -#define MCF_DMA_DIMR_TASK5 (0x00000020) -#define MCF_DMA_DIMR_TASK6 (0x00000040) -#define MCF_DMA_DIMR_TASK7 (0x00000080) -#define MCF_DMA_DIMR_TASK8 (0x00000100) -#define MCF_DMA_DIMR_TASK9 (0x00000200) -#define MCF_DMA_DIMR_TASK10 (0x00000400) -#define MCF_DMA_DIMR_TASK11 (0x00000800) -#define MCF_DMA_DIMR_TASK12 (0x00001000) -#define MCF_DMA_DIMR_TASK13 (0x00002000) -#define MCF_DMA_DIMR_TASK14 (0x00004000) -#define MCF_DMA_DIMR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF_DMA_IMCR */ -#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) -#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) -#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) -#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) -#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) -#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) -#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) -#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) -#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) -#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) -#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) -#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) -#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) -#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) -#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) -#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) -#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) -#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) -#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) -#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) -#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) -#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) -#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) -#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) -#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) -#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) -#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) -#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) -#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) -#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) -#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) -#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) -#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) -#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) -#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) -#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) -#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) -#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) -#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) -#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) -#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) -#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) -#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) -#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) -#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) -#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) - -#endif /* __MCF548X_DMA_H__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dspi.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dspi.h deleted file mode 100644 index 0b7f6f37e1..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dspi.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * File: mcf548x_dspi.h - * Purpose: Register and bit definitions for the MCF548X - * - * Notes: - * - */ - -#ifndef _M5485DSPI_H_ -#define _M5485DSPI_H_ - -/* - * - * DMA Serial Peripheral Interface (DSPI) - * - */ - -/* Register read/write macros */ -#define MCF_DSPI_DMCR MCF_REG32(0x008A00) -#define MCF_DSPI_DTCR MCF_REG32(0x008A08) -#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C) -#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10) -#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14) -#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18) -#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C) -#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20) -#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24) -#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28) -#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4)) -#define MCF_DSPI_DSR MCF_REG32(0x008A2C) -#define MCF_DSPI_DRSER MCF_REG32(0x008A30) -#define MCF_DSPI_DTFR MCF_REG32(0x008A34) -#define MCF_DSPI_DRFR MCF_REG32(0x008A38) -#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C) -#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40) -#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44) -#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48) -#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4)) -#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C) -#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80) -#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84) -#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88) -#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4)) - -/* Bit definitions and macros for MCF_DSPI_DMCR */ -#define MCF_DSPI_DMCR_HALT (0x00000001) -#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) -#define MCF_DSPI_DMCR_CRXF (0x00000400) -#define MCF_DSPI_DMCR_CTXF (0x00000800) -#define MCF_DSPI_DMCR_DRXF (0x00001000) -#define MCF_DSPI_DMCR_DTXF (0x00002000) -#define MCF_DSPI_DMCR_CSIS0 (0x00010000) -#define MCF_DSPI_DMCR_CSIS2 (0x00040000) -#define MCF_DSPI_DMCR_CSIS3 (0x00080000) -#define MCF_DSPI_DMCR_CSIS5 (0x00200000) -#define MCF_DSPI_DMCR_ROOE (0x01000000) -#define MCF_DSPI_DMCR_PCSSE (0x02000000) -#define MCF_DSPI_DMCR_MTFE (0x04000000) -#define MCF_DSPI_DMCR_FRZ (0x08000000) -#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) -#define MCF_DSPI_DMCR_CSCK (0x40000000) -#define MCF_DSPI_DMCR_MSTR (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DTCR */ -#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_DSPI_DCTARn */ -#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0) -#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) -#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) -#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) -#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) -#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) -#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) -#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) -#define MCF_DSPI_DCTAR_LSBFE (0x01000000) -#define MCF_DSPI_DCTAR_CPHA (0x02000000) -#define MCF_DSPI_DCTAR_CPOL (0x04000000) -/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */ -#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) -#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) -#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) -#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) -#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) -#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) -#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) -#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) -#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) -#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) -#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) -#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) -#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000) -#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000) -#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) -#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) -#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) - -/* Bit definitions and macros for MCF_DSPI_DSR */ -#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) -#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) -#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) -#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) -#define MCF_DSPI_DSR_RFDF (0x00020000) -#define MCF_DSPI_DSR_RFOF (0x00080000) -#define MCF_DSPI_DSR_TFFF (0x02000000) -#define MCF_DSPI_DSR_TFUF (0x08000000) -#define MCF_DSPI_DSR_EOQF (0x10000000) -#define MCF_DSPI_DSR_TXRXS (0x40000000) -#define MCF_DSPI_DSR_TCF (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DRSER */ -#define MCF_DSPI_DRSER_RFDFS (0x00010000) -#define MCF_DSPI_DRSER_RFDFE (0x00020000) -#define MCF_DSPI_DRSER_RFOFE (0x00080000) -#define MCF_DSPI_DRSER_TFFFS (0x01000000) -#define MCF_DSPI_DRSER_TFFFE (0x02000000) -#define MCF_DSPI_DRSER_TFUFE (0x08000000) -#define MCF_DSPI_DRSER_EOQFE (0x10000000) -#define MCF_DSPI_DRSER_TCFE (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DTFR */ -#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_DSPI_DTFR_CS0 (0x00010000) -#define MCF_DSPI_DTFR_CS2 (0x00040000) -#define MCF_DSPI_DTFR_CS3 (0x00080000) -#define MCF_DSPI_DTFR_CS5 (0x00200000) -#define MCF_DSPI_DTFR_CTCNT (0x04000000) -#define MCF_DSPI_DTFR_EOQ (0x08000000) -#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) -#define MCF_DSPI_DTFR_CONT (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DRFR */ -#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_DSPI_DTFDRn */ -#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_DSPI_DRFDRn */ -#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) - -/********************************************************************/ - -#endif /* _M5485DSPI_H_ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpio.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpio.h deleted file mode 100644 index 3ca4b8c393..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpio.h +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * File: mcf548x_gpio.h - * Purpose: Register and bit definitions for the MCF548X - * - * Notes: - * - */ - -#ifndef _M5485GPIO_H_ -#define _M5485GPIO_H_ - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00) -#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01) -#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02) -#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04) -#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05) -#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06) -#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07) -#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08) -#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09) -#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A) -#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C) -#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D) -#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E) -#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10) -#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11) -#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12) -#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14) -#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15) -#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16) -#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17) -#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18) -#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19) -#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A) -#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C) -#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D) -#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E) -#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20) -#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21) -#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22) -#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24) -#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25) -#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26) -#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27) -#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28) -#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29) -#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A) -#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C) -#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D) -#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E) -#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30) -#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31) -#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32) -#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34) -#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35) -#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36) -#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37) -#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38) -#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39) -#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A) -#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C) -#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D) -#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E) -#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40) -#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42) -#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43) -#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44) -#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48) -#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A) -#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C) -#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D) -#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E) -#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F) -#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50) -#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52) - -/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40) -#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ -#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02) -#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04) -#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08) -#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10) -#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ -#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01) -#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02) -#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04) -#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40) -#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40) -#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40) -#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40) -#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ -#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01) -#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02) -#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04) -#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08) -#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ -#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01) -#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02) -#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04) -#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08) -#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40) -#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40) -#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ -#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01) -#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02) -#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04) -#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08) -#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10) -#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20) -#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40) -#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ -#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02) -#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04) -#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08) -#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10) -#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ -#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01) -#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02) -#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04) -#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40) -#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40) -#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40) -#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40) -#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ -#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01) -#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02) -#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04) -#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08) -#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ -#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01) -#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02) -#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04) -#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08) -#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01) -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02) -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04) -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08) -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10) -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20) -#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ -#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ -#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01) -#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02) -#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04) -#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ -#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08) -#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40) -#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ -#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02) -#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04) -#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08) -#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10) -#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ -#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01) -#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02) -#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04) -#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40) -#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ -#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01) -#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02) -#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04) -#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08) -#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10) -#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20) -#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40) -#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ -#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01) -#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02) -#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04) -#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08) -#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10) -#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20) -#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40) -#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01) -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02) -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04) -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08) -#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10) -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20) -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40) -#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ -#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01) -#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02) -#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04) -#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08) -#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ -#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01) -#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02) -#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04) -#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08) -#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ -#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20) -#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01) -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02) -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04) -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08) -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10) -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20) -#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ -#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010) -#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) - -/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ -#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ -#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) - -/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ -#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) -#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) -#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ -#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) -#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ -#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) -#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ -#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) -#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ -#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) -#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) - -/********************************************************************/ - -#endif /* _M5485GPIO_H_ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpt.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpt.h deleted file mode 100644 index 27f716b875..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485gpt.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * File: mcf548x_gpt.h - * Purpose: Register and bit definitions for the MCF548X - * - * Notes: - * - */ - -#ifndef __MCF548X_GPT_H__ -#define __MCF548X_GPT_H__ - -/********************************************************************* -* -* General Purpose Timers (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT_GMS0 MCF_REG32(0x000800) -#define MCF_GPT_GCIR0 MCF_REG32(0x000804) -#define MCF_GPT_GPWM0 MCF_REG32(0x000808) -#define MCF_GPT_GSR0 MCF_REG32(0x00080C) -#define MCF_GPT_GMS1 MCF_REG32(0x000810) -#define MCF_GPT_GCIR1 MCF_REG32(0x000814) -#define MCF_GPT_GPWM1 MCF_REG32(0x000818) -#define MCF_GPT_GSR1 MCF_REG32(0x00081C) -#define MCF_GPT_GMS2 MCF_REG32(0x000820) -#define MCF_GPT_GCIR2 MCF_REG32(0x000824) -#define MCF_GPT_GPWM2 MCF_REG32(0x000828) -#define MCF_GPT_GSR2 MCF_REG32(0x00082C) -#define MCF_GPT_GMS3 MCF_REG32(0x000830) -#define MCF_GPT_GCIR3 MCF_REG32(0x000834) -#define MCF_GPT_GPWM3 MCF_REG32(0x000838) -#define MCF_GPT_GSR3 MCF_REG32(0x00083C) -#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010)) -#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010)) -#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010)) -#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010)) - -/* Bit definitions and macros for MCF_GPT_GMS */ -#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -#define MCF_GPT_GMS_IEN (0x00000100) -#define MCF_GPT_GMS_OD (0x00000200) -#define MCF_GPT_GMS_SC (0x00000400) -#define MCF_GPT_GMS_CE (0x00001000) -#define MCF_GPT_GMS_WDEN (0x00008000) -#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) -#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) -#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) -#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) -#define MCF_GPT_GMS_ICT_ANY (0x00000000) -#define MCF_GPT_GMS_ICT_RISE (0x00010000) -#define MCF_GPT_GMS_ICT_FALL (0x00020000) -#define MCF_GPT_GMS_ICT_PULSE (0x00030000) -#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) -#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) -#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) -#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) -#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) -#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) -#define MCF_GPT_GMS_TMS_PWM (0x00000003) -#define MCF_GPT_GMS_TMS_GPIO (0x00000004) - -/* Bit definitions and macros for MCF_GPT_GCIR */ -#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GPWM */ -#define MCF_GPT_GPWM_LOAD (0x00000001) -#define MCF_GPT_GPWM_PWMOP (0x00000100) -#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GSR */ -#define MCF_GPT_GSR_CAPT (0x00000001) -#define MCF_GPT_GSR_COMP (0x00000002) -#define MCF_GPT_GSR_PWMP (0x00000004) -#define MCF_GPT_GSR_TEXP (0x00000008) -#define MCF_GPT_GSR_PIN (0x00000100) -#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) - -#define MCF_GPT_MAX_TIMEOUT 30 -/********************************************************************/ - -#endif /* __MCF548X_GPT_H__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485pci.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485pci.h deleted file mode 100644 index 601b1d23ff..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485pci.h +++ /dev/null @@ -1,380 +0,0 @@ -/* - * m5485pci.h -- ColdFire 547x/548x PCI controller support. - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#ifndef __MCF548X_PCI_H__ -#define __MCF548X_PCI_H__ - - -/* PCI Type 0 Configuration Registers */ -#define MCF_PCIIDR MCF_REG32(0x000B00) -/* PCI Device ID/Vendor ID */ -#define MCF_PCISCR MCF_REG32(0x000B04) -/* PCI Status/Command */ -#define MCF_PCICCRIR MCF_REG32(0x000B08) -/* PCI Class Code / Revision ID */ -#define MCF_PCICR1 MCF_REG32(0x000B0C) -/* PCI Configuration 1 Register */ -#define MCF_PCIBAR0 MCF_REG32(0x000B10) -/* PCI Base Address Register 0 */ -#define MCF_PCIBAR1 MCF_REG32(0x000B14) -/* PCI Base Address Register 1 */ -#define MCF_PCICCPR MCF_REG32(0x000B28) -/* PCI Cardbus CIS Pointer */ -#define MCF_PCISID MCF_REG32(0x000B2C) -/* Subsystem ID/Subsystem Vendor ID*/ -#define MCF_PCIERBAR MCF_REG32(0x000B30) -/* PCI Expansion ROM */ -#define MCF_PCICPR MCF_REG32(0x000B30) -/* PCI Capabilities Pointer */ -#define MCF_PCICR2 MCF_REG32(0x000B3C) -/* PCI Configuration Register 2 */ - -/* General Control/Status Registers */ -#define MCF_PCIGSCR MCF_REG32(0x000B60) -/* Global Status/Control Register */ -#define MCF_PCITBATR0 MCF_REG32(0x000B64) -/* Target Base Address Translation 0*/ -#define MCF_PCITBATR1 MCF_REG32(0x000B68) -/* Target Base Address Translation 1*/ -#define MCF_PCITCR MCF_REG32(0x000B6C) -/* Target Control Register */ -#define MCF_PCIIW0BTAR MCF_REG32(0x000B70) -/* Initiator Window 0 Base Address */ -#define MCF_PCIIW1BTAR MCF_REG32(0x000B74) -/* Initiator Window 1 Base Address */ -#define MCF_PCIIW2BTAR MCF_REG32(0x000B78) -/* Initiator Window 2 Base Address */ -#define MCF_PCIIWCR MCF_REG32(0x000B80) -/* Initiator Window Configuration */ -#define MCF_PCIICR MCF_REG32(0x000B84) -/* Initiator Control Register */ -#define MCF_PCIISR MCF_REG32(0x000B88) -/* Initiator Status Register */ -#define MCF_PCICAR MCF_REG32(0x000BF8) -/* Configuration Address Register */ - -/* CommBus FIFO Transmit Interface Registers */ -#define MCF_PCITPSR MCF_REG32(0x008400) -/* Tx Packet Size Register */ -#define MCF_PCITSAR MCF_REG32(0x008404) -/* Tx Start Address Register */ -#define MCF_PCITTCR MCF_REG32(0x008408) -/* Tx Transaction Control Register */ -#define MCF_PCITER MCF_REG32(0x00840C) -/* Tx Enables Register */ -#define MCF_PCITNAR MCF_REG32(0x008410) -/* Tx Next Address Register */ -#define MCF_PCITLWR MCF_REG32(0x008414) -/* Tx Last Word Register */ -#define MCF_PCITDCR MCF_REG32(0x008418) -/* Tx Done Counts Register */ -#define MCF_PCITSR MCF_REG32(0x00841C) -/* Tx Status Register */ -#define MCF_PCITFDR MCF_REG32(0x008440) -/* Tx FIFO Data Register */ -#define MCF_PCITFSR MCF_REG32(0x008444) -/* Tx FIFO Status Register */ -#define MCF_PCITFCR MCF_REG32(0x008448) -/* Tx FIFO Control Register */ -#define MCF_PCITFAR MCF_REG32(0x00844C) -/* Tx FIFO Alarm Register */ -#define MCF_PCITFRPR MCF_REG32(0x008450) -/* Tx FIFO Read Pointer Register */ -#define MCF_PCITFWPR MCF_REG32(0x008454) -/* Tx FIFO Write Pointer Register */ - -/* CommBus FIFO Receive Interface Registers */ -#define MCF_PCIRPSR MCF_REG32(0x008480) -/* Tx Packet Size Register */ -#define MCF_PCIRSAR MCF_REG32(0x008484) -/* Tx Start Address Register */ -#define MCF_PCIRTCR MCF_REG32(0x008488) -/* Tx Transaction Control Register */ -#define MCF_PCIRER MCF_REG32(0x00848C) -/* Tx Enables Register */ -#define MCF_PCIRNAR MCF_REG32(0x008490) -/* Tx Next Address Register */ -#define MCF_PCIRDCR MCF_REG32(0x008498) -/* Tx Done Counts Register */ -#define MCF_PCIRSR MCF_REG32(0x00849C) -/* Tx Status Register */ -#define MCF_PCIRFDR MCF_REG32(0x0084C0) -/* Tx FIFO Data Register */ -#define MCF_PCIRFSR MCF_REG32(0x0084C4) -/* Tx FIFO Status Register */ -#define MCF_PCIRFCR MCF_REG32(0x0084C8) -/* Tx FIFO Control Register */ -#define MCF_PCIRFAR MCF_REG32(0x0084CC) -/* Tx FIFO Alarm Register */ -#define MCF_PCIRFRPR MCF_REG32(0x0084D0) -/* Tx FIFO Read Pointer Register */ -#define MCF_PCIRFWPR MCF_REG32(0x0084D4) -/* Tx FIFO Write Pointer Register */ - -/* PCI Arbiter Registers */ -#define MCF_PCIARB_PACR MCF_REG32(0x000C00) -#define MCF_PCIARB_PASR MCF_REG32(0x000C04) - - -/* Bit definitions and macros for MCF_PCIIDR */ -#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCISCR */ -#define MCF_PCISCR_M (0x00000002) -#define MCF_PCISCR_B (0x00000004) -#define MCF_PCISCR_SP (0x00000008) -#define MCF_PCISCR_MW (0x00000010) -#define MCF_PCISCR_PER (0x00000040) -#define MCF_PCISCR_S (0x00000100) -#define MCF_PCISCR_F (0x00000200) -#define MCF_PCISCR_C (0x00100000) -#define MCF_PCISCR_66M (0x00200000) -#define MCF_PCISCR_R (0x00400000) -#define MCF_PCISCR_FC (0x00800000) -#define MCF_PCISCR_DP (0x01000000) -#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25) -#define MCF_PCISCR_TS (0x08000000) -#define MCF_PCISCR_TR (0x10000000) -#define MCF_PCISCR_MA (0x20000000) -#define MCF_PCISCR_SE (0x40000000) -#define MCF_PCISCR_PE (0x80000000) - -/* Bit definitions and macros for MCF_PCICCRIR */ -#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) -#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) - -/* Bit definitions and macros for MCF_PCICR1 */ -#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) -#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) -#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) -#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCIBAR# */ -#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18) -#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_PCICR2 */ -#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) -#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) -#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) -#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCIGSCR */ -#define MCF_PCIGSCR_PR (0x00000001) -#define MCF_PCIGSCR_SEE (0x00001000) -#define MCF_PCIGSCR_PEE (0x00002000) -#define MCF_PCIGSCR_SE (0x10000000) -#define MCF_PCIGSCR_PE (0x20000000) - -/* Bit definitions and macros for MCF_PCITBATR0 */ -#define MCF_PCITBATR0_EN (0x00000001) -#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_PCITBATR1 */ -#define MCF_PCITBATR1_EN (0x00000001) -#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_PCITCR */ -#define MCF_PCITCR_P (0x00010000) -#define MCF_PCITCR_LD (0x01000000) - -/* Bit definitions and macros for MCF_PCIIW0BTAR */ -#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) -#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) -#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCIIW1BTAR */ -#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) -#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) -#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCIIW2BTAR */ -#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) -#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) -#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCIIWCR */ -#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) -#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) -#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) -#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) -#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) -#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) -#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000) -#define MCF_PCIIWCR_WINCTRL0_E (0x01000000) -#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) -#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) -#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) -#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000) -#define MCF_PCIIWCR_WINCTRL1_E (0x00010000) -#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) -#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) -#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) -#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900) -#define MCF_PCIIWCR_WINCTRL2_E (0x00000100) - - -/* Bit definitions and macros for MCF_PCIICR */ -#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) -#define MCF_PCIICR_TAE (0x01000000) -#define MCF_PCIICR_IAE (0x02000000) -#define MCF_PCIICR_REE (0x04000000) - -/* Bit definitions and macros for MCF_PCIISR */ -#define MCF_PCIISR_TA (0x01000000) -#define MCF_PCIISR_IA (0x02000000) -#define MCF_PCIISR_RE (0x04000000) - -/* Bit definitions and macros for MCF_PCICAR */ -#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) -#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) -#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) -#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) -#define MCF_PCICAR_E (0x80000000) - -/* Bit definitions and macros for MCF_PCITPSR */ -#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCITTCR */ -#define MCF_PCITTCR_DI (0x00000001) -#define MCF_PCITTCR_W (0x00000010) -#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_PCITER */ -#define MCF_PCITER_NE (0x00010000) -#define MCF_PCITER_IAE (0x00020000) -#define MCF_PCITER_TAE (0x00040000) -#define MCF_PCITER_RE (0x00080000) -#define MCF_PCITER_SE (0x00100000) -#define MCF_PCITER_FEE (0x00200000) -#define MCF_PCITER_ME (0x01000000) -#define MCF_PCITER_BE (0x08000000) -#define MCF_PCITER_CM (0x10000000) -#define MCF_PCITER_RF (0x40000000) -#define MCF_PCITER_RC (0x80000000) - -/* Bit definitions and macros for MCF_PCITDCR */ -#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCITSR */ -#define MCF_PCITSR_IA (0x00010000) -#define MCF_PCITSR_TA (0x00020000) -#define MCF_PCITSR_RE (0x00040000) -#define MCF_PCITSR_SE (0x00080000) -#define MCF_PCITSR_FE (0x00100000) -#define MCF_PCITSR_BE1 (0x00200000) -#define MCF_PCITSR_BE2 (0x00400000) -#define MCF_PCITSR_BE3 (0x00800000) -#define MCF_PCITSR_NT (0x01000000) - -/* Bit definitions and macros for MCF_PCITFSR */ -#define MCF_PCITFSR_EMT (0x00010000) -#define MCF_PCITFSR_ALARM (0x00020000) -#define MCF_PCITFSR_FU (0x00040000) -#define MCF_PCITFSR_FR (0x00080000) -#define MCF_PCITFSR_OF (0x00100000) -#define MCF_PCITFSR_UF (0x00200000) -#define MCF_PCITFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF_PCITFCR */ -#define MCF_PCITFCR_OF_MSK (0x00080000) -#define MCF_PCITFCR_UF_MSK (0x00100000) -#define MCF_PCITFCR_RXW_MSK (0x00200000) -#define MCF_PCITFCR_FAE_MSK (0x00400000) -#define MCF_PCITFCR_IP_MSK (0x00800000) -#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_PCITFAR */ -#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF_PCITFRPR */ -#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCITFWPR */ -#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCIRPSR */ -#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCIRTCR */ -#define MCF_PCIRTCR_DI (0x00000001) -#define MCF_PCIRTCR_W (0x00000010) -#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF_PCIRTCR_FB (0x00001000) -#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_PCIRER */ -#define MCF_PCIRER_NE (0x00010000) -#define MCF_PCIRER_IAE (0x00020000) -#define MCF_PCIRER_TAE (0x00040000) -#define MCF_PCIRER_RE (0x00080000) -#define MCF_PCIRER_SE (0x00100000) -#define MCF_PCIRER_FEE (0x00200000) -#define MCF_PCIRER_ME (0x01000000) -#define MCF_PCIRER_BE (0x08000000) -#define MCF_PCIRER_CM (0x10000000) -#define MCF_PCIRER_FE (0x20000000) -#define MCF_PCIRER_RF (0x40000000) -#define MCF_PCIRER_RC (0x80000000) - -/* Bit definitions and macros for MCF_PCIRDCR */ -#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCIRSR */ -#define MCF_PCIRSR_IA (0x00010000) -#define MCF_PCIRSR_TA (0x00020000) -#define MCF_PCIRSR_RE (0x00040000) -#define MCF_PCIRSR_SE (0x00080000) -#define MCF_PCIRSR_FE (0x00100000) -#define MCF_PCIRSR_BE1 (0x00200000) -#define MCF_PCIRSR_BE2 (0x00400000) -#define MCF_PCIRSR_BE3 (0x00800000) -#define MCF_PCIRSR_NT (0x01000000) - -/* Bit definitions and macros for MCF_PCIRFSR */ -#define MCF_PCIRFSR_EMT (0x00010000) -#define MCF_PCIRFSR_ALARM (0x00020000) -#define MCF_PCIRFSR_FU (0x00040000) -#define MCF_PCIRFSR_FR (0x00080000) -#define MCF_PCIRFSR_OF (0x00100000) -#define MCF_PCIRFSR_UF (0x00200000) -#define MCF_PCIRFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF_PCIRFCR */ -#define MCF_PCIRFCR_OF_MSK (0x00080000) -#define MCF_PCIRFCR_UF_MSK (0x00100000) -#define MCF_PCIRFCR_RXW_MSK (0x00200000) -#define MCF_PCIRFCR_FAE_MSK (0x00400000) -#define MCF_PCIRFCR_IP_MSK (0x00800000) -#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_PCIRFAR */ -#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF_PCIRFRPR */ -#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCIRFWPR */ -#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - - -/* Bit definitions and macros for MCF_PCIARB_PACR */ -#define MCF_PCIARB_PACR_INTMPRI (0x00000001) -#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) -#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) -#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) -#define MCF_PCIARB_PACR_PKMD (0x40000000) -#define MCF_PCIARB_PACR_DS (0x80000000) - -/* Bit definitions and macros for MCF_PCIARB_PASR */ -#define MCF_PCIARB_PASR_ITLMBK (0x00010000) -#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) - -#endif /* __MCF548X_PCI_H__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485psc.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485psc.h deleted file mode 100644 index 2aa6e9fd76..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485psc.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * File: mcf548x_psc.h - * Purpose: Register and bit definitions for the MCF548X - * - * Notes - * - */ - -#ifndef __MCF548X_PSC_H__ -#define __MCF548X_PSC_H__ - -/********************************************************************* -* -* Programmable Serial Controller (PSC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PSC_MR0 MCF_REG08(0x008600) -#define MCF_PSC_SR0 MCF_REG16(0x008604) -#define MCF_PSC_CSR0 MCF_REG08(0x008604) -#define MCF_PSC_CR0 MCF_REG08(0x008608) -#define MCF_PSC_RB0 MCF_REG32(0x00860C) -#define MCF_PSC_TB0 MCF_REG32(0x00860C) -#define MCF_PSC_TB_8BIT0 MCF_REG32(0x00860C) -#define MCF_PSC_TB_16BIT0 MCF_REG32(0x00860C) -#define MCF_PSC_TB_AC970 MCF_REG32(0x00860C) -#define MCF_PSC_IPCR0 MCF_REG08(0x008610) -#define MCF_PSC_ACR0 MCF_REG08(0x008610) -#define MCF_PSC_ISR0 MCF_REG16(0x008614) -#define MCF_PSC_IMR0 MCF_REG16(0x008614) -#define MCF_PSC_CTUR0 MCF_REG08(0x008618) -#define MCF_PSC_CTLR0 MCF_REG08(0x00861C) -#define MCF_PSC_IP0 MCF_REG08(0x008634) -#define MCF_PSC_OPSET0 MCF_REG08(0x008638) -#define MCF_PSC_OPRESET0 MCF_REG08(0x00863C) -#define MCF_PSC_SICR0 MCF_REG08(0x008640) -#define MCF_PSC_IRCR10 MCF_REG08(0x008644) -#define MCF_PSC_IRCR20 MCF_REG08(0x008648) -#define MCF_PSC_IRSDR0 MCF_REG08(0x00864C) -#define MCF_PSC_IRMDR0 MCF_REG08(0x008650) -#define MCF_PSC_IRFDR0 MCF_REG08(0x008654) -#define MCF_PSC_RFCNT0 MCF_REG16(0x008658) -#define MCF_PSC_TFCNT0 MCF_REG16(0x00865C) -#define MCF_PSC_RFSR0 MCF_REG16(0x008664) -#define MCF_PSC_TFSR0 MCF_REG16(0x008684) -#define MCF_PSC_RFCR0 MCF_REG32(0x008668) -#define MCF_PSC_TFCR0 MCF_REG32(0x008688) -#define MCF_PSC_RFAR0 MCF_REG16(0x00866E) -#define MCF_PSC_TFAR0 MCF_REG16(0x00868E) -#define MCF_PSC_RFRP0 MCF_REG16(0x008672) -#define MCF_PSC_TFRP0 MCF_REG16(0x008692) -#define MCF_PSC_RFWP0 MCF_REG16(0x008676) -#define MCF_PSC_TFWP0 MCF_REG16(0x008696) -#define MCF_PSC_RLRFP0 MCF_REG16(0x00867A) -#define MCF_PSC_TLRFP0 MCF_REG16(0x00869A) -#define MCF_PSC_RLWFP0 MCF_REG16(0x00867E) -#define MCF_PSC_TLWFP0 MCF_REG16(0x00869E) -#define MCF_PSC_MR1 MCF_REG08(0x008700) -#define MCF_PSC_SR1 MCF_REG16(0x008704) -#define MCF_PSC_CSR1 MCF_REG08(0x008704) -#define MCF_PSC_CR1 MCF_REG08(0x008708) -#define MCF_PSC_RB1 MCF_REG32(0x00870C) -#define MCF_PSC_TB1 MCF_REG32(0x00870C) -#define MCF_PSC_TB_8BIT1 MCF_REG32(0x00870C) -#define MCF_PSC_TB_16BIT1 MCF_REG32(0x00870C) -#define MCF_PSC_TB_AC971 MCF_REG32(0x00870C) -#define MCF_PSC_IPCR1 MCF_REG08(0x008710) -#define MCF_PSC_ACR1 MCF_REG08(0x008710) -#define MCF_PSC_ISR1 MCF_REG16(0x008714) -#define MCF_PSC_IMR1 MCF_REG16(0x008714) -#define MCF_PSC_CTUR1 MCF_REG08(0x008718) -#define MCF_PSC_CTLR1 MCF_REG08(0x00871C) -#define MCF_PSC_IP1 MCF_REG08(0x008734) -#define MCF_PSC_OPSET1 MCF_REG08(0x008738) -#define MCF_PSC_OPRESET1 MCF_REG08(0x00873C) -#define MCF_PSC_SICR1 MCF_REG08(0x008740) -#define MCF_PSC_IRCR11 MCF_REG08(0x008744) -#define MCF_PSC_IRCR21 MCF_REG08(0x008748) -#define MCF_PSC_IRSDR1 MCF_REG08(0x00874C) -#define MCF_PSC_IRMDR1 MCF_REG08(0x008750) -#define MCF_PSC_IRFDR1 MCF_REG08(0x008754) -#define MCF_PSC_RFCNT1 MCF_REG16(0x008758) -#define MCF_PSC_TFCNT1 MCF_REG16(0x00875C) -#define MCF_PSC_RFSR1 MCF_REG16(0x008764) -#define MCF_PSC_TFSR1 MCF_REG16(0x008784) -#define MCF_PSC_RFCR1 MCF_REG32(0x008768) -#define MCF_PSC_TFCR1 MCF_REG32(0x008788) -#define MCF_PSC_RFAR1 MCF_REG16(0x00876E) -#define MCF_PSC_TFAR1 MCF_REG16(0x00878E) -#define MCF_PSC_RFRP1 MCF_REG16(0x008772) -#define MCF_PSC_TFRP1 MCF_REG16(0x008792) -#define MCF_PSC_RFWP1 MCF_REG16(0x008776) -#define MCF_PSC_TFWP1 MCF_REG16(0x008796) -#define MCF_PSC_RLRFP1 MCF_REG16(0x00877A) -#define MCF_PSC_TLRFP1 MCF_REG16(0x00879A) -#define MCF_PSC_RLWFP1 MCF_REG16(0x00877E) -#define MCF_PSC_TLWFP1 MCF_REG16(0x00879E) -#define MCF_PSC_MR2 MCF_REG08(0x008800) -#define MCF_PSC_SR2 MCF_REG16(0x008804) -#define MCF_PSC_CSR2 MCF_REG08(0x008804) -#define MCF_PSC_CR2 MCF_REG08(0x008808) -#define MCF_PSC_RB2 MCF_REG32(0x00880C) -#define MCF_PSC_TB2 MCF_REG32(0x00880C) -#define MCF_PSC_TB_8BIT2 MCF_REG32(0x00880C) -#define MCF_PSC_TB_16BIT2 MCF_REG32(0x00880C) -#define MCF_PSC_TB_AC972 MCF_REG32(0x00880C) -#define MCF_PSC_IPCR2 MCF_REG08(0x008810) -#define MCF_PSC_ACR2 MCF_REG08(0x008810) -#define MCF_PSC_ISR2 MCF_REG16(0x008814) -#define MCF_PSC_IMR2 MCF_REG16(0x008814) -#define MCF_PSC_CTUR2 MCF_REG08(0x008818) -#define MCF_PSC_CTLR2 MCF_REG08(0x00881C) -#define MCF_PSC_IP2 MCF_REG08(0x008834) -#define MCF_PSC_OPSET2 MCF_REG08(0x008838) -#define MCF_PSC_OPRESET2 MCF_REG08(0x00883C) -#define MCF_PSC_SICR2 MCF_REG08(0x008840) -#define MCF_PSC_IRCR12 MCF_REG08(0x008844) -#define MCF_PSC_IRCR22 MCF_REG08(0x008848) -#define MCF_PSC_IRSDR2 MCF_REG08(0x00884C) -#define MCF_PSC_IRMDR2 MCF_REG08(0x008850) -#define MCF_PSC_IRFDR2 MCF_REG08(0x008854) -#define MCF_PSC_RFCNT2 MCF_REG16(0x008858) -#define MCF_PSC_TFCNT2 MCF_REG16(0x00885C) -#define MCF_PSC_RFSR2 MCF_REG16(0x008864) -#define MCF_PSC_TFSR2 MCF_REG16(0x008884) -#define MCF_PSC_RFCR2 MCF_REG32(0x008868) -#define MCF_PSC_TFCR2 MCF_REG32(0x008888) -#define MCF_PSC_RFAR2 MCF_REG16(0x00886E) -#define MCF_PSC_TFAR2 MCF_REG16(0x00888E) -#define MCF_PSC_RFRP2 MCF_REG16(0x008872) -#define MCF_PSC_TFRP2 MCF_REG16(0x008892) -#define MCF_PSC_RFWP2 MCF_REG16(0x008876) -#define MCF_PSC_TFWP2 MCF_REG16(0x008896) -#define MCF_PSC_RLRFP2 MCF_REG16(0x00887A) -#define MCF_PSC_TLRFP2 MCF_REG16(0x00889A) -#define MCF_PSC_RLWFP2 MCF_REG16(0x00887E) -#define MCF_PSC_TLWFP2 MCF_REG16(0x00889E) -#define MCF_PSC_MR3 MCF_REG08(0x008900) -#define MCF_PSC_SR3 MCF_REG16(0x008904) -#define MCF_PSC_CSR3 MCF_REG08(0x008904) -#define MCF_PSC_CR3 MCF_REG08(0x008908) -#define MCF_PSC_RB3 MCF_REG32(0x00890C) -#define MCF_PSC_TB3 MCF_REG32(0x00890C) -#define MCF_PSC_TB_8BIT3 MCF_REG32(0x00890C) -#define MCF_PSC_TB_16BIT3 MCF_REG32(0x00890C) -#define MCF_PSC_TB_AC973 MCF_REG32(0x00890C) -#define MCF_PSC_IPCR3 MCF_REG08(0x008910) -#define MCF_PSC_ACR3 MCF_REG08(0x008910) -#define MCF_PSC_ISR3 MCF_REG16(0x008914) -#define MCF_PSC_IMR3 MCF_REG16(0x008914) -#define MCF_PSC_CTUR3 MCF_REG08(0x008918) -#define MCF_PSC_CTLR3 MCF_REG08(0x00891C) -#define MCF_PSC_IP3 MCF_REG08(0x008934) -#define MCF_PSC_OPSET3 MCF_REG08(0x008938) -#define MCF_PSC_OPRESET3 MCF_REG08(0x00893C) -#define MCF_PSC_SICR3 MCF_REG08(0x008940) -#define MCF_PSC_IRCR13 MCF_REG08(0x008944) -#define MCF_PSC_IRCR23 MCF_REG08(0x008948) -#define MCF_PSC_IRSDR3 MCF_REG08(0x00894C) -#define MCF_PSC_IRMDR3 MCF_REG08(0x008950) -#define MCF_PSC_IRFDR3 MCF_REG08(0x008954) -#define MCF_PSC_RFCNT3 MCF_REG16(0x008958) -#define MCF_PSC_TFCNT3 MCF_REG16(0x00895C) -#define MCF_PSC_RFSR3 MCF_REG16(0x008964) -#define MCF_PSC_TFSR3 MCF_REG16(0x008984) -#define MCF_PSC_RFCR3 MCF_REG32(0x008968) -#define MCF_PSC_TFCR3 MCF_REG32(0x008988) -#define MCF_PSC_RFAR3 MCF_REG16(0x00896E) -#define MCF_PSC_TFAR3 MCF_REG16(0x00898E) -#define MCF_PSC_RFRP3 MCF_REG16(0x008972) -#define MCF_PSC_TFRP3 MCF_REG16(0x008992) -#define MCF_PSC_RFWP3 MCF_REG16(0x008976) -#define MCF_PSC_TFWP3 MCF_REG16(0x008996) -#define MCF_PSC_RLRFP3 MCF_REG16(0x00897A) -#define MCF_PSC_TLRFP3 MCF_REG16(0x00899A) -#define MCF_PSC_RLWFP3 MCF_REG16(0x00897E) -#define MCF_PSC_TLWFP3 MCF_REG16(0x00899E) -#define MCF_PSC_MR(x) MCF_REG08(0x008600+((x)*0x100)) -#define MCF_PSC_SR(x) MCF_REG16(0x008604+((x)*0x100)) -#define MCF_PSC_CSR(x) MCF_REG08(0x008604+((x)*0x100)) -#define MCF_PSC_CR(x) MCF_REG08(0x008608+((x)*0x100)) -#define MCF_PSC_RB(x) MCF_REG32(0x00860C+((x)*0x100)) -#define MCF_PSC_TB(x) MCF_REG32(0x00860C+((x)*0x100)) -#define MCF_PSC_TB_8BIT(x) MCF_REG32(0x00860C+((x)*0x100)) -#define MCF_PSC_TB_16BIT(x) MCF_REG32(0x00860C+((x)*0x100)) -#define MCF_PSC_TB_AC97(x) MCF_REG32(0x00860C+((x)*0x100)) -#define MCF_PSC_IPCR(x) MCF_REG08(0x008610+((x)*0x100)) -#define MCF_PSC_ACR(x) MCF_REG08(0x008610+((x)*0x100)) -#define MCF_PSC_ISR(x) MCF_REG16(0x008614+((x)*0x100)) -#define MCF_PSC_IMR(x) MCF_REG16(0x008614+((x)*0x100)) -#define MCF_PSC_CTUR(x) MCF_REG08(0x008618+((x)*0x100)) -#define MCF_PSC_CTLR(x) MCF_REG08(0x00861C+((x)*0x100)) -#define MCF_PSC_IP(x) MCF_REG08(0x008634+((x)*0x100)) -#define MCF_PSC_OPSET(x) MCF_REG08(0x008638+((x)*0x100)) -#define MCF_PSC_OPRESET(x) MCF_REG08(0x00863C+((x)*0x100)) -#define MCF_PSC_SICR(x) MCF_REG08(0x008640+((x)*0x100)) -#define MCF_PSC_IRCR1(x) MCF_REG08(0x008644+((x)*0x100)) -#define MCF_PSC_IRCR2(x) MCF_REG08(0x008648+((x)*0x100)) -#define MCF_PSC_IRSDR(x) MCF_REG08(0x00864C+((x)*0x100)) -#define MCF_PSC_IRMDR(x) MCF_REG08(0x008650+((x)*0x100)) -#define MCF_PSC_IRFDR(x) MCF_REG08(0x008654+((x)*0x100)) -#define MCF_PSC_RFCNT(x) MCF_REG16(0x008658+((x)*0x100)) -#define MCF_PSC_TFCNT(x) MCF_REG16(0x00865C+((x)*0x100)) -#define MCF_PSC_RFSR(x) MCF_REG16(0x008664+((x)*0x100)) -#define MCF_PSC_TFSR(x) MCF_REG16(0x008684+((x)*0x100)) -#define MCF_PSC_RFCR(x) MCF_REG32(0x008668+((x)*0x100)) -#define MCF_PSC_TFCR(x) MCF_REG32(0x008688+((x)*0x100)) -#define MCF_PSC_RFAR(x) MCF_REG16((0x00866E)+((x)*0x100)) -#define MCF_PSC_TFAR(x) MCF_REG16((0x00868E)+((x)*0x100)) -#define MCF_PSC_RFRP(x) MCF_REG16(0x008672+((x)*0x100)) -#define MCF_PSC_TFRP(x) MCF_REG16(0x008692+((x)*0x100)) -#define MCF_PSC_RFWP(x) MCF_REG16(0x008676+((x)*0x100)) -#define MCF_PSC_TFWP(x) MCF_REG16(0x008696+((x)*0x100)) -#define MCF_PSC_RLRFP(x) MCF_REG16(0x00867A+((x)*0x100)) -#define MCF_PSC_TLRFP(x) MCF_REG16(0x00869A+((x)*0x100)) -#define MCF_PSC_RLWFP(x) MCF_REG16(0x00867E+((x)*0x100)) -#define MCF_PSC_TLWFP(x) MCF_REG16(0x00869E+((x)*0x100)) - -/* Bit definitions and macros for MCF_PSC_MR */ -#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) -#define MCF_PSC_MR_PT (0x04) -#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) -#define MCF_PSC_MR_ERR (0x20) -#define MCF_PSC_MR_RXIRQ (0x40) -#define MCF_PSC_MR_RXRTS (0x80) -#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) -#define MCF_PSC_MR_TXCTS (0x10) -#define MCF_PSC_MR_TXRTS (0x20) -#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) -#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) -#define MCF_PSC_MR_PM_MULTI_DATA (0x18) -#define MCF_PSC_MR_PM_NONE (0x10) -#define MCF_PSC_MR_PM_FORCE_HI (0x0C) -#define MCF_PSC_MR_PM_FORCE_LO (0x08) -#define MCF_PSC_MR_PM_ODD (0x04) -#define MCF_PSC_MR_PM_EVEN (0x00) -#define MCF_PSC_MR_BC_5 (0x00) -#define MCF_PSC_MR_BC_6 (0x01) -#define MCF_PSC_MR_BC_7 (0x02) -#define MCF_PSC_MR_BC_8 (0x03) -#define MCF_PSC_MR_CM_NORMAL (0x00) -#define MCF_PSC_MR_CM_ECHO (0x40) -#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) -#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) -#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) -#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) -#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_PSC_SR */ -#define MCF_PSC_SR_ERR (0x0040) -#define MCF_PSC_SR_CDE_DEOF (0x0080) -#define MCF_PSC_SR_RXRDY (0x0100) -#define MCF_PSC_SR_FU (0x0200) -#define MCF_PSC_SR_TXRDY (0x0400) -#define MCF_PSC_SR_TXEMP_URERR (0x0800) -#define MCF_PSC_SR_OE (0x1000) -#define MCF_PSC_SR_PE_CRCERR (0x2000) -#define MCF_PSC_SR_FE_PHYERR (0x4000) -#define MCF_PSC_SR_RB_NEOF (0x8000) - -/* Bit definitions and macros for MCF_PSC_CSR */ -#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) -#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) -#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) -#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) -#define MCF_PSC_CSR_RCSEL_CTM (0xF0) -#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) -#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) -#define MCF_PSC_CSR_TCSEL_CTM (0x0F) - -/* Bit definitions and macros for MCF_PSC_CR */ -#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) -#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) -#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) -#define MCF_PSC_CR_NONE (0x00) -#define MCF_PSC_CR_STOP_BREAK (0x70) -#define MCF_PSC_CR_START_BREAK (0x60) -#define MCF_PSC_CR_BKCHGINT (0x50) -#define MCF_PSC_CR_RESET_ERROR (0x40) -#define MCF_PSC_CR_RESET_TX (0x30) -#define MCF_PSC_CR_RESET_RX (0x20) -#define MCF_PSC_CR_RESET_MR (0x10) -#define MCF_PSC_CR_TX_DISABLED (0x08) -#define MCF_PSC_CR_TX_ENABLED (0x04) -#define MCF_PSC_CR_RX_DISABLED (0x02) -#define MCF_PSC_CR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_PSC_TB_8BIT */ -#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) -#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) -#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) -#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PSC_TB_16BIT */ -#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PSC_TB_AC97 */ -#define MCF_PSC_TB_AC97_SOF (0x00000800) -#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) - -/* Bit definitions and macros for MCF_PSC_IPCR */ -#define MCF_PSC_IPCR_RESERVED (0x0C) -#define MCF_PSC_IPCR_CTS (0x0D) -#define MCF_PSC_IPCR_D_CTS (0x1C) -#define MCF_PSC_IPCR_SYNC (0x8C) - -/* Bit definitions and macros for MCF_PSC_ACR */ -#define MCF_PSC_ACR_IEC0 (0x01) -#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) -#define MCF_PSC_ACR_BRG (0x80) - -/* Bit definitions and macros for MCF_PSC_ISR */ -#define MCF_PSC_ISR_ERR (0x0040) -#define MCF_PSC_ISR_DEOF (0x0080) -#define MCF_PSC_ISR_TXRDY (0x0100) -#define MCF_PSC_ISR_RXRDY_FU (0x0200) -#define MCF_PSC_ISR_DB (0x0400) -#define MCF_PSC_ISR_IPC (0x8000) - -/* Bit definitions and macros for MCF_PSC_IMR */ -#define MCF_PSC_IMR_ERR (0x0040) -#define MCF_PSC_IMR_DEOF (0x0080) -#define MCF_PSC_IMR_TXRDY (0x0100) -#define MCF_PSC_IMR_RXRDY_FU (0x0200) -#define MCF_PSC_IMR_DB (0x0400) -#define MCF_PSC_IMR_IPC (0x8000) - -/* Bit definitions and macros for MCF_PSC_IP */ -#define MCF_PSC_IP_CTS (0x01) -#define MCF_PSC_IP_TGL (0x40) -#define MCF_PSC_IP_LWPR_B (0x80) - -/* Bit definitions and macros for MCF_PSC_OPSET */ -#define MCF_PSC_OPSET_RTS (0x01) - -/* Bit definitions and macros for MCF_PSC_OPRESET */ -#define MCF_PSC_OPRESET_RTS (0x01) - -/* Bit definitions and macros for MCF_PSC_SICR */ -#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) -#define MCF_PSC_SICR_SHDIR (0x10) -#define MCF_PSC_SICR_DTS (0x20) -#define MCF_PSC_SICR_AWR (0x40) -#define MCF_PSC_SICR_ACRB (0x80) -#define MCF_PSC_SICR_SIM_UART (0x00) -#define MCF_PSC_SICR_SIM_MODEM8 (0x01) -#define MCF_PSC_SICR_SIM_MODEM16 (0x02) -#define MCF_PSC_SICR_SIM_AC97 (0x03) -#define MCF_PSC_SICR_SIM_SIR (0x04) -#define MCF_PSC_SICR_SIM_MIR (0x05) -#define MCF_PSC_SICR_SIM_FIR (0x06) - -/* Bit definitions and macros for MCF_PSC_IRCR1 */ -#define MCF_PSC_IRCR1_SPUL (0x01) -#define MCF_PSC_IRCR1_SIPEN (0x02) -#define MCF_PSC_IRCR1_FD (0x04) - -/* Bit definitions and macros for MCF_PSC_IRCR2 */ -#define MCF_PSC_IRCR2_NXTEOF (0x01) -#define MCF_PSC_IRCR2_ABORT (0x02) -#define MCF_PSC_IRCR2_SIPREQ (0x04) - -/* Bit definitions and macros for MCF_PSC_IRMDR */ -#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) -#define MCF_PSC_IRMDR_FREQ (0x80) - -/* Bit definitions and macros for MCF_PSC_IRFDR */ -#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_PSC_RFCNT */ -#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFCNT */ -#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFSR */ -#define MCF_PSC_RFSR_EMT (0x0001) -#define MCF_PSC_RFSR_ALARM (0x0002) -#define MCF_PSC_RFSR_FU (0x0004) -#define MCF_PSC_RFSR_FRMRY (0x0008) -#define MCF_PSC_RFSR_OF (0x0010) -#define MCF_PSC_RFSR_UF (0x0020) -#define MCF_PSC_RFSR_RXW (0x0040) -#define MCF_PSC_RFSR_FAE (0x0080) -#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF_PSC_RFSR_TAG (0x1000) -#define MCF_PSC_RFSR_TXW (0x4000) -#define MCF_PSC_RFSR_IP (0x8000) -#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) -#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) -#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) -#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF_PSC_TFSR */ -#define MCF_PSC_TFSR_EMT (0x0001) -#define MCF_PSC_TFSR_ALARM (0x0002) -#define MCF_PSC_TFSR_FU (0x0004) -#define MCF_PSC_TFSR_FRMRY (0x0008) -#define MCF_PSC_TFSR_OF (0x0010) -#define MCF_PSC_TFSR_UF (0x0020) -#define MCF_PSC_TFSR_RXW (0x0040) -#define MCF_PSC_TFSR_FAE (0x0080) -#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF_PSC_TFSR_TAG (0x1000) -#define MCF_PSC_TFSR_TXW (0x4000) -#define MCF_PSC_TFSR_IP (0x8000) -#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) -#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) -#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) -#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF_PSC_RFCR */ -#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_RFCR_TXW_MSK (0x00040000) -#define MCF_PSC_RFCR_OF_MSK (0x00080000) -#define MCF_PSC_RFCR_UF_MSK (0x00100000) -#define MCF_PSC_RFCR_RXW_MSK (0x00200000) -#define MCF_PSC_RFCR_FAE_MSK (0x00400000) -#define MCF_PSC_RFCR_IP_MSK (0x00800000) -#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_PSC_RFCR_FRMEN (0x08000000) -#define MCF_PSC_RFCR_TIMER (0x10000000) -#define MCF_PSC_RFCR_WRITETAG (0x20000000) -#define MCF_PSC_RFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF_PSC_TFCR */ -#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_TFCR_TXW_MSK (0x00040000) -#define MCF_PSC_TFCR_OF_MSK (0x00080000) -#define MCF_PSC_TFCR_UF_MSK (0x00100000) -#define MCF_PSC_TFCR_RXW_MSK (0x00200000) -#define MCF_PSC_TFCR_FAE_MSK (0x00400000) -#define MCF_PSC_TFCR_IP_MSK (0x00800000) -#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_PSC_TFCR_FRMEN (0x08000000) -#define MCF_PSC_TFCR_TIMER (0x10000000) -#define MCF_PSC_TFCR_WRITETAG (0x20000000) -#define MCF_PSC_TFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF_PSC_RFAR */ -#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFAR */ -#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFRP */ -#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFRP */ -#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFWP */ -#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFWP */ -#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RLRFP */ -#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TLRFP */ -#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RLWFP */ -#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TLWFP */ -#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) - -/********************************************************************/ - -#endif /* __MCF548X_PSC_H__ */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sec.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sec.h deleted file mode 100644 index b7a99c8056..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sec.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef M5485SEC_H -#define M5484SEC_H - -#define SEC_EUACR_U MCF_REG32(0x21000) -#define SEC_EUACR_L MCF_REG32(0x21004) -#define SEC_EUASR_U MCF_REG32(0x21028) -#define SEC_EUASR_L MCF_REG32(0x2102C) -#define SEC_SMCR MCF_REG32(0x21030) -#define SEC_SISR_U MCF_REG32(0x21010) -#define SEC_SISR_L MCF_REG32(0x21014) -#define SEC_SICR_U MCF_REG32(0x21018) -#define SEC_SICR_L MCF_REG32(0x2101C) -#define SEC_SIMR_U MCF_REG32(0x21008) -#define SEC_SIMR_L MCF_REG32(0x2100C) -#define SEC_SID MCF_REG32(0x21020) - -#define SEC_SMCR_RESET 0x01000000 -#define SEC_SIMR_MASK_U 0x00000000 -#define SEC_SIMR_MASK_L 0x03333340 - -#define SEC_CC0_FR MCF_REG32(0x2204C) -#define SEC_CC0_CR MCF_REG32(0x2200C) -#define SEC_CC0_CDPR MCF_REG32(0x22044) -#define SEC_CC0_PSR_U MCF_REG32(0x22010) -#define SEC_CC0_PSR_L MCF_REG32(0x22014) -#define SEC_CC1_FR MCF_REG32(0x2304C) -#define SEC_CC1_CR MCF_REG32(0x2300C) -#define SEC_CC1_CDPR MCF_REG32(0x23044) -#define SEC_CC1_PSR_U MCF_REG32(0x23010) -#define SEC_CC1_PSR_L MCF_REG32(0x23014) - -#define SEC_CC_CR_RESET 0x00000001 -#define SEC_CC_CR_CONFIGURATION 0x0000001E -#define SEC_CC_PSR_U_ERR_CH0 0x20000000 -#define SEC_CC_PSR_U_ERR_CH1 0x80000000 -#define SEC_CC_PSR_U_DN_CH0 0x10000000 -#define SEC_CC_PSR_U_DN_CH1 0x40000000 - -#define SEC_DEU_DRCR MCF_REG32(0x2A018) -#define SEC_DEU_DSR MCF_REG32(0x2A028) -#define SEC_DEU_DISR MCF_REG32(0x2A030) -#define SEC_DEU_DIMR MCF_REG32(0x2A038) - -#define SEC_DEU_DRCR_RESET 0x01000000 -#define SEC_DEU_DSR_RD 0x01000000 -#define SEC_DEU_DIMR_MASK 0xF63F0000 - -#define SEC_AFEU_AFRCR MCF_REG32(0x28018) -#define SEC_AFEU_AFSR MCF_REG32(0x28028) -#define SEC_AFEU_AFISR MCF_REG32(0x28030) -#define SEC_AFEU_AFIMR MCF_REG32(0x28038) - -#define SEC_AFEU_AFRCR_RESET 0x01000000 -#define SEC_AFEU_AFSR_RD 0x01000000 -#define SEC_AFEU_AFIMR_MASK 0xF61F0000 - - -#define SEC_MDEU_MDRCR MCF_REG32(0x2C018) -#define SEC_MDEU_MDSR MCF_REG32(0x2C028) -#define SEC_MDEU_MDISR MCF_REG32(0x2C030) -#define SEC_MDEU_MDIMR MCF_REG32(0x2C038) - -#define SEC_MDEU_MDRCR_RESET 0x01000000 -#define SEC_MDEU_MDSR_RD 0x01000000 -#define SEC_MDEU_MDIMR_MASK 0xC41F0000 - - -#define SEC_RNG_RNGRCR MCF_REG32(0x2E018) -#define SEC_RNG_RNGSR MCF_REG32(0x2E028) -#define SEC_RNG_RNGISR MCF_REG32(0x2E030) -#define SEC_RNG_RNGIMR MCF_REG32(0x2E038) - -#define SEC_RNG_RNGRCR_RESET 0x01000000 -#define SEC_RNG_RNGSR_RD 0x01000000 -#define SEC_RNG_RNGIMR_MASK 0xC2100000 - -#define SEC_AESU_AESRCR MCF_REG32(0x32018) -#define SEC_AESU_AESSR MCF_REG32(0x32028) -#define SEC_AESU_AESISR MCF_REG32(0x32030) -#define SEC_AESU_AESIMR MCF_REG32(0x32038) - -#define SEC_AESU_AESRCR_RESET 0x01000000 -#define SEC_AESU_AESSR_RD 0x01000000 -#define SEC_AESU_AESIMR_MASK 0xF61F0000 - - -#define SEC_DESC_NUM 20 -#define SEC_CHANNEL_NUMBER 2 -#define SEC_MAX_BUF_SIZE 32*1024 -#define SEC_INIT_TIMEOUT 1*HZ -#define SEC_INTERRUPT 37 - -/* Header descriptor values*/ -#define SEC_ALG_ENCR_DES_ECB_SINGLE 0x20100010 -#define SEC_ALG_DECR_DES_ECB_SINGLE 0x20000010 -#define SEC_ALG_ENCR_DES_ECB_TRIPLE 0x20300010 -#define SEC_ALG_DECR_DES_ECB_TRIPLE 0x20200010 -#define SEC_ALG_ENCR_DES_CBC_SINGLE 0x20500010 -#define SEC_ALG_DECR_DES_CBC_SINGLE 0x20400010 -#define SEC_ALG_ENCR_DES_CBC_TRIPLE 0x20700010 -#define SEC_ALG_DECR_DES_CBC_TRIPLE 0x20600010 - -#define SEC_ALG_MDEU_SHA256 0x30500010 -#define SEC_ALG_MDEU_MD5 0x30600010 -#define SEC_ALG_MDEU_SHA 0x30400010 -#define SEC_ALG_MDEU_SHA256_HMAC 0x31D00010 -#define SEC_ALG_MDEU_MD5_HMAC 0x31E00010 -#define SEC_ALG_MDEU_SHA_HMAC 0x31C00010 - -#define SEC_ALG_RNG 0x40000010 - - -#define SEC_ALG_AFEU_KEY 0x10200050 -#define SEC_ALG_AFEU_CONTEXT 0x10700050 - -#define SEC_ALG_ENCR_AESU_CBC 0x60300010 -#define SEC_ALG_DECR_AESU_CBC 0x60200010 -#define SEC_ALG_ENCR_AESU_ECB 0x60100010 -#define SEC_ALG_DECR_AESU_ECB 0x60000010 -#define SEC_ALG_AESU_CTR 0x60600010 - - - -#define SEC_DESCHEAD_ERROR 0xFE000000 -#define SEC_DESCHEAD_COMPLETED 0xFF000000 - -#define SEC_DEVICE_NAME "cfsec" - -/*!!! This number must be changed*/ -#define SEC_MAJOR 130 - -#define SEC_DEV_BUF 1024 -#define SEC_DEV_KEY_LEN 64 -#define SEC_DEV_VECTOR_LEN 259 - -#define SEC_AES_BLCK_LEN 16 -#define SEC_DES_BLCK_LEN 8 - - -/* Descriptor structure of SEC*/ -struct sec_descriptor { - volatile unsigned long secdesc_header; - unsigned long secdesc_len1; - void *secdesc_ptr1; - unsigned long secdesc_iv_in_len; - void *secdesc_iv_in_ptr; - unsigned long secdesc_key_len; - void *secdesc_key_ptr; - unsigned long secdesc_data_in_len; - void *secdesc_data_in_ptr; - unsigned long secdesc_data_out_len; - void *secdesc_data_out_ptr; - unsigned long secdesc_iv_out_len; - void *secdesc_iv_out_ptr; - unsigned long secdesc_len7; - void *secdesc_ptr7; - void *secdesc_ptrnext; -}; - -struct sec_device_data { - unsigned char secdev_inbuf[SEC_DEV_BUF]; - unsigned char secdev_outbuf[SEC_DEV_BUF]; - unsigned char secdev_key[SEC_DEV_KEY_LEN]; - unsigned char secdev_iv[SEC_DEV_VECTOR_LEN]; - unsigned char secdev_ov[SEC_DEV_VECTOR_LEN]; - struct sec_descriptor *secdev_desc; -}; - -struct sec_descriptor *sec_desc_alloc(void); -inline void sec_desc_free(struct sec_descriptor *desc); -int sec_execute(int channel, struct sec_descriptor *desc, int timeout); -int sec_nonblock_execute(struct sec_descriptor *desc); -#endif diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sim.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sim.h deleted file mode 100644 index 53984019da..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sim.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * m5485sim.h -- ColdFire 547x/548x System Integration Unit support. - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#ifndef m5485sim_h -#define m5485sim_h -/* - * System Integration Unit Registers - */ -#define MCF_SDRAMDS MCF_REG32(0x000004) -/* SDRAM Drive Strength */ -#define MCF_SBCR MCF_REG32(0x000010) -/* System Breakpoint Control */ -#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4)) -/* SDRAM Chip Select X */ -#define MCF_SECSACR MCF_REG32(0x000038) -/* Sequential Access Control */ -#define MCF_RSR MCF_REG32(0x000044) -/* Reset Status */ -#define MCF_JTAGID MCF_REG32(0x000050) -/* JTAG Device Identification */ -#define MCF_XARB_PRIEN MCF_REG32(0x000264) -/* Arbiter master pri enable */ -#define MCF_XARB_PRI MCF_REG32(0x000268) -/* Arbiter master pri levels */ - -/* - * FlexBus Chip Selects Registers - */ -#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC)) -#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC)) -#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC)) - -/* - * Interrupt Controller Registers - */ -#define MCF_IPRH MCF_REG32(0x000700) -#define MCF_IPRL MCF_REG32(0x000704) -#define MCF_IMRH MCF_REG32(0x000708) -#define MCF_IMRL MCF_REG32(0x00070C) -#define MCF_INTFRCH MCF_REG32(0x000710) -#define MCF_INTFRCL MCF_REG32(0x000714) -#define MCF_IRLR MCF_REG08(0x000718) -#define MCF_IACKLPR MCF_REG08(0x000719) -#define MCF_SWIACK MCF_REG08(0x0007E0) -#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004)) -#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001)) - -/* - * Slice Timers Registers - */ -#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010)) -#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010)) -#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010)) -#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010)) - -/* - * Interrupt sources - */ -#define ISC_EPORT_Fn(x) (x) -/* EPORT Interrupts */ -#define ISC_USB_EPn(x) (15+(x)) -/* USB Endopint */ -#define ISC_USB_ISR (22) -/* USB General source */ -#define ISC_USB_AISR (22) -/* USB core source */ -#define ISC_DSPI_OVRFW (25) -/* DSPI overflow */ -#define ISC_DSPI_RFOF (26) -#define ISC_DSPI_RFDF (27) -#define ISC_DSPI_TFUF (28) -#define ISC_DSPI_TCF (29) -#define ISC_DSPI_TFFF (30) -#define ISC_DSPI_EOQF (31) -#define ISC_PSCn(x) (35-(x)) -#define ISC_COMM_TIM (36) -#define ISC_SEC (37) -#define ISC_FEC1 (38) -#define ISC_FEC0 (39) -#define ISC_I2C (40) -#define ISC_PCI_ARB (41) -#define ISC_PCI_CB (42) -#define ISC_PCI_XLB (43) -#define ISC_DMA (48) -#define ISC_CANn_ERR(x) (49+(6*(x))) -#define ISC_CANn_BUSOFF(x) (50+(6*(x))) -#define ISC_CANn_MBOR(x) (51+(6*(x))) -#define ISC_CAN0_WAKEIN (52) -#define ISC_SLTn(x) (54-(x)) -#define ISC_GPTn(x) (62-(x)) - -/* - * Interrupt level and priorities - */ -#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3)) -#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2)) -#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1)) -#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0)) -#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7)) -#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6)) -#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5)) -#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4)) -#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3)) -#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2)) -#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1)) - -#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x))) -#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7)) -#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6)) -#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5)) -#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4)) -#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3)) -#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2)) -#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1)) -#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0)) - -#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7)) -#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6)) -#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5)) -#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4)) -#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3)) -#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2)) -#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1)) -#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0)) - -#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7)) -#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3))) -#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3)) -#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2)) -#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1)) -#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0)) - - - - - -/********************************************************************/ - -/* - * System Integration Unit Bitfields - */ - -/* SBCR */ -#define MCF_SBCR_PIN2DSPI (0x08000000) -#define MCF_SBCR_DMA2CPU (0x10000000) -#define MCF_SBCR_CPU2DMA (0x20000000) -#define MCF_SBCR_PIN2DMA (0x40000000) -#define MCF_SBCR_PIN2CPU (0x80000000) - -/* SECSACR */ -#define MCF_SECSACR_SEQEN (0x00000001) - -/* RSR */ -#define MCF_RSR_RST (0x00000001) -#define MCF_RSR_RSTWD (0x00000002) -#define MCF_RSR_RSTJTG (0x00000008) - -/* JTAGID */ -#define MCF_JTAGID_REV (0xF0000000) -#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF) -#define MCF_JTAGID_MCF5485 (0x0800C01D) -#define MCF_JTAGID_MCF5484 (0x0800D01D) -#define MCF_JTAGID_MCF5483 (0x0800E01D) -#define MCF_JTAGID_MCF5482 (0x0800F01D) -#define MCF_JTAGID_MCF5481 (0x0801001D) -#define MCF_JTAGID_MCF5480 (0x0801101D) -#define MCF_JTAGID_MCF5475 (0x0801201D) -#define MCF_JTAGID_MCF5474 (0x0801301D) -#define MCF_JTAGID_MCF5473 (0x0801401D) -#define MCF_JTAGID_MCF5472 (0x0801501D) -#define MCF_JTAGID_MCF5471 (0x0801601D) -#define MCF_JTAGID_MCF5470 (0x0801701D) - - -/* - * Interrupt Controller Bitfields - */ -#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1) -#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4) -#define MCF_ICR_IP(x) (((x)&0x07)<<0) -#define MCF_ICR_IL(x) (((x)&0x07)<<3) - -/* - * Slice Timers Bitfields - */ -#define MCF_SCR_TEN (0x01000000) -#define MCF_SCR_IEN (0x02000000) -#define MCF_SCR_RUN (0x04000000) -#define MCF_SSR_ST (0x01000000) -#define MCF_SSR_BE (0x02000000) - - -/* - * Some needed coldfire registers - */ -#define MCF_PAR_PCIBG MCF_REG16(0x000A48) -#define MCF_PAR_PCIBR MCF_REG16(0x000A4A) -#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3)) -#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44) -#define MCF_PAR_DSPI MCF_REG16(0x000A50) -#define MCF_PAR_TIMER MCF_REG08(0X000A52) -#define MCF_EPPAR MCF_REG16(0x000F00) -#define MCF_EPDDR MCF_REG08(0x000F04) -#define MCF_EPIER MCF_REG08(0x000F05) -#define MCF_EPFR MCF_REG08(0x000F0C) - -/* - * Some GPIO bitfields - */ -#define MCF_PAR_SDA (0x0008) -#define MCF_PAR_SCL (0x0004) -#define MCF_PAR_PSC_TXD (0x04) -#define MCF_PAR_PSC_RXD (0x08) -#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) -#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) -#define MCF_PAR_PSC_CTS_GPIO (0x00) -#define MCF_PAR_PSC_CTS_BCLK (0x80) -#define MCF_PAR_PSC_CTS_CTS (0xC0) -#define MCF_PAR_PSC_RTS_GPIO (0x00) -#define MCF_PAR_PSC_RTS_FSYNC (0x20) -#define MCF_PAR_PSC_RTS_RTS (0x30) -#define MCF_PAR_PSC_CANRX (0x40) - -/* - * FlexCAN Module Configuration Register - */ -#define CANMCR_MDIS (0x80000000) -#define CANMCR_FRZ (0x40000000) -#define CANMCR_HALT (0x10000000) -#define CANMCR_SOFTRST (0x02000000) -#define CANMCR_NOTRDY (0x08000000) -#define CANMCR_FRZACK (0x01000000) -#define CANMCR_SUPV (0x00800000) -#define CANMCR_MAXMB (0x0F) -/* - * FlexCAN Control Register - */ -#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) -#define CANCTRL_RJW(x) (((x)&0x03)<<22) -#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) -#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) -#define CANCTRL_BOFFMSK (0x00008000) -#define CANCTRL_ERRMSK (0x00004000) -#define CANCTRL_CLKSRC (0x00002000) -#define CANCTRL_LPB (0x00001000) -#define CANCTRL_SAMP(x) (((x)&0x01)<<7) -#define CANCTRL_BOFFREC (0x00000040) -#define CANCTRL_TSYNC (0x00000020) -#define CANCTRL_LBUF (0x00000010) -#define CANCTRL_LOM (0x00000008) -#define CANCTRL_PROPSEG(x) ((x)&0x07) - -/* - * FlexCAN Error Counter Register - */ -#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) -#define ERRCNT_TXECTR(x) ((x)&0xFF) - -/* - * FlexCAN Error and Status Register - */ -#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) -#define ERRSTAT_ACKERR (0x00002000) -#define ERRSTAT_CRCERR (0x00001000) -#define ERRSTAT_FRMERR (0x00000800) -#define ERRSTAT_STFERR (0x00000400) -#define ERRSTAT_TXWRN (0x00000200) -#define ERRSTAT_RXWRN (0x00000100) -#define ERRSTAT_IDLE (0x00000080) -#define ERRSTAT_TXRX (0x00000040) -#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) -#define ERRSTAT_BOFFINT (0x00000004) -#define ERRSTAT_ERRINT (0x00000002) - -/* - * Interrupt Mask Register - */ -#define IMASK_BUF15M (0x8000) -#define IMASK_BUF14M (0x4000) -#define IMASK_BUF13M (0x2000) -#define IMASK_BUF12M (0x1000) -#define IMASK_BUF11M (0x0800) -#define IMASK_BUF10M (0x0400) -#define IMASK_BUF9M (0x0200) -#define IMASK_BUF8M (0x0100) -#define IMASK_BUF7M (0x0080) -#define IMASK_BUF6M (0x0040) -#define IMASK_BUF5M (0x0020) -#define IMASK_BUF4M (0x0010) -#define IMASK_BUF3M (0x0008) -#define IMASK_BUF2M (0x0004) -#define IMASK_BUF1M (0x0002) -#define IMASK_BUF0M (0x0001) -#define IMASK_BUFnM(x) (0x1<<(x)) -#define IMASK_BUFF_ENABLE_ALL (0xFFFF) -#define IMASK_BUFF_DISABLE_ALL (0x0000) - -/* - * Interrupt Flag Register - */ -#define IFLAG_BUF15M (0x8000) -#define IFLAG_BUF14M (0x4000) -#define IFLAG_BUF13M (0x2000) -#define IFLAG_BUF12M (0x1000) -#define IFLAG_BUF11M (0x0800) -#define IFLAG_BUF10M (0x0400) -#define IFLAG_BUF9M (0x0200) -#define IFLAG_BUF8M (0x0100) -#define IFLAG_BUF7M (0x0080) -#define IFLAG_BUF6M (0x0040) -#define IFLAG_BUF5M (0x0020) -#define IFLAG_BUF4M (0x0010) -#define IFLAG_BUF3M (0x0008) -#define IFLAG_BUF2M (0x0004) -#define IFLAG_BUF1M (0x0002) -#define IFLAG_BUF0M (0x0001) -#define IFLAG_BUFF_SET_ALL (0xFFFF) -#define IFLAG_BUFF_CLEAR_ALL (0x0000) -#define IFLAG_BUFnM(x) (0x1<<(x)) - -/* - * Message Buffers - */ -#define MB_CNT_CODE(x) (((x)&0x0F)<<24) -#define MB_CNT_SRR (0x00400000) -#define MB_CNT_IDE (0x00200000) -#define MB_CNT_RTR (0x00100000) -#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) -#define MB_ID_STD (0x07FF) -#define MB_ID_EXT (0x1FFFFFFF) -#define MB_CODE_MASK (0xF0FFFFFF) -#define CAN_MB 16 -#define PDEV_MAX 2 - -/* - * Some used coldfire values - */ -#define MCF_EPIER_EPIE(x) (0x01 << (x)) -#define MCF_EPPAR_EPPAx_FALLING (2) -#define MCF_EPPAR_EPPA(n, x) (((x)&0x0003) << (2*n)) - - -#endif /* m5485sim_h */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sram.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sram.h deleted file mode 100644 index 95627ae0eb..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sram.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef SYS_SRAM_H -#define SYS_SRAM_H - - -#define SYS_SRAM_DMA_START (MCF_MBAR + 0x10000) -#define SYS_SRAM_DMA_SIZE 8192 -#define SYS_SRAM_FEC_START (SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE) -#define SYS_SRAM_FEC_SIZE 2048 -#define SYS_SRAM_SEC_START (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE) -#define SYS_SRAM_SEC_SIZE 1280 - -#endif /* SYS_SRAM_H */ diff --git a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/mcffec.h b/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/mcffec.h deleted file mode 100644 index 4581f9e43e..0000000000 --- a/target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/mcffec.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved. - * Author: Chenghu Wu <b16972@freescale.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#ifndef __MCFFEC_H__ -#define __MCFFEC_H -#include <linux/netdevice.h> -#include <linux/etherdevice.h> -#include <linux/skbuff.h> -#include <linux/spinlock.h> -#include <linux/workqueue.h> -#include <linux/platform_device.h> -#include <asm/pgtable.h> - -/* The FEC stores dest/src/type, data, and checksum for receive packets. - */ -#define PKT_MAXBUF_SIZE 1518 - -/* - * The 5270/5271/5280/5282/532x RX control register also contains maximum frame - * size bits. Other FEC hardware does not, so we need to take that into - * account when setting it. - */ -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ - defined(CONFIG_M537x) || defined(CONFIG_M5301x) || \ - defined(CONFIG_M5445X) -#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) -#else -#define OPT_FRAME_SIZE 0 -#endif -/* - * Some hardware gets it MAC address out of local flash memory. - * if this is non-zero then assume it is the address to get MAC from. - */ -#if defined(CONFIG_NETtel) -#define FEC_FLASHMAC 0xf0006006 -#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) -#define FEC_FLASHMAC 0xf0006000 -#elif defined(CONFIG_CANCam) -#define FEC_FLASHMAC 0xf0020000 -#elif defined(CONFIG_M5272C3) -#define FEC_FLASHMAC (0xffe04000 + 4) -#elif defined(CONFIG_MOD5272) -#define FEC_FLASHMAC 0xffc0406b -#else -#define FEC_FLASHMAC 0 -#endif - -#ifdef CONFIG_FEC_DMA_USE_SRAM -#define TX_RING_SIZE 8 /* Must be power of two */ -#define TX_RING_MOD_MASK 7 /* for this to work */ -#else -#define TX_RING_SIZE 16 /* Must be power of two */ -#define TX_RING_MOD_MASK 15 /* for this to work */ -#endif - -typedef struct fec { - unsigned long fec_reserved0; - unsigned long fec_ievent; /* Interrupt event reg */ - unsigned long fec_imask; /* Interrupt mask reg */ - unsigned long fec_reserved1; - unsigned long fec_r_des_active; /* Receive descriptor reg */ - unsigned long fec_x_des_active; /* Transmit descriptor reg */ - unsigned long fec_reserved2[3]; - unsigned long fec_ecntrl; /* Ethernet control reg */ - unsigned long fec_reserved3[6]; - unsigned long fec_mii_data; /* MII manage frame reg */ - unsigned long fec_mii_speed; /* MII speed control reg */ - unsigned long fec_reserved4[7]; - unsigned long fec_mib_ctrlstat; /* MIB control/status reg */ - unsigned long fec_reserved5[7]; - unsigned long fec_r_cntrl; /* Receive control reg */ - unsigned long fec_reserved6[15]; - unsigned long fec_x_cntrl; /* Transmit Control reg */ - unsigned long fec_reserved7[7]; - unsigned long fec_addr_low; /* Low 32bits MAC address */ - unsigned long fec_addr_high; /* High 16bits MAC address */ - unsigned long fec_opd; /* Opcode + Pause duration */ - unsigned long fec_reserved8[10]; - unsigned long fec_hash_table_high; /* High 32bits hash table */ - unsigned long fec_hash_table_low; /* Low 32bits hash table */ - unsigned long fec_grp_hash_table_high;/* High 32bits hash table */ - unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */ - unsigned long fec_reserved9[7]; - unsigned long fec_x_wmrk; /* FIFO transmit water mark */ - unsigned long fec_reserved10; - unsigned long fec_r_bound; /* FIFO receive bound reg */ - unsigned long fec_r_fstart; /* FIFO receive start reg */ - unsigned long fec_reserved11[11]; - unsigned long fec_r_des_start; /* Receive descriptor ring */ - unsigned long fec_x_des_start; /* Transmit descriptor ring */ - unsigned long fec_r_buff_size; /* Maximum receive buff size */ -} fec_t; - -/* - * Define the buffer descriptor structure. - */ -typedef struct bufdesc { - unsigned short cbd_sc; /* Control and status info */ - unsigned short cbd_datlen; /* Data length */ - unsigned long cbd_bufaddr; /* Buffer address */ -} cbd_t; - -/* Forward declarations of some structures to support different PHYs - */ -typedef struct { - uint mii_data; - void (*funct)(uint mii_reg, struct net_device *dev); -} phy_cmd_t; - -typedef struct { - uint id; - char *name; - - const phy_cmd_t *config; - const phy_cmd_t *startup; - const phy_cmd_t *ack_int; - const phy_cmd_t *shutdown; -} phy_info_t; - -/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and - * tx_bd_base always point to the base of the buffer descriptors. The - * cur_rx and cur_tx point to the currently available buffer. - * The dirty_tx tracks the current buffer that is being sent by the - * controller. The cur_tx and dirty_tx are equal under both completely - * empty and completely full conditions. The empty/ready indicator in - * the buffer descriptor determines the actual condition. - */ -struct fec_enet_private { - /* Hardware registers of the FEC device */ - volatile fec_t *hwp; - - struct net_device *netdev; - struct platform_device *pdev; - /* The saved address of a sent-in-place packet/buffer, for skfree(). */ - unsigned char *tx_bounce[TX_RING_SIZE]; - struct sk_buff *tx_skbuff[TX_RING_SIZE]; - ushort skb_cur; - ushort skb_dirty; - - /* CPM dual port RAM relative addresses. - */ - cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ - cbd_t *tx_bd_base; - cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ - cbd_t *dirty_tx; /* The ring entries to be free()ed. */ - uint tx_full; - /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ - spinlock_t hw_lock; - - /* hold while accessing the mii_list_t() elements */ - spinlock_t mii_lock; - struct mii_bus *mdio_bus; - struct phy_device *phydev; - - uint phy_id; - uint phy_id_done; - uint phy_status; - uint phy_speed; - phy_info_t const *phy; - struct work_struct phy_task; - volatile fec_t *phy_hwp; - - uint sequence_done; - uint mii_phy_task_queued; - - uint phy_addr; - - int index; - int opened; - int link; - int old_link; - int full_duplex; - int duplex; - int speed; - int msg_enable; -}; - -struct fec_platform_private { - struct platform_device *pdev; - - unsigned long quirks; - int num_slots; /* Slots on controller */ - struct fec_enet_private *fep_host[0]; /* Pointers to hosts */ -}; - -#endif |