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-rw-r--r--target/linux/brcm63xx/patches-3.3/007-MIPS-BCM63XX-remove-SPI2-register.patch83
1 files changed, 0 insertions, 83 deletions
diff --git a/target/linux/brcm63xx/patches-3.3/007-MIPS-BCM63XX-remove-SPI2-register.patch b/target/linux/brcm63xx/patches-3.3/007-MIPS-BCM63XX-remove-SPI2-register.patch
deleted file mode 100644
index cafef10dbb..0000000000
--- a/target/linux/brcm63xx/patches-3.3/007-MIPS-BCM63XX-remove-SPI2-register.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 32511e7dfab9b9cabe2772e3f5430559294a8d1c Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Wed, 25 Jan 2012 17:40:01 +0100
-Subject: [PATCH 09/63] MIPS: BCM63XX: remove SPI2 register
-
-This register was introduced with the support of the BCM6368 CPU in the idea
-that its internal layout was different from the other CPUs SPI controller.
-The controller is actually the same as the one present on BCM6358 so we can
-remove this register and use the usual SPI register instead.
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
----
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +---------
- 1 files changed, 1 insertions(+), 9 deletions(-)
-
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -102,7 +102,6 @@ enum bcm63xx_regs_set {
- RSET_UART1,
- RSET_GPIO,
- RSET_SPI,
-- RSET_SPI2,
- RSET_UDC0,
- RSET_OHCI0,
- RSET_OHCI_PRIV,
-@@ -166,7 +165,6 @@ enum bcm63xx_regs_set {
- #define BCM_6338_UART1_BASE (0xdeadbeef)
- #define BCM_6338_GPIO_BASE (0xfffe0400)
- #define BCM_6338_SPI_BASE (0xfffe0c00)
--#define BCM_6338_SPI2_BASE (0xdeadbeef)
- #define BCM_6338_UDC0_BASE (0xdeadbeef)
- #define BCM_6338_USBDMA_BASE (0xfffe2400)
- #define BCM_6338_OHCI0_BASE (0xdeadbeef)
-@@ -210,7 +208,6 @@ enum bcm63xx_regs_set {
- #define BCM_6345_UART1_BASE (0xdeadbeef)
- #define BCM_6345_GPIO_BASE (0xfffe0400)
- #define BCM_6345_SPI_BASE (0xdeadbeef)
--#define BCM_6345_SPI2_BASE (0xdeadbeef)
- #define BCM_6345_UDC0_BASE (0xdeadbeef)
- #define BCM_6345_USBDMA_BASE (0xfffe2800)
- #define BCM_6345_ENET0_BASE (0xfffe1800)
-@@ -253,7 +250,6 @@ enum bcm63xx_regs_set {
- #define BCM_6348_UART1_BASE (0xdeadbeef)
- #define BCM_6348_GPIO_BASE (0xfffe0400)
- #define BCM_6348_SPI_BASE (0xfffe0c00)
--#define BCM_6348_SPI2_BASE (0xdeadbeef)
- #define BCM_6348_UDC0_BASE (0xfffe1000)
- #define BCM_6348_OHCI0_BASE (0xfffe1b00)
- #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
-@@ -294,7 +290,6 @@ enum bcm63xx_regs_set {
- #define BCM_6358_UART1_BASE (0xfffe0120)
- #define BCM_6358_GPIO_BASE (0xfffe0080)
- #define BCM_6358_SPI_BASE (0xfffe0800)
--#define BCM_6358_SPI2_BASE (0xfffe0800)
- #define BCM_6358_UDC0_BASE (0xfffe0800)
- #define BCM_6358_OHCI0_BASE (0xfffe1400)
- #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
-@@ -335,8 +330,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_UART0_BASE (0xb0000100)
- #define BCM_6368_UART1_BASE (0xb0000120)
- #define BCM_6368_GPIO_BASE (0xb0000080)
--#define BCM_6368_SPI_BASE (0xdeadbeef)
--#define BCM_6368_SPI2_BASE (0xb0000800)
-+#define BCM_6368_SPI_BASE (0xb0000800)
- #define BCM_6368_UDC0_BASE (0xdeadbeef)
- #define BCM_6368_OHCI0_BASE (0xb0001600)
- #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
-@@ -383,7 +377,6 @@ extern const unsigned long *bcm63xx_regs
- __GEN_RSET_BASE(__cpu, UART1) \
- __GEN_RSET_BASE(__cpu, GPIO) \
- __GEN_RSET_BASE(__cpu, SPI) \
-- __GEN_RSET_BASE(__cpu, SPI2) \
- __GEN_RSET_BASE(__cpu, UDC0) \
- __GEN_RSET_BASE(__cpu, OHCI0) \
- __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
-@@ -422,7 +415,6 @@ extern const unsigned long *bcm63xx_regs
- [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
- [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
- [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
-- [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
- [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
- [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
- [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \