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Diffstat (limited to 'target/linux/ar71xx/files/arch/mips')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c48
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/irq.c24
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb750.c16
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h22
4 files changed, 55 insertions, 55 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c b/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
index 137a018156..abd7747267 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
@@ -30,15 +30,15 @@ void __ar71xx_gpio_set_value(unsigned gpio, int value)
void __iomem *base = ar71xx_gpio_base;
if (value)
- __raw_writel(1 << gpio, base + GPIO_REG_SET);
+ __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
else
- __raw_writel(1 << gpio, base + GPIO_REG_CLEAR);
+ __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
}
EXPORT_SYMBOL(__ar71xx_gpio_set_value);
int __ar71xx_gpio_get_value(unsigned gpio)
{
- return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1;
+ return (__raw_readl(ar71xx_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
}
EXPORT_SYMBOL(__ar71xx_gpio_get_value);
@@ -61,8 +61,8 @@ static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset),
- base + GPIO_REG_OE);
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
+ base + AR71XX_GPIO_REG_OE);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
@@ -78,12 +78,12 @@ static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
if (value)
- __raw_writel(1 << offset, base + GPIO_REG_SET);
+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
else
- __raw_writel(1 << offset, base + GPIO_REG_CLEAR);
+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
- __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset),
- base + GPIO_REG_OE);
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
+ base + AR71XX_GPIO_REG_OE);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
@@ -98,8 +98,8 @@ static int ar934x_gpio_direction_input(struct gpio_chip *chip,
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset),
- base + GPIO_REG_OE);
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
+ base + AR71XX_GPIO_REG_OE);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
@@ -115,12 +115,12 @@ static int ar934x_gpio_direction_output(struct gpio_chip *chip,
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
if (value)
- __raw_writel(1 << offset, base + GPIO_REG_SET);
+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
else
- __raw_writel(1 << offset, base + GPIO_REG_CLEAR);
+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
- __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset),
- base + GPIO_REG_OE);
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
+ base + AR71XX_GPIO_REG_OE);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
@@ -144,10 +144,10 @@ void ar71xx_gpio_function_enable(u32 mask)
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask,
- base + GPIO_REG_FUNC);
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
+ base + AR71XX_GPIO_REG_FUNC);
/* flush write */
- (void) __raw_readl(base + GPIO_REG_FUNC);
+ (void) __raw_readl(base + AR71XX_GPIO_REG_FUNC);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
@@ -159,10 +159,10 @@ void ar71xx_gpio_function_disable(u32 mask)
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask,
- base + GPIO_REG_FUNC);
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
+ base + AR71XX_GPIO_REG_FUNC);
/* flush write */
- (void) __raw_readl(base + GPIO_REG_FUNC);
+ (void) __raw_readl(base + AR71XX_GPIO_REG_FUNC);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
@@ -174,10 +174,10 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear)
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
- __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set,
- base + GPIO_REG_FUNC);
+ __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
+ base + AR71XX_GPIO_REG_FUNC);
/* flush write */
- (void) __raw_readl(base + GPIO_REG_FUNC);
+ (void) __raw_readl(base + AR71XX_GPIO_REG_FUNC);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
index c4297d399a..6d744daefa 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
@@ -28,8 +28,8 @@ static void ar71xx_gpio_irq_dispatch(void)
void __iomem *base = ar71xx_gpio_base;
u32 pending;
- pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
- __raw_readl(base + GPIO_REG_INT_ENABLE);
+ pending = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING) &
+ __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
if (pending)
do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
@@ -43,11 +43,11 @@ static void ar71xx_gpio_irq_unmask(struct irq_data *d)
void __iomem *base = ar71xx_gpio_base;
u32 t;
- t = __raw_readl(base + GPIO_REG_INT_ENABLE);
- __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
+ t = __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+ __raw_writel(t | (1 << irq), base + AR71XX_GPIO_REG_INT_ENABLE);
/* flush write */
- (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
+ (void) __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
}
static void ar71xx_gpio_irq_mask(struct irq_data *d)
@@ -56,11 +56,11 @@ static void ar71xx_gpio_irq_mask(struct irq_data *d)
void __iomem *base = ar71xx_gpio_base;
u32 t;
- t = __raw_readl(base + GPIO_REG_INT_ENABLE);
- __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
+ t = __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
+ __raw_writel(t & ~(1 << irq), base + AR71XX_GPIO_REG_INT_ENABLE);
/* flush write */
- (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
+ (void) __raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE);
}
static struct irq_chip ar71xx_gpio_irq_chip = {
@@ -82,14 +82,14 @@ static void __init ar71xx_gpio_irq_init(void)
void __iomem *base = ar71xx_gpio_base;
int i;
- __raw_writel(0, base + GPIO_REG_INT_ENABLE);
- __raw_writel(0, base + GPIO_REG_INT_PENDING);
+ __raw_writel(0, base + AR71XX_GPIO_REG_INT_ENABLE);
+ __raw_writel(0, base + AR71XX_GPIO_REG_INT_PENDING);
/* setup type of all GPIO interrupts to level sensitive */
- __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
+ __raw_writel(GPIO_INT_ALL, base + AR71XX_GPIO_REG_INT_TYPE);
/* setup polarity of all GPIO interrupts to active high */
- __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
+ __raw_writel(GPIO_INT_ALL, base + AR71XX_GPIO_REG_INT_POLARITY);
for (i = AR71XX_GPIO_IRQ_BASE;
i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb750.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb750.c
index ea1f089c22..9b63dc3688 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb750.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-rb750.c
@@ -81,24 +81,24 @@ int rb750_latch_change(u32 mask_clr, u32 mask_set)
latch_clr = (latch_clr | mask_clr) & ~mask_set;
if (latch_oe == 0)
- latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE);
+ latch_oe = __raw_readl(ar71xx_gpio_base + AR71XX_GPIO_REG_OE);
if (likely(latch_set & RB750_LVC573_LE)) {
void __iomem *base = ar71xx_gpio_base;
- t = __raw_readl(base + GPIO_REG_OE);
+ t = __raw_readl(base + AR71XX_GPIO_REG_OE);
t |= mask_clr | latch_oe | mask_set;
- __raw_writel(t, base + GPIO_REG_OE);
- __raw_writel(latch_clr, base + GPIO_REG_CLEAR);
- __raw_writel(latch_set, base + GPIO_REG_SET);
+ __raw_writel(t, base + AR71XX_GPIO_REG_OE);
+ __raw_writel(latch_clr, base + AR71XX_GPIO_REG_CLEAR);
+ __raw_writel(latch_set, base + AR71XX_GPIO_REG_SET);
} else if (mask_clr & RB750_LVC573_LE) {
void __iomem *base = ar71xx_gpio_base;
- latch_oe = __raw_readl(base + GPIO_REG_OE);
- __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR);
+ latch_oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
+ __raw_writel(RB750_LVC573_LE, base + AR71XX_GPIO_REG_CLEAR);
/* flush write */
- __raw_readl(base + GPIO_REG_CLEAR);
+ __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
}
ret = 1;
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 91f382480a..a83b0460b0 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -418,17 +418,17 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
/*
* GPIO block
*/
-#define GPIO_REG_OE 0x00
-#define GPIO_REG_IN 0x04
-#define GPIO_REG_OUT 0x08
-#define GPIO_REG_SET 0x0c
-#define GPIO_REG_CLEAR 0x10
-#define GPIO_REG_INT_MODE 0x14
-#define GPIO_REG_INT_TYPE 0x18
-#define GPIO_REG_INT_POLARITY 0x1c
-#define GPIO_REG_INT_PENDING 0x20
-#define GPIO_REG_INT_ENABLE 0x24
-#define GPIO_REG_FUNC 0x28
+#define AR71XX_GPIO_REG_OE 0x00
+#define AR71XX_GPIO_REG_IN 0x04
+#define AR71XX_GPIO_REG_OUT 0x08
+#define AR71XX_GPIO_REG_SET 0x0c
+#define AR71XX_GPIO_REG_CLEAR 0x10
+#define AR71XX_GPIO_REG_INT_MODE 0x14
+#define AR71XX_GPIO_REG_INT_TYPE 0x18
+#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
+#define AR71XX_GPIO_REG_INT_PENDING 0x20
+#define AR71XX_GPIO_REG_INT_ENABLE 0x24
+#define AR71XX_GPIO_REG_FUNC 0x28
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)