diff options
Diffstat (limited to 'package/kernel/mac80211/patches/300-pending_work.patch')
| -rw-r--r-- | package/kernel/mac80211/patches/300-pending_work.patch | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/300-pending_work.patch b/package/kernel/mac80211/patches/300-pending_work.patch index 5ffcf63378..6d1bc806c0 100644 --- a/package/kernel/mac80211/patches/300-pending_work.patch +++ b/package/kernel/mac80211/patches/300-pending_work.patch @@ -1,3 +1,33 @@ +commit 0fecedddd4a0945873db1bd230ec6a168b3cc4fe +Author: Felix Fietkau <nbd@openwrt.org> +Date: Mon Sep 8 18:35:08 2014 +0200 + + ath9k_hw: reduce ANI spur immunity setting on HT40 extension channel + + The cycpwr_thr1 value needs to be lower on the extension channel than on + the control channel, similar to how the register settings are programmed + in the initvals. + + Also drop the unnecessary check for HT40 - this register can always be + written. This patch has been reported to improve HT40 stability and + throughput in some environments. + + Signed-off-by: Felix Fietkau <nbd@openwrt.org> + +commit 30d7434ccb853b96de698a040888fa4dacd0cc19 +Author: Felix Fietkau <nbd@openwrt.org> +Date: Mon Sep 8 18:31:26 2014 +0200 + + Revert "ath9k_hw: reduce ANI firstep range for older chips" + + This reverts commit 09efc56345be4146ab9fc87a55c837ed5d6ea1ab + + I've received reports that this change is decreasing throughput in some + rare conditions on an AR9280 based device + + Cc: stable@vger.kernel.org + Signed-off-by: Felix Fietkau <nbd@openwrt.org> + commit 15ed54948f508ad1baad79c30050e2d29a21696d Author: Felix Fietkau <nbd@openwrt.org> Date: Fri Jul 25 16:18:03 2014 +0200 @@ -3109,3 +3139,30 @@ Date: Mon May 19 21:20:49 2014 +0200 if (!compat) compat = &sdata->vif.bss_conf.chandef; +--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c ++++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c +@@ -1004,9 +1004,11 @@ static bool ar5008_hw_ani_control_new(st + case ATH9K_ANI_FIRSTEP_LEVEL:{ + u32 level = param; + +- value = level; ++ value = level * 2; + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, + AR_PHY_FIND_SIG_FIRSTEP, value); ++ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, ++ AR_PHY_FIND_SIG_FIRSTEP_LOW, value); + + if (level != aniState->firstepLevel) { + ath_dbg(common, ANI, +@@ -1040,9 +1042,8 @@ static bool ar5008_hw_ani_control_new(st + REG_RMW_FIELD(ah, AR_PHY_TIMING5, + AR_PHY_TIMING5_CYCPWR_THR1, value); + +- if (IS_CHAN_HT40(ah->curchan)) +- REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, +- AR_PHY_EXT_TIMING5_CYCPWR_THR1, value); ++ REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, ++ AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); + + if (level != aniState->spurImmunityLevel) { + ath_dbg(common, ANI, |