diff options
Diffstat (limited to 'package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch')
| -rw-r--r-- | package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch index a402feb3cd..0b38901cd5 100644 --- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch +++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch @@ -12,9 +12,9 @@ More specifically, the following settings are now used: * up to 1152MHz: mul=3, div=2 (unchanged) * above 1152MHz: mul=4, div=2 (was: mul=2, div=1) ---- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -@@ -122,11 +122,12 @@ void clock_set_pll1(unsigned int clk) +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -91,11 +91,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; |