diff options
Diffstat (limited to 'package/boot/uboot-lantiq')
6 files changed, 416 insertions, 136 deletions
diff --git a/package/boot/uboot-lantiq/Makefile b/package/boot/uboot-lantiq/Makefile index 99b101f5f3..e224559af6 100644 --- a/package/boot/uboot-lantiq/Makefile +++ b/package/boot/uboot-lantiq/Makefile @@ -40,259 +40,278 @@ define uboot/arv4519pw_ram TITLE:=U-Boot for Arcadyan arv4519pw (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv4519pw/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV4519PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv4519pw_nor TITLE:=U-Boot for Arcadyan arv4519pw (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV4519PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv4519pw_brn TITLE:=U-Boot for Arcadyan arv4519pw (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV4519PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7510pw_ram TITLE:=U-Boot for Arcadyan arv7510pw (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv7510pw/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV4510PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7510pw_nor TITLE:=U-Boot for Arcadyan arv7510pw (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV4510PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7510pw_brn TITLE:=U-Boot for Arcadyan arv7510pw (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV4510PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7510pw22_ram TITLE:=U-Boot for Arcadyan arv7510pw22 (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv7510pw22/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV7510PW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7510pw22_nor TITLE:=U-Boot for Arcadyan arv7510pw22 (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV7510PW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7510pw22_brn TITLE:=U-Boot for Arcadyan arv7510pw22 (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV7510PW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7518pw_ram TITLE:=U-Boot for Arcadyan arv7518pw (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv7518pw/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV7518PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7518pw_nor TITLE:=U-Boot for Arcadyan arv7518pw (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV7518PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv7518pw_brn TITLE:=U-Boot for Arcadyan arv7518pw (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV7518PW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv752dpw_ram TITLE:=U-Boot for Arcadyan arv752dpw (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv752dpw/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV752DPW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv752dpw_nor TITLE:=U-Boot for Arcadyan arv752dpw (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV752DPW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv752dpw_brn TITLE:=U-Boot for Arcadyan arv752dpw (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV752DPW + DEPS:=@TARGET_lantiq_xway endef define uboot/arv752dpw22_ram TITLE:=U-Boot for Arcadyan arv752dpw22 (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv752dpw22/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV752DPW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv752dpw22_nor TITLE:=U-Boot for Arcadyan arv752dpw22 (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV752DPW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv752dpw22_brn TITLE:=U-Boot for Arcadyan arv752dpw22 (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV752DPW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv8539pw22_ram TITLE:=U-Boot for Speedport W 504V Typ A (RAM) SOC:=danube DDR_SETTINGS:=board/arcadyan/arv8539pw22/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ARV8539PW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv8539pw22_nor TITLE:=U-Boot for Speedport W 504V Typ A (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV8539PW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/arv8539pw22_brn TITLE:=U-Boot for Speedport W 504V Typ A (BRN) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ARV8539PW22 + DEPS:=@TARGET_lantiq_xway endef define uboot/gigasx76x_ram TITLE:=U-Boot for Siemens Gigaset sx76x (RAM) SOC:=danube DDR_SETTINGS:=board/gigaset/sx76x/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_GIGASX76X + DEPS:=@TARGET_lantiq_xway endef define uboot/gigasx76x_nor TITLE:=U-Boot for Siemens Gigaset sx76x (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_GIGASX76X + DEPS:=@TARGET_lantiq_xway endef define uboot/acmp252_ram TITLE:=U-Boot for AudioCodes MP-252 (RAM) SOC:=danube DDR_SETTINGS:=board/audiocodes/acmp252/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_ACMP252 + DEPS:=@TARGET_lantiq_xway endef define uboot/acmp252_nor TITLE:=U-Boot for AudioCodes MP-252 (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_ACMP252 + DEPS:=@TARGET_lantiq_xway endef define uboot/easy50712_ram TITLE:=U-Boot for Lantiq EASY50712 (RAM) SOC:=danube DDR_SETTINGS:=board/lantiq/easy50712/ddr_settings.h - DEPS:=@TARGET_lantiq_xway_EASY50712 + DEPS:=@TARGET_lantiq_xway endef define uboot/easy50712_nor TITLE:=U-Boot for Lantiq EASY50712 (NOR) SOC:=danube - DEPS:=@TARGET_lantiq_xway_EASY50712 + DEPS:=@TARGET_lantiq_xway endef define uboot/easy50712_norspl TITLE:=U-Boot for Lantiq EASY50712 (NOR SPL) SOC:=danube IMAGE:=u-boot.ltq.lzo.norspl - DEPS:=@TARGET_lantiq_xway_EASY50712 + DEPS:=@TARGET_lantiq_xway endef define uboot/easy80920_ram TITLE:=U-Boot for Lantiq EASY80920 (RAM) SOC:=vr9 DDR_SETTINGS:=board/lantiq/easy80920/ddr_settings.h - DEPS:=@(TARGET_lantiq_xrx200_EASY80920NOR||TARGET_lantiq_xrx200_EASY80920NAND) + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/easy80920_nor TITLE:=U-Boot for Lantiq EASY80920 (NOR) SOC:=vr9 - DEPS:=@(TARGET_lantiq_xrx200_EASY80920NOR||TARGET_lantiq_xrx200_EASY80920NAND) + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/easy80920_norspl TITLE:=U-Boot for Lantiq EASY80920 (NOR SPL) SOC:=vr9 IMAGE:=u-boot.ltq.lzo.norspl - DEPS:=@(TARGET_lantiq_xrx200_EASY80920NOR||TARGET_lantiq_xrx200_EASY80920NAND) + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/easy80920_sfspl TITLE:=U-Boot for Lantiq EASY80920 (SPI SPL) SOC:=vr9 IMAGE:=u-boot.ltq.lzo.sfspl - DEPS:=@(TARGET_lantiq_xrx200_EASY80920NOR||TARGET_lantiq_xrx200_EASY80920NAND) + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/fb3370_eva TITLE:=U-Boot for AVM FRITZ3370 (EVA) SOC:=vr9 - DEPS:=@TARGET_lantiq_xrx200_FRITZ3370 + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/fb3370_ram TITLE:=U-Boot for AVM FRITZ3370 (RAM) SOC:=vr9 DDR_SETTINGS:=board/avm/fb3370/ddr_settings.h - DEPS:=@TARGET_lantiq_xrx200_FRITZ3370 + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/fb3370_sfspl TITLE:=U-Boot for AVM FRITZ3370 (SPI SPL) SOC:=vr9 IMAGE:=u-boot.ltq.lzo.sfspl - DEPS:=@TARGET_lantiq_xrx200_FRITZ3370 + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/p2812hnufx_ram TITLE:=U-Boot for ZyXEL P-2812HNU-Fx (RAM) SOC:=vr9 DDR_SETTINGS:=board/zyxel/p2812hnufx/ddr_settings.h - DEPS:=@TARGET_lantiq_xrx200_P2812HNUF1||@TARGET_lantiq_xrx200_P2812HNUF3 + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/p2812hnufx_nandspl TITLE:=U-Boot for ZyXEL P-2812HNU-Fx (NAND SPL) SOC:=vr9 IMAGE:=u-boot.ltq.lzo.nandspl - DEPS:=@TARGET_lantiq_xrx200_P2812HNUF1||@TARGET_lantiq_xrx200_P2812HNUF3 + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/vgv7510kw22_brn TITLE:=U-Boot for Arcadyan VGV7510KW22 (BRN) SOC:=vr9 - DEPS:=@TARGET_lantiq_xrx200_VGV7510KW22NOR||@TARGET_lantiq_xrx200_VGV7510KW22BRN + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/vgv7510kw22_nor TITLE:=U-Boot for Arcadyan VGV7510KW22 (NOR) SOC:=vr9 - DEPS:=@TARGET_lantiq_xrx200_VGV7510KW22NOR||@TARGET_lantiq_xrx200_VGV7510KW22BRN + DEPS:=@TARGET_lantiq_xrx200 endef define uboot/vgv7510kw22_ram TITLE:=U-Boot for Arcadyan VGV7510KW22 (RAM) SOC:=vr9 DDR_SETTINGS:=board/arcadyan/vgv7510kw22/ddr_settings.h - DEPS:=@TARGET_lantiq_xrx200_VGV7510KW22NOR||@TARGET_lantiq_xrx200_VGV7510KW22BRN + DEPS:=@TARGET_lantiq_xrx200 +endef + +define uboot/vgv7519_brn + TITLE:=U-Boot for Arcadyan VGV7519 (BRN) + SOC:=vr9 + DEPS:=@TARGET_lantiq_xrx200 +endef + +define uboot/vgv7519_nor + TITLE:=U-Boot for Arcadyan VGV7519 (NOR) + SOC:=vr9 + DEPS:=@TARGET_lantiq_xrx200 +endef + +define uboot/vgv7519_ram + TITLE:=U-Boot for Arcadyan VGV7519 (RAM) + SOC:=vr9 + DDR_SETTINGS:=board/arcadyan/vgv7519/ddr_settings.h + DEPS:=@TARGET_lantiq_xrx200 endef UBOOTS:= \ @@ -309,7 +328,8 @@ UBOOTS:= \ easy80920_ram easy80920_nor easy80920_norspl easy80920_sfspl \ fb3370_eva fb3370_ram fb3370_sfspl \ p2812hnufx_ram p2812hnufx_nandspl \ - vgv7510kw22_brn vgv7510kw22_nor vgv7510kw22_ram + vgv7510kw22_brn vgv7510kw22_nor vgv7510kw22_ram \ + vgv7519_brn vgv7519_nor vgv7519_ram define Package/uboot/template define Package/uboot-lantiq-$(1) @@ -330,18 +350,19 @@ define BuildUBootPackage $(call Package/uboot/template,$(1),$(TITLE),$(DEPS)) endef -define CopyVR9Firmware - $(CP) $(FIRMWARE_LANTIQ_SOURCE)/vr9_phy$(1)_a$(2)x.bin \ +define CompressVR9Firmware + $(STAGING_DIR_HOST)/bin/lzma e \ + $(FIRMWARE_LANTIQ_SOURCE)/vr9_phy$(1)_a$(2)x.bin \ $(PKG_BUILD_DIR)/arch/mips/cpu/mips32/vrx200/fw_phy$(1)_a$(2)x.blob endef define Build/Prepare $(call Build/Prepare/Default) mkdir -p $(PKG_BUILD_DIR)/arch/mips/cpu/mips32/vrx200/ - $(call CopyVR9Firmware,11g,1) - $(call CopyVR9Firmware,11g,2) - $(call CopyVR9Firmware,22f,1) - $(call CopyVR9Firmware,22f,2) + $(call CompressVR9Firmware,11g,1) + $(call CompressVR9Firmware,11g,2) + $(call CompressVR9Firmware,22f,1) + $(call CompressVR9Firmware,22f,2) endef define Build/Configure diff --git a/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch index ef6eb1aaf9..5e6cf85985 100644 --- a/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch +++ b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch @@ -2381,7 +2381,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +} --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/ebu.c -@@ -0,0 +1,111 @@ +@@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * @@ -2424,7 +2424,13 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define ebu_region0_enable 0 +#endif + -+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) ++#if ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) ) ++#define ebu_region0_addrsel_mask 3 ++#else ++#define ebu_region0_addrsel_mask 1 ++#endif ++ ++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) || ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) ) +#define ebu_region1_enable 1 +#else +#define ebu_region1_enable 0 @@ -2460,7 +2466,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + * bank 0. + */ + ltq_writel(<q_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE | -+ EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN); ++ EBU_ADDRSEL_MASK(ebu_region0_addrsel_mask) | EBU_ADDRSEL_REGEN); + + ltq_writel(<q_ebu_regs->con_0, EBU_CON_AGEN_DEMUX | + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT | @@ -2474,17 +2480,26 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + if (ebu_region1_enable) { + /* + * Map EBU region 1 to range 0x14000000-0x13ffffff and enable -+ * region control. This supports NAND flash in bank 1. ++ * region control. This supports NAND flash in bank 1. (and NOR flash in bank 2) + */ + ltq_writel(<q_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE | + EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN); + -+ ltq_writel(<q_ebu_regs->con_1, EBU_CON_AGEN_DEMUX | -+ EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT | -+ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | -+ EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) | -+ EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) | -+ EBU_CON_CMULT_4); ++ if (ebu_region0_addrsel_mask == 1) ++ ltq_writel(<q_ebu_regs->con_1, EBU_CON_AGEN_DEMUX | ++ EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT | ++ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | ++ EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) | ++ EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) | ++ EBU_CON_CMULT_4); ++ ++ if (ebu_region0_addrsel_mask == 3) ++ ltq_writel(<q_ebu_regs->con_1, EBU_CON_AGEN_DEMUX | ++ EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT | ++ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | ++ EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) | ++ EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) | ++ EBU_CON_CMULT_16); + } else + ltq_clrbits(<q_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN); +} @@ -2495,7 +2510,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +} --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/gphy.c -@@ -0,0 +1,58 @@ +@@ -0,0 +1,68 @@ +/* + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * @@ -2506,17 +2521,23 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#include <asm/lantiq/io.h> +#include <asm/arch/soc.h> +#include <asm/arch/gphy.h> ++#include <lzma/LzmaTypes.h> ++#include <lzma/LzmaDec.h> ++#include <lzma/LzmaTools.h> + -+static inline void ltq_gphy_copy(const void *fw_start, const void *fw_end, ++static inline void ltq_gphy_decompress(const void *fw_start, const void *fw_end, + ulong dst_addr) +{ + const ulong fw_len = (ulong) fw_end - (ulong) fw_start; + const ulong addr = CKSEG1ADDR(dst_addr); + -+ debug("ltq_gphy_copy: addr %08lx, fw_start %p, fw_end %p\n", ++ debug("ltq_gphy_decompress: addr %08lx, fw_start %p, fw_end %p\n", + addr, fw_start, fw_end); + -+ memcpy((void *) addr, fw_start, fw_len); ++ SizeT lzma_len = 65536; ++ int ret = lzmaBuffToBuffDecompress( ++ (unsigned char *)addr, &lzma_len, ++ (unsigned char *)fw_start, fw_len); +} + +void ltq_gphy_phy11g_a1x_load(ulong addr) @@ -2524,8 +2545,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + extern ulong __ltq_fw_phy11g_a1x_start; + extern ulong __ltq_fw_phy11g_a1x_end; + -+ ltq_gphy_copy(&__ltq_fw_phy11g_a1x_start, &__ltq_fw_phy11g_a1x_end, -+ addr); ++ ltq_gphy_decompress(&__ltq_fw_phy11g_a1x_start, ++ &__ltq_fw_phy11g_a1x_end, ++ addr); +} + +void ltq_gphy_phy11g_a2x_load(ulong addr) @@ -2533,8 +2555,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + extern ulong __ltq_fw_phy11g_a2x_start; + extern ulong __ltq_fw_phy11g_a2x_end; + -+ ltq_gphy_copy(&__ltq_fw_phy11g_a2x_start, &__ltq_fw_phy11g_a2x_end, -+ addr); ++ ltq_gphy_decompress(&__ltq_fw_phy11g_a2x_start, ++ &__ltq_fw_phy11g_a2x_end, ++ addr); +} + +void ltq_gphy_phy22f_a1x_load(ulong addr) @@ -2542,8 +2565,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + extern ulong __ltq_fw_phy22f_a1x_start; + extern ulong __ltq_fw_phy22f_a1x_end; + -+ ltq_gphy_copy(&__ltq_fw_phy22f_a1x_start, &__ltq_fw_phy22f_a1x_end, -+ addr); ++ ltq_gphy_decompress(&__ltq_fw_phy22f_a1x_start, ++ &__ltq_fw_phy22f_a1x_end, ++ addr); +} + +void ltq_gphy_phy22f_a2x_load(ulong addr) @@ -2551,8 +2575,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + extern ulong __ltq_fw_phy22f_a2x_start; + extern ulong __ltq_fw_phy22f_a2x_end; + -+ ltq_gphy_copy(&__ltq_fw_phy22f_a2x_start, &__ltq_fw_phy22f_a2x_end, -+ addr); ++ ltq_gphy_decompress(&__ltq_fw_phy22f_a2x_start, ++ &__ltq_fw_phy22f_a2x_end, ++ addr); +} --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/gphy_fw.S @@ -3450,7 +3475,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#endif /* __DANUBE_SOC_H__ */ --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/config.h -@@ -0,0 +1,184 @@ +@@ -0,0 +1,187 @@ +/* + * Copyright (C) 2010 Lantiq Deutschland GmbH + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com @@ -3538,9 +3563,12 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +/* FLASH driver */ +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) ++#ifndef CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#endif +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_BASE 0xB0000000 ++#define CONFIG_SYS_FLASH2_BASE 0xB4000000 +#define CONFIG_FLASH_16BIT +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER diff --git a/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch b/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch index 6c9f14b043..8296f2c75e 100644 --- a/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch +++ b/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch @@ -19,7 +19,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> endif --- a/arch/mips/include/asm/arch-vrx200/config.h +++ b/arch/mips/include/asm/arch-vrx200/config.h -@@ -164,7 +164,7 @@ +@@ -167,7 +167,7 @@ #define CONFIG_SYS_TEXT_BASE 0xB0000000 #endif diff --git a/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch b/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch index 676ef12a8a..7c75fc4dd1 100644 --- a/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch +++ b/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch @@ -195,7 +195,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +/* Switch devices */ +#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_RTL8206 ++#define CONFIG_SWITCH_RTL8306 + +/* Environment */ +#if defined(CONFIG_SYS_BOOT_NOR) diff --git a/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch b/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch index adb894f018..14758fd8fc 100644 --- a/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch +++ b/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch @@ -30,7 +30,7 @@ +######################################################################### --- /dev/null +++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c -@@ -0,0 +1,136 @@ +@@ -0,0 +1,98 @@ +/* + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + * @@ -38,7 +38,6 @@ + */ + +#include <common.h> -+#include <spi.h> +#include <asm/gpio.h> +#include <asm/lantiq/eth.h> +#include <asm/lantiq/chipid.h> @@ -67,12 +66,8 @@ + +static void gpio_init(void) +{ -+ /* SPI CS 0.4 to serial flash */ -+ gpio_direction_output(10, 1); -+ + /* Turn on the green power LED */ + gpio_direction_output(GPIO_POWER_GREEN, 0); -+ gpio_set_value(GPIO_POWER_GREEN, 0); +} + +int board_early_init_f(void) @@ -134,39 +129,6 @@ + + return ltq_eth_initialize(ð_board_config); +} -+ -+int spi_cs_is_valid(unsigned int bus, unsigned int cs) -+{ -+ if (bus) -+ return 0; -+ -+ if (cs == 4) -+ return 1; -+ -+ return 0; -+} -+ -+void spi_cs_activate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 0); -+ break; -+ default: -+ break; -+ } -+} -+ -+void spi_cs_deactivate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 1); -+ break; -+ default: -+ break; -+ } -+} --- /dev/null +++ b/board/arcadyan/vgv7510kw22/config.mk @@ -0,0 +1,7 @@ @@ -220,7 +182,7 @@ +#define MC_CCR28_VALUE 0x0 +#define MC_CCR29_VALUE 0x0 +#define MC_CCR30_VALUE 0x798 -+#define MC_CCR31_VALUE 0x0 ++#define MC_CCR31_VALUE 0x2040F +#define MC_CCR32_VALUE 0x0 +#define MC_CCR33_VALUE 0x650000 +#define MC_CCR34_VALUE 0x200C8 @@ -236,7 +198,7 @@ +#define MC_CCR44_VALUE 0x566504 +#define MC_CCR45_VALUE 0x565F17 +#define MC_CCR46_VALUE 0x565F17 -+#define MC_CCR47_VALUE 0x0 ++#define MC_CCR47_VALUE 0x2040F +#define MC_CCR48_VALUE 0x0 +#define MC_CCR49_VALUE 0x0 +#define MC_CCR50_VALUE 0x0 @@ -253,10 +215,10 @@ +#define MC_CCR61_VALUE 0x4 --- a/boards.cfg +++ b/boards.cfg -@@ -542,6 +542,9 @@ +@@ -531,6 +531,9 @@ Active mips mips32 incai + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> - Active mips mips32 vrx200 arcadyan easybox904 easybox904_ram easybox904:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com> @@ -265,7 +227,7 @@ Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> --- /dev/null +++ b/include/configs/vgv7510kw22.h -@@ -0,0 +1,78 @@ +@@ -0,0 +1,59 @@ +/* + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + * @@ -286,33 +248,14 @@ + +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ + -+#define CONFIG_LTQ_SUPPORT_SPI_FLASH -+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29GL128EL parallel flash */ -+ -+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ -+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ -+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ -+ -+#define CONFIG_SPL_SPI_BUS 0 -+#define CONFIG_SPL_SPI_CS 4 -+#define CONFIG_SPL_SPI_MAX_HZ 25000000 -+#define CONFIG_SPL_SPI_MODE 0 -+ -+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ -+ +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */ + -+/* Environment */ -+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS -+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS -+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ -+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE -+ +#if defined(CONFIG_SYS_BOOT_BRN) +#define CONFIG_SYS_TEXT_BASE 0x80002000 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_DISABLE_CACHE +#define CONFIG_ENV_IS_NOWHERE ++#define CONFIG_ENV_OVERWRITE 1 +#elif defined(CONFIG_SYS_BOOT_NOR) +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE diff --git a/package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch b/package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch new file mode 100644 index 0000000000..952bdce0cc --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch @@ -0,0 +1,288 @@ +--- /dev/null ++++ b/board/arcadyan/vgv7519/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/vgv7519/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/vgv7519/ddr_settings.h +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me> ++ * ++ * The values have been extracted from original brnboot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x100 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000401 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x2040F ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x2040F ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +--- /dev/null ++++ b/board/arcadyan/vgv7519/vgv7519.c +@@ -0,0 +1,95 @@ ++/* ++ * This file is released under the terms of GPL v2 and any later version. ++ * See the file COPYING in the root directory of the source tree for details. ++ * ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ */ ++ ++#include <common.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/chipid.h> ++#include <asm/lantiq/cpu.h> ++#include <asm/arch/gphy.h> ++ ++#if defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#elif defined(CONFIG_SYS_BOOT_NOR) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++#define GPIO_GPHY_RESET 47 ++ ++static void gpio_init(void) ++{ ++ /* Disable reset on external eth PHY */ ++ gpio_direction_output(GPIO_GPHY_RESET, 1); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ ++ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ ++ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC3: unused */ ++ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ ++ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ if (ltq_chip_version_get() == 1) ++ ltq_gphy_phy22f_a1x_load(fw_addr); ++ else ++ ltq_gphy_phy22f_a2x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} +--- a/boards.cfg ++++ b/boards.cfg +@@ -537,6 +537,9 @@ Active mips mips32 incai + Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com> + Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com> + Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com> ++Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_brn vgv7519:SYS_BOOT_BRN Mathias Kresin <dev@kresin.me> ++Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_nor vgv7519:SYS_BOOT_NOR Eddi De Pieri <eddi@depieri.net> ++Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_ram vgv7519:SYS_BOOT_RAM Eddi De Pieri <eddi@depieri.net> + Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +--- /dev/null ++++ b/include/configs/vgv7519.h +@@ -0,0 +1,62 @@ ++/* ++ * This file is released under the terms of GPL v2 and any later version. ++ * See the file COPYING in the root directory of the source tree for details. ++ * ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "VGV7519" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan VGV7519" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ ++#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH2_BASE } ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_IS_NOWHERE ++#define CONFIG_ENV_OVERWRITE 1 ++#elif defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (384 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++ ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ "kernel_addr=0xB0080000\0" ++ ++#endif /* __CONFIG_H */ |