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| author | John Crispin <blogic@openwrt.org> | 2013-07-22 13:52:32 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-07-22 13:52:32 +0000 |
| commit | 020c18be59888443948895663079574ce54d2fd8 (patch) | |
| tree | 24f396509057722aa70d908e7be2132777b9dcf5 /target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | |
| parent | bd2cbce22c162e9bc56b27bbcda95b7877b3a89f (diff) | |
| download | master-187ad058-020c18be59888443948895663079574ce54d2fd8.tar.gz master-187ad058-020c18be59888443948895663079574ce54d2fd8.tar.bz2 master-187ad058-020c18be59888443948895663079574ce54d2fd8.zip | |
ralink: set v3.10 as default
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37497 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch deleted file mode 100644 index fb0cd7bcdb..0000000000 --- a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 17d26ed75f0981cdc497f9062aec5f66d3c44d88 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Thu, 23 May 2013 18:46:25 +0200 -Subject: [PATCH 139/164] MIPS: ralink: add spi clock definition to mt7620a - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/mt7620.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -183,6 +183,7 @@ void __init ralink_clk_init(void) - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", 40000000); - ralink_clk_add("10000500.uart", 40000000); -+ ralink_clk_add("10000b00.spi", 40000000); - ralink_clk_add("10000c00.uartlite", 40000000); - } - |