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authorJohn Crispin <blogic@openwrt.org>2013-06-23 15:50:49 +0000
committerJohn Crispin <blogic@openwrt.org>2013-06-23 15:50:49 +0000
commit5f6caa26e516e578be547df489d2ae8900da58a5 (patch)
tree48ec89a784c8c7ebb382cb8486ed0021a07b6109 /target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
parent21ee9d504d834133a99fecfd36f1a65f8df8c096 (diff)
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ralink: update patches
Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37016 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch')
-rw-r--r--target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch39
1 files changed, 39 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch b/target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
new file mode 100644
index 0000000000..d17c227649
--- /dev/null
+++ b/target/linux/ramips/patches-3.8/0048-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
@@ -0,0 +1,39 @@
+From 8c2015a6eed656d8578a78e392625869ba8f9bb4 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 20 May 2013 20:30:11 +0200
+Subject: [PATCH 48/79] MIPS: ralink: make mt7620 ram detect verbose
+
+Make the code print which of SDRAM, DDR1 or DDR2 was detected.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index 98ddb93..28350d0 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+
+ switch (dram_type) {
+ case SYSCFG0_DRAM_TYPE_SDRAM:
++ pr_info("Board has SDRAM\n");
+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+ break;
+
+ case SYSCFG0_DRAM_TYPE_DDR1:
++ pr_info("Board has DDR1\n");
+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+ break;
+
+ case SYSCFG0_DRAM_TYPE_DDR2:
++ pr_info("Board has DDR2\n");
+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+ break;
+--
+1.7.10.4
+