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| author | John Crispin <blogic@openwrt.org> | 2015-11-21 21:25:20 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2015-11-21 21:25:20 +0000 |
| commit | a667d6367a7ffca1f025c0a4a8a51617e88182a9 (patch) | |
| tree | 5ad42192eccbc6135b4fef646e579bdee3f6f4f4 /target/linux/netlogic/Makefile | |
| parent | 450e9f1f563f5371069015d9806ac2527fd0c99b (diff) | |
| download | master-187ad058-a667d6367a7ffca1f025c0a4a8a51617e88182a9.tar.gz master-187ad058-a667d6367a7ffca1f025c0a4a8a51617e88182a9.tar.bz2 master-187ad058-a667d6367a7ffca1f025c0a4a8a51617e88182a9.zip | |
lantiq: tweak DWC2 default parameters
This patch improves the default configuration of DWC2 on lantiq SoCs
somewhat:
* Set maximum packet count to largest allowed value by the DWC2 (511)
* Use 16-bit DMA bursts
* Divide fifo buffers more evenly
Default fifo buffer sizes from original ltq-hcd driver seem really
irrational. For example according to DWC2 data book rxfifo size of 240
will not fit even a single full length USB packet. On the other hand
non-periodic tx fifo size of 240 is more than enough to fit one complete
packet.
Change the sizes around to improve the situation and to fix some issues
especially with isochronous USB transfers.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47563 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/netlogic/Makefile')
0 files changed, 0 insertions, 0 deletions