diff options
author | Luka Perkov <luka@openwrt.org> | 2013-09-27 01:52:28 +0000 |
---|---|---|
committer | Luka Perkov <luka@openwrt.org> | 2013-09-27 01:52:28 +0000 |
commit | e0e36cb5d987c6515f2b9c6ed4e4df6c84f18541 (patch) | |
tree | 90b32b568e37dd68264a916ebdcdb807897b2451 /target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch | |
parent | 896a6277b51daa7f253d849a7a501959dfcf705e (diff) | |
download | master-187ad058-e0e36cb5d987c6515f2b9c6ed4e4df6c84f18541.tar.gz master-187ad058-e0e36cb5d987c6515f2b9c6ed4e4df6c84f18541.tar.bz2 master-187ad058-e0e36cb5d987c6515f2b9c6ed4e4df6c84f18541.zip |
mvebu: drop 3.8 support
Signed-off-by: Luka Perkov <luka@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38225 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch')
-rw-r--r-- | target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch b/target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch deleted file mode 100644 index af15d4b85d..0000000000 --- a/target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch +++ /dev/null @@ -1,44 +0,0 @@ -The Marvell evaluation board (DB) for the Armada XP SoC has 6 -physicals full-size PCIe slots, so we enable the corresponding PCIe -interfaces in the Device Tree. - -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - arch/arm/boot/dts/armada-xp-db.dts | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/arch/arm/boot/dts/armada-xp-db.dts -+++ b/arch/arm/boot/dts/armada-xp-db.dts -@@ -109,5 +109,32 @@ - usb@d0052000 { - status = "okay"; - }; -+ -+ pcie-controller { -+ status = "okay"; -+ -+ /* -+ * All 6 slots are physically present as -+ * standard PCIe slots on the board. -+ */ -+ pcie0.0@0xd0040000 { -+ status = "okay"; -+ }; -+ pcie0.1@0xd0044000 { -+ status = "okay"; -+ }; -+ pcie0.2@0xd0048000 { -+ status = "okay"; -+ }; -+ pcie0.3@0xd004C000 { -+ status = "okay"; -+ }; -+ pcie2@0xd0042000 { -+ status = "okay"; -+ }; -+ pcie3@0xd0082000 { -+ status = "okay"; -+ }; -+ }; - }; - }; |