mvebu: drop 3.10 support

Signed-off-by: Luka Perkov <luka@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41406 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 127 deletions

diff --git a/target/linux/mvebu/patches-3.10/0122-mtd-nand-pxa3xx-Move-cached-registers-to-info-struct.patch b/target/linux/mvebu/patches-3.10/0122-mtd-nand-pxa3xx-Move-cached-registers-to-info-struct.patch
deleted file mode 100644
index a5109f0ce7..0000000000
--- a/target/linux/mvebu/patches-3.10/0122-mtd-nand-pxa3xx-Move-cached-registers-to-info-struct.patch
+++ /dev/null
@@ -1,127 +0,0 @@
-From 5c5367d7f9ad835b3b8a2dddfbe90e4c6e669084 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Date: Mon, 12 Aug 2013 14:14:55 -0300
-Subject: [PATCH 122/203] mtd: nand: pxa3xx: Move cached registers to info
- structure
-
-This registers are not per-chip (aka host) but controller-wide,
-so it's better to store them in the global 'info' structure.
-
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
-Tested-by: Daniel Mack <zonque@gmail.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/pxa3xx_nand.c | 36 +++++++++++++++++-------------------
- 1 file changed, 17 insertions(+), 19 deletions(-)
-
---- a/drivers/mtd/nand/pxa3xx_nand.c
-+++ b/drivers/mtd/nand/pxa3xx_nand.c
-@@ -144,10 +144,6 @@ struct pxa3xx_nand_host {
- 	unsigned int		row_addr_cycles;
- 	size_t			read_id_bytes;
- 
--	/* cached register value */
--	uint32_t		reg_ndcr;
--	uint32_t		ndtr0cs0;
--	uint32_t		ndtr1cs0;
- };
- 
- struct pxa3xx_nand_info {
-@@ -193,6 +189,11 @@ struct pxa3xx_nand_info {
- 	unsigned int		oob_size;
- 	int 			retcode;
- 
-+	/* cached register value */
-+	uint32_t		reg_ndcr;
-+	uint32_t		ndtr0cs0;
-+	uint32_t		ndtr1cs0;
-+
- 	/* generated NDCBx register values */
- 	uint32_t		ndcb0;
- 	uint32_t		ndcb1;
-@@ -258,8 +259,8 @@ static void pxa3xx_nand_set_timing(struc
- 		NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
- 		NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
- 
--	host->ndtr0cs0 = ndtr0;
--	host->ndtr1cs0 = ndtr1;
-+	info->ndtr0cs0 = ndtr0;
-+	info->ndtr1cs0 = ndtr1;
- 	nand_writel(info, NDTR0CS0, ndtr0);
- 	nand_writel(info, NDTR1CS0, ndtr1);
- }
-@@ -267,7 +268,7 @@ static void pxa3xx_nand_set_timing(struc
- static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
- {
- 	struct pxa3xx_nand_host *host = info->host[info->cs];
--	int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
-+	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
- 
- 	info->data_size = host->page_size;
- 	if (!oob_enable) {
-@@ -293,10 +294,9 @@ static void pxa3xx_set_datasize(struct p
-  */
- static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
- {
--	struct pxa3xx_nand_host *host = info->host[info->cs];
- 	uint32_t ndcr;
- 
--	ndcr = host->reg_ndcr;
-+	ndcr = info->reg_ndcr;
- 
- 	if (info->use_ecc)
- 		ndcr |= NDCR_ECC_EN;
-@@ -683,7 +683,7 @@ static void pxa3xx_nand_cmdfunc(struct m
- 	 * "byte" address into a "word" address appropriate
- 	 * for indexing a word-oriented device
- 	 */
--	if (host->reg_ndcr & NDCR_DWIDTH_M)
-+	if (info->reg_ndcr & NDCR_DWIDTH_M)
- 		column /= 2;
- 
- 	/*
-@@ -693,8 +693,8 @@ static void pxa3xx_nand_cmdfunc(struct m
- 	 */
- 	if (info->cs != host->cs) {
- 		info->cs = host->cs;
--		nand_writel(info, NDTR0CS0, host->ndtr0cs0);
--		nand_writel(info, NDTR1CS0, host->ndtr1cs0);
-+		nand_writel(info, NDTR0CS0, info->ndtr0cs0);
-+		nand_writel(info, NDTR1CS0, info->ndtr1cs0);
- 	}
- 
- 	info->state = STATE_PREPARED;
-@@ -870,7 +870,7 @@ static int pxa3xx_nand_config_flash(stru
- 	ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
- 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */
- 
--	host->reg_ndcr = ndcr;
-+	info->reg_ndcr = ndcr;
- 
- 	pxa3xx_nand_set_timing(host, f->timing);
- 	return 0;
-@@ -893,11 +893,9 @@ static int pxa3xx_nand_detect_config(str
- 		host->read_id_bytes = 2;
- 	}
- 
--	host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
--
--	host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
--	host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
--
-+	info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
-+	info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
-+	info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
- 	return 0;
- }
- 
-@@ -1044,7 +1042,7 @@ KEEP_CONFIG:
- 	chip->ecc.size = host->page_size;
- 	chip->ecc.strength = 1;
- 
--	if (host->reg_ndcr & NDCR_DWIDTH_M)
-+	if (info->reg_ndcr & NDCR_DWIDTH_M)
- 		chip->options |= NAND_BUSWIDTH_16;
- 
- 	if (nand_scan_ident(mtd, 1, def))