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| author | John Crispin <blogic@openwrt.org> | 2016-05-02 18:50:31 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2016-06-19 19:18:47 +0200 |
| commit | f9151d154f7a6f0523dd09f348178bbe788b8ef0 (patch) | |
| tree | b5f77ed411374492931c452d69ffe2a96bbee65b /target/linux/lantiq | |
| parent | 989f7773a636eabea1e9210cb81b990b4042c322 (diff) | |
| download | master-187ad058-f9151d154f7a6f0523dd09f348178bbe788b8ef0.tar.gz master-187ad058-f9151d154f7a6f0523dd09f348178bbe788b8ef0.tar.bz2 master-187ad058-f9151d154f7a6f0523dd09f348178bbe788b8ef0.zip | |
lantiq: add device tree binding for the phy clock source
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49283 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq')
| -rw-r--r-- | target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch new file mode 100644 index 0000000000..227d1cf25a --- /dev/null +++ b/target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -423,6 +423,20 @@ static void clkdev_add_clkout(void) + } + } + ++static void set_phy_clock_source(struct device_node *np_cgu) ++{ ++ u32 phy_clk_src, ifcc; ++ ++ if (!np_cgu) ++ return; ++ ++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) ++ return; ++ ++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); ++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); ++} ++ + /* bring up all register ranges that we need for basic system control */ + void __init ltq_soc_init(void) + { +@@ -608,4 +622,6 @@ void __init ltq_soc_init(void) + + if (of_machine_is_compatible("lantiq,vr9")) + xbar_fpi_burst_disable(); ++ ++ set_phy_clock_source(np_cgu); + } |