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author | John Crispin <blogic@openwrt.org> | 2010-12-12 22:57:16 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2010-12-12 22:57:16 +0000 |
commit | 3a8cab4295251305a2b8fba4f5ba3b9340915957 (patch) | |
tree | 24f859f8849a0d5180c1bef85c758ce70aa43c80 /target/linux/lantiq/patches/010-mips_clocksource_init_war.patch | |
parent | 30ce14b5fcdfbc1d739af351ab01e8d3e287f174 (diff) | |
download | master-187ad058-3a8cab4295251305a2b8fba4f5ba3b9340915957.tar.gz master-187ad058-3a8cab4295251305a2b8fba4f5ba3b9340915957.tar.bz2 master-187ad058-3a8cab4295251305a2b8fba4f5ba3b9340915957.zip |
[lantiq] adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24526 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/patches/010-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/lantiq/patches/010-mips_clocksource_init_war.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches/010-mips_clocksource_init_war.patch b/target/linux/lantiq/patches/010-mips_clocksource_init_war.patch new file mode 100644 index 0000000000..81eabc6dcd --- /dev/null +++ b/target/linux/lantiq/patches/010-mips_clocksource_init_war.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -22,6 +22,22 @@ + + #ifndef CONFIG_MIPS_MT_SMTC + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } |