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authorJohn Crispin <blogic@openwrt.org>2013-09-17 21:46:10 +0000
committerJohn Crispin <blogic@openwrt.org>2013-09-17 21:46:10 +0000
commit718e5fe27e81d84b1e08ac57486433e4267ae74c (patch)
treebc305784e92a261300f79b3999710bc635e947c3 /target/linux/lantiq/patches-3.10/0017-MTD-lantiq-xway-remove-endless-loop.patch
parente032c312184f85253ca93a46f47cfae2f3f64f00 (diff)
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lantiq: add v3.10 patches
Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38031 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/patches-3.10/0017-MTD-lantiq-xway-remove-endless-loop.patch')
-rw-r--r--target/linux/lantiq/patches-3.10/0017-MTD-lantiq-xway-remove-endless-loop.patch46
1 files changed, 46 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.10/0017-MTD-lantiq-xway-remove-endless-loop.patch b/target/linux/lantiq/patches-3.10/0017-MTD-lantiq-xway-remove-endless-loop.patch
new file mode 100644
index 0000000000..726207150f
--- /dev/null
+++ b/target/linux/lantiq/patches-3.10/0017-MTD-lantiq-xway-remove-endless-loop.patch
@@ -0,0 +1,46 @@
+From 43c13af427d6900c7ce0111c53d3a428146b3f50 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 18:02:06 +0200
+Subject: [PATCH 17/34] MTD: lantiq: xway: remove endless loop
+
+The reset loop logic could run into a endless loop. Lets fix it as requested.
+
+--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/xway_nand.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
+index 7f2bdd1..8d14f1b 100644
+--- a/drivers/mtd/nand/xway_nand.c
++++ b/drivers/mtd/nand/xway_nand.c
+@@ -59,16 +59,22 @@ static u32 xway_latchcmd;
+ static void xway_reset_chip(struct nand_chip *chip)
+ {
+ unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
++ unsigned long timeout;
+ unsigned long flags;
+
+ nandaddr &= ~NAND_WRITE_ADDR;
+ nandaddr |= NAND_WRITE_CMD;
+
+ /* finish with a reset */
++ timeout = jiffies + msecs_to_jiffies(20);
++
+ spin_lock_irqsave(&ebu_lock, flags);
+ writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
+- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+- ;
++ do {
++ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
++ break;
++ cond_resched();
++ } while (!time_after_eq(jiffies, timeout));
+ spin_unlock_irqrestore(&ebu_lock, flags);
+ }
+
+--
+1.7.10.4
+