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| author | Felix Fietkau <nbd@openwrt.org> | 2015-11-21 10:55:05 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-11-21 10:55:05 +0000 |
| commit | e42003b7e7444236ca8dbe7c5d777ff02eda4694 (patch) | |
| tree | 92a48c4dea1f786eb72e223860c7edf41d72539c /target/linux/ipq806x | |
| parent | 6253ade3515c13b8f03c162618e5a5ee9f4e2936 (diff) | |
| download | master-187ad058-e42003b7e7444236ca8dbe7c5d777ff02eda4694.tar.gz master-187ad058-e42003b7e7444236ca8dbe7c5d777ff02eda4694.tar.bz2 master-187ad058-e42003b7e7444236ca8dbe7c5d777ff02eda4694.zip | |
ipq806x: reduce PCIe buffer size setting to fix potential data corruption issues
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47545 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ipq806x')
| -rw-r--r-- | target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch | 4 | ||||
| -rw-r--r-- | target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch index 11c9810fe2..c0b65c712b 100644 --- a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch +++ b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch @@ -229,8 +229,8 @@ + writel(upper_32_bits(pp->mem_bus_addr), + pcie->dbi + PCIE20_PLR_IATU_UTAR); + -+ /* 1K PCIE buffer setting */ -+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ /* 256B PCIE buffer setting */ ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + diff --git a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch index 11c9810fe2..c0b65c712b 100644 --- a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch +++ b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch @@ -229,8 +229,8 @@ + writel(upper_32_bits(pp->mem_bus_addr), + pcie->dbi + PCIE20_PLR_IATU_UTAR); + -+ /* 1K PCIE buffer setting */ -+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ /* 256B PCIE buffer setting */ ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + |