ipq806x: Add support for IPQ806x chip family

Patches are generated using the "format-patch" command from the
following location:
*https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base
*rev=0771849495b4128cac2faf7d49c85c729fc48b20
Patches numbered 76/77/102/103 have already been integrated in 3.14.12,
so they're not in this list.

All these patches are either integrated are pending integration into
kernel.org, therefore these patches should go away once the kernel
gets upgraded to 3.16.

Support is currently limited to AP148 board but can be extended to other
platforms in the future.

These changes do not cover ethernet connectivity.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42334 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 82 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches/0178-dmaengine-qcom_adm-Add-device-tree-binding.patch b/target/linux/ipq806x/patches/0178-dmaengine-qcom_adm-Add-device-tree-binding.patch
new file mode 100644
index 0000000000..a80fcfa7f5
--- /dev/null
+++ b/target/linux/ipq806x/patches/0178-dmaengine-qcom_adm-Add-device-tree-binding.patch
@@ -0,0 +1,82 @@
+From 331294fa5c703536e27b79e9c112d162393f725a Mon Sep 17 00:00:00 2001
+From: Andy Gross <agross@codeaurora.org>
+Date: Thu, 26 Jun 2014 13:55:10 -0500
+Subject: [PATCH 178/182] dmaengine: qcom_adm: Add device tree binding
+
+Add device tree binding support for the QCOM ADM DMA driver.
+
+Signed-off-by: Andy Gross <agross@codeaurora.org>
+---
+ Documentation/devicetree/bindings/dma/qcom_adm.txt |   60 ++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
+
+diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt
+new file mode 100644
+index 0000000..7f05cb5
+--- /dev/null
++++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
+@@ -0,0 +1,60 @@
++QCOM ADM DMA Controller
++
++Required properties:
++- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
++- reg: Address range for DMA registers
++- interrupts: Should contain one interrupt shared by all channels
++- #dma-cells: must be <2>.  First cell denotes the channel number.  Second cell
++  denotes CRCI (client rate control interface) flow control assignment.
++- clocks: Should contain the core clock and interface clock.
++- clock-names: Must contain "core" for the core clock and "iface" for the
++  interface clock.
++- resets: Must contain an entry for each entry in reset names.
++- reset-names: Must include the following entries:
++  - clk
++  - c0
++  - c1
++  - c2
++- qcom,ee: indicates the security domain identifier used in the secure world.
++
++Example:
++		adm_dma: dma@18300000 {
++			compatible = "qcom,adm";
++			reg = <0x18300000 0x100000>;
++			interrupts = <0 170 0>;
++			#dma-cells = <2>;
++
++			clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
++			clock-names = "core", "iface";
++
++			resets = <&gcc ADM0_RESET>,
++				<&gcc ADM0_C0_RESET>,
++				<&gcc ADM0_C1_RESET>,
++				<&gcc ADM0_C2_RESET>;
++			reset-names = "clk", "c0", "c1", "c2";
++			qcom,ee = <0>;
++		};
++
++DMA clients must use the format descripted in the dma.txt file, using a three
++cell specifier for each channel.
++
++Each dmas request consists of 3 cells:
++ 1. phandle pointing to the DMA controller
++ 2. channel number
++ 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 0.
++
++Example:
++
++	spi4: spi@1a280000 {
++		status = "ok";
++		spi-max-frequency = <50000000>;
++
++		pinctrl-0 = <&spi_pins>;
++		pinctrl-names = "default";
++
++		cs-gpios = <&qcom_pinmux 20 0>;
++
++		dmas = <&adm_dma 6 9>,
++			<&adm_dma 5 10>;
++		dma-names = "rx", "tx";
++	};
+-- 
+1.7.10.4
+