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author | John Crispin <blogic@openwrt.org> | 2015-08-17 06:17:47 +0000 |
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committer | John Crispin <blogic@openwrt.org> | 2015-08-17 06:17:47 +0000 |
commit | 8c106ba3553b7da7386d13efa5f3454c9639f919 (patch) | |
tree | 1be94bd4deb1d10cc5781935e92ef98a1e0da1b9 /target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch | |
parent | a44d24b7952cd6107c653d764270df8f71ca2451 (diff) | |
download | master-187ad058-8c106ba3553b7da7386d13efa5f3454c9639f919.tar.gz master-187ad058-8c106ba3553b7da7386d13efa5f3454c9639f919.tar.bz2 master-187ad058-8c106ba3553b7da7386d13efa5f3454c9639f919.zip |
ipq806x: add hwspinlock support
This change cherry-picks the following 3 changes from linux-next:
*fb7737 hwspinlock/core: add device tree support
*19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block
*bd5717 hwspinlock: qcom: Correct msb in regmap_field
We're also adding a patch to add the hardware spinlock device nodes on
IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch).
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46655 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch')
-rw-r--r-- | target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch index 59b7fcc1b3..d01e5a8ede 100644 --- a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch +++ b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -359,15 +359,21 @@ +@@ -364,15 +364,21 @@ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, @@ -26,7 +26,7 @@ status = "disabled"; }; -@@ -400,15 +406,21 @@ +@@ -405,15 +411,21 @@ clocks = <&gcc PCIE_1_A_CLK>, <&gcc PCIE_1_H_CLK>, @@ -52,7 +52,7 @@ status = "disabled"; }; -@@ -441,15 +453,21 @@ +@@ -446,15 +458,21 @@ clocks = <&gcc PCIE_2_A_CLK>, <&gcc PCIE_2_H_CLK>, |