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authorLuka Perkov <luka@openwrt.org>2014-08-11 20:35:10 +0000
committerLuka Perkov <luka@openwrt.org>2014-08-11 20:35:10 +0000
commit6b2145fca6698555c8f1e5c5373a440f2088e7a3 (patch)
treea64f715cba41287389630147006415e6c2a25bdb /target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
parent7d82dc4a822da3d708c566444de19f81c0b0137f (diff)
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imx6: kernel: add GW16083 Ethernet Expansion Mezzanine support
The GW16083 Ethernet Expansion Mezzanine adds the following to supported Gateworks baseboards: * 7-port Ethernet Switch * 4x RJ45 ports (ENET1-4) supporing 802.11af/at PoE (with optional PoE module) * 2x RJ45 ports or SFP module (ENET5-6) (auto-selected) This series adds support for a phy driver that adds support for ENET5/ENET6 PHY adding initialization for those PHY's and a polling mechanism that detects SFP insertion and configuration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42147 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch')
-rw-r--r--target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch129
1 files changed, 129 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
new file mode 100644
index 0000000000..9de5dfe44a
--- /dev/null
+++ b/target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch
@@ -0,0 +1,129 @@
+Author: Tim Harvey <tharvey@gateworks.com>
+Date: Thu May 15 00:12:26 2014 -0700
+
+ net: igb: add i210/i211 support for phy read/write
+
+ The i210/i211 uses the MDICNFG register for the phy address instead of the
+ MDIC register.
+
+ Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+
+--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
++++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
+@@ -139,7 +139,7 @@ out:
+ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
+ {
+ struct e1000_phy_info *phy = &hw->phy;
+- u32 i, mdic = 0;
++ u32 i, mdicnfg, mdic = 0;
+ s32 ret_val = 0;
+
+ if (offset > MAX_PHY_REG_ADDRESS) {
+@@ -152,11 +152,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+ * Control register. The MAC will take care of interfacing with the
+ * PHY to retrieve the desired data.
+ */
+- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+- (phy->addr << E1000_MDIC_PHY_SHIFT) |
+- (E1000_MDIC_OP_READ));
++ switch (hw->mac.type) {
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
++ (E1000_MDIC_OP_READ));
++ break;
++ default:
++ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
++ (phy->addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_READ));
++ break;
++ }
+
+ wr32(E1000_MDIC, mdic);
++ wrfl();
+
+ /* Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+@@ -181,6 +195,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+ *data = (u16) mdic;
+
+ out:
++ switch (hw->mac.type) {
++ /* restore MDICNFG to have phy's addr */
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ break;
++ default:
++ break;
++ }
+ return ret_val;
+ }
+
+@@ -195,7 +221,7 @@ out:
+ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
+ {
+ struct e1000_phy_info *phy = &hw->phy;
+- u32 i, mdic = 0;
++ u32 i, mdicnfg, mdic = 0;
+ s32 ret_val = 0;
+
+ if (offset > MAX_PHY_REG_ADDRESS) {
+@@ -208,12 +234,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+ * Control register. The MAC will take care of interfacing with the
+ * PHY to retrieve the desired data.
+ */
+- mdic = (((u32)data) |
+- (offset << E1000_MDIC_REG_SHIFT) |
+- (phy->addr << E1000_MDIC_PHY_SHIFT) |
+- (E1000_MDIC_OP_WRITE));
++ switch (hw->mac.type) {
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ mdic = (((u32)data) |
++ (offset << E1000_MDIC_REG_SHIFT) |
++ (E1000_MDIC_OP_WRITE));
++ break;
++ default:
++ mdic = (((u32)data) |
++ (offset << E1000_MDIC_REG_SHIFT) |
++ (phy->addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_WRITE));
++ break;
++ }
+
+ wr32(E1000_MDIC, mdic);
++ wrfl();
+
+ /* Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+@@ -237,6 +278,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+ }
+
+ out:
++ switch (hw->mac.type) {
++ /* restore MDICNFG to have phy's addr */
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ break;
++ default:
++ break;
++ }
+ return ret_val;
+ }
+