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| author | Luka Perkov <luka@openwrt.org> | 2014-02-20 17:26:10 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2014-02-20 17:26:10 +0000 |
| commit | 48d02a5a97e4d853b14d9663eb5def66ede80e63 (patch) | |
| tree | 0d0256e4f7adf38e45cbc655fbc31096ae739c99 /target/linux/imx6/patches-3.10/112-gw51xx.patch | |
| parent | 91ea98bba889cf4bd86644677272208f401ebf5c (diff) | |
| download | master-187ad058-48d02a5a97e4d853b14d9663eb5def66ede80e63.tar.gz master-187ad058-48d02a5a97e4d853b14d9663eb5def66ede80e63.tar.bz2 master-187ad058-48d02a5a97e4d853b14d9663eb5def66ede80e63.zip | |
imx6: update Ventana dts
Update the Ventana device-tree to match upstream:
- Add IMX6Q/IMX6DL variants for GW54xx/GW53xx/GW52xx/GW51xx
- align pinctrl with upstream
- consolidate multiple patches into one
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39644 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/imx6/patches-3.10/112-gw51xx.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.10/112-gw51xx.patch | 161 |
1 files changed, 0 insertions, 161 deletions
diff --git a/target/linux/imx6/patches-3.10/112-gw51xx.patch b/target/linux/imx6/patches-3.10/112-gw51xx.patch deleted file mode 100644 index e222984920..0000000000 --- a/target/linux/imx6/patches-3.10/112-gw51xx.patch +++ /dev/null @@ -1,161 +0,0 @@ ---- a/arch/arm/boot/dts/imx6dl.dtsi -+++ b/arch/arm/boot/dts/imx6dl.dtsi -@@ -105,6 +105,95 @@ - }; - }; - -+ gpmi-nand { -+ pinctrl_gpmi_nand_1: gpmi-nand-1 { -+ fsl,pins = < -+ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 -+ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 -+ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 -+ >; -+ }; -+ -+ /* No strobe */ -+ pinctrl_gpmi_nand_2: gpmi-nand-2 { -+ fsl,pins = < -+ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 -+ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 -+ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; -+ }; -+ -+ i2c1 { -+ pinctrl_i2c1_1: i2c1grp-1 { -+ fsl,pins = < -+ MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ }; -+ -+ i2c2 { -+ pinctrl_i2c2_1: i2c2grp-1 { -+ fsl,pins = < -+ MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 -+ MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ pinctrl_i2c2_2: i2c2grp-2 { -+ fsl,pins = < -+ MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ }; -+ -+ i2c3 { -+ pinctrl_i2c3_1: i2c3grp-1 { -+ fsl,pins = < -+ MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 -+ MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ pinctrl_i2c3_2: i2c3grp-2 { -+ fsl,pins = < -+ MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ }; -+ - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < -@@ -112,6 +201,36 @@ - MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; -+ pinctrl_uart1_2: uart1grp-2 { -+ fsl,pins = < -+ MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ >; -+ }; -+ }; -+ -+ uart2 { -+ pinctrl_uart2_1: uart2grp-1 { -+ fsl,pins = < -+ MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ pinctrl_uart2_2: uart2grp-2 { -+ fsl,pins = < -+ MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 -+ MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 -+ >; -+ }; -+ }; -+ -+ uart3 { -+ pinctrl_uart3_1: uart3grp-1 { -+ fsl,pins = < -+ MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 -+ MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 -+ >; -+ }; - }; - - uart4 { -@@ -122,6 +241,15 @@ - >; - }; - }; -+ -+ uart5 { -+ pinctrl_uart5_1: uart5grp-1 { -+ fsl,pins = < -+ MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ }; - - usbotg { - pinctrl_usbotg_2: usbotggrp-2 { ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ - imx6q-arm2.dtb \ - imx6q-gw5400-a.dtb \ - imx6q-gw54xx.dtb \ -+ imx6dl-gw51xx.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb \ |