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author | OpenWrt Developers <openwrt-devel@openwrt.org> | 2008-12-16 14:07:55 +0000 |
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committer | OpenWrt Developers <openwrt-devel@openwrt.org> | 2008-12-16 14:07:55 +0000 |
commit | 269f4bbc24d3061764c9ee37f2da31d3228bec9a (patch) | |
tree | 07dc39510a01c7dca62cd1d2a794c1800ecab6c2 /target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch | |
parent | 9c2776b652d64041f98918b86f4554b7b678067c (diff) | |
download | master-187ad058-269f4bbc24d3061764c9ee37f2da31d3228bec9a.tar.gz master-187ad058-269f4bbc24d3061764c9ee37f2da31d3228bec9a.tar.bz2 master-187ad058-269f4bbc24d3061764c9ee37f2da31d3228bec9a.zip |
[ifxmips] cleanup sources and prepare for 2.6.27
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13660 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch new file mode 100644 index 0000000000..ac44c308fa --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.27/010-mips_clocksource_init_war.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -21,6 +21,22 @@ + + #ifndef CONFIG_MIPS_MT_SMTC + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } |