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| author | John Crispin <blogic@openwrt.org> | 2008-05-11 14:13:15 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2008-05-11 14:13:15 +0000 |
| commit | 6725612c18fa6dc796ea875981eec8adffacdf9f (patch) | |
| tree | 0657d1101a95896275d2f9cb22d757cd7b794fb8 /target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings.h | |
| parent | 748fe624cee148cfbce99ed90949ede0abd9bbbb (diff) | |
| download | master-187ad058-6725612c18fa6dc796ea875981eec8adffacdf9f.tar.gz master-187ad058-6725612c18fa6dc796ea875981eec8adffacdf9f.tar.bz2 master-187ad058-6725612c18fa6dc796ea875981eec8adffacdf9f.zip | |
add u-boot sources for danube
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11108 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings.h')
| -rw-r--r-- | target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings.h b/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings.h new file mode 100644 index 0000000000..cecd279b39 --- /dev/null +++ b/target/linux/ifxmips/image/u-boot/files/board/danube/ddr_settings.h @@ -0,0 +1,50 @@ +/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1d00
+#define MC_DC22_VALUE 0x1d1d
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5e /* was 0x7f */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
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