diff options
author | John Crispin <blogic@openwrt.org> | 2008-06-07 16:04:31 +0000 |
---|---|---|
committer | John Crispin <blogic@openwrt.org> | 2008-06-07 16:04:31 +0000 |
commit | c3347ecaa8b85e2f39bedf2494f14b4dbcb7776e (patch) | |
tree | a3fe62b2ed00258db4c9a03427a08dea6f4d8e2f /target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c | |
parent | 35429cda0dee9d6a6eba563cc01437228f205e85 (diff) | |
download | master-187ad058-c3347ecaa8b85e2f39bedf2494f14b4dbcb7776e.tar.gz master-187ad058-c3347ecaa8b85e2f39bedf2494f14b4dbcb7776e.tar.bz2 master-187ad058-c3347ecaa8b85e2f39bedf2494f14b4dbcb7776e.zip |
fixes ifxmips pci support and adds GENERIC_GPIO
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11396 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c')
-rw-r--r-- | target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c index 33cdc83867..c62936046d 100644 --- a/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c +++ b/target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c @@ -60,8 +60,8 @@ ifxmips_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data) ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) | phy_data; - while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); - writel(val, IFXMIPS_PPE32_MDIO_ACC); + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); + ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); } unsigned short @@ -71,9 +71,9 @@ ifxmips_read_mdio (u32 phy_addr, u32 phy_reg) ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET); - writel(val, IFXMIPS_PPE32_MDIO_ACC); - while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){}; - val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; + ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); + while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){}; + val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; return val; } @@ -374,13 +374,13 @@ ifxmips_sw_chip_init (int mode) ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE); if(mode == REV_MII_MODE) - writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG); + ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG); else if(mode == MII_MODE) - writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG); + ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG); - writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL); + ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL); - writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG); + ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG); wmb(); } |