diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2012-12-25 18:45:31 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-12-25 18:45:31 +0000 |
| commit | 2e918d7ca50862d2f0477969c542a30130f63764 (patch) | |
| tree | 1e4ae48a592b780f83c5ae9ce4560af4627e8a6c /target/linux/generic/files/drivers/net/phy | |
| parent | 17bb18be18bd5d88146d893d0f8ac63833f3f2c8 (diff) | |
| download | master-187ad058-2e918d7ca50862d2f0477969c542a30130f63764.tar.gz master-187ad058-2e918d7ca50862d2f0477969c542a30130f63764.tar.bz2 master-187ad058-2e918d7ca50862d2f0477969c542a30130f63764.zip | |
generic: ar8216: add sgmii_delay_en field to ar8327_platform_data
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34881 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.c | 3 | ||||
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c index 8dcaf0a483..b274b13662 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.c +++ b/target/linux/generic/files/drivers/net/phy/ar8216.c @@ -917,6 +917,9 @@ ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) if (cfg->txclk_delay_en) t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; + if (cfg->sgmii_delay_en) + t |= AR8327_PAD_SGMII_DELAY_EN; + break; case AR8327_PAD_MAC2PHY_MII: diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index d464101e8f..c83bf44e18 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -281,6 +281,7 @@ #define AR8327_PAD_PHYX_GMII_EN BIT(16) #define AR8327_PAD_PHYX_RGMII_EN BIT(17) #define AR8327_PAD_PHYX_MII_EN BIT(18) +#define AR8327_PAD_SGMII_DELAY_EN BIT(19) #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) |