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authorFelix Fietkau <nbd@openwrt.org>2015-01-24 19:42:06 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-01-24 19:42:06 +0000
commit4bfb00d02d6537fee9557d989601bc235fa81116 (patch)
treea0afadd52a96538fee50829f7c06d84fce4b2cb2 /target/linux/generic/files/drivers/net/phy/ar8216.h
parent95e0b242c20cd8fe135e989cdad76405d38cca25 (diff)
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ar8216: add swconfig attribute to display ARL table on AR8327/AR8337
Add global read-only swconfig attribute "arl_table" to display the address resolution table. So far the chip-specific part is implemented for AR8327/AR8337 only as I don't have the datasheets for the other AR8XXX chips. Successfully tested on TL-WDR4300 (AR8327rev2) and TL-WDR4900 (AR8327rev4). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44104 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/ar8216.h')
-rw-r--r--target/linux/generic/files/drivers/net/phy/ar8216.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h
index 77df506256..7163cf430f 100644
--- a/target/linux/generic/files/drivers/net/phy/ar8216.h
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.h
@@ -337,6 +337,18 @@ enum {
AR8XXX_VER_AR8337 = 0x13,
};
+#define AR8XXX_NUM_ARL_RECORDS 100
+
+enum arl_op {
+ AR8XXX_ARL_INITIALIZE,
+ AR8XXX_ARL_GET_NEXT
+};
+
+struct arl_entry {
+ u8 port;
+ u8 mac[6];
+};
+
struct ar8xxx_priv;
struct ar8xxx_mib_desc {
@@ -372,6 +384,8 @@ struct ar8xxx_chip {
void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
void (*set_mirror_regs)(struct ar8xxx_priv *priv);
+ void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
+ u32 *status, enum arl_op op);
int (*sw_hw_apply)(struct switch_dev *dev);
const struct ar8xxx_mib_desc *mib_decs;
@@ -396,6 +410,8 @@ struct ar8xxx_priv {
bool initialized;
bool port4_phy;
char buf[2048];
+ struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
+ char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
bool link_up[AR8X16_MAX_PORTS];
bool init;
@@ -423,6 +439,10 @@ struct ar8xxx_priv {
};
u32
+mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
+void
+mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
+u32
ar8xxx_read(struct ar8xxx_priv *priv, int reg);
void
ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
@@ -500,6 +520,10 @@ ar8xxx_sw_get_port_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val);
int
+ar8xxx_sw_get_arl_table(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val);
+int
ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
static inline struct ar8xxx_priv *
@@ -556,6 +580,19 @@ ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
}
static inline void
+split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
+{
+ regaddr >>= 1;
+ *r1 = regaddr & 0x1e;
+
+ regaddr >>= 5;
+ *r2 = regaddr & 0x7;
+
+ regaddr >>= 3;
+ *page = regaddr & 0x1ff;
+}
+
+static inline void
wait_for_page_switch(void)
{
udelay(5);